CN1284002C

CN1284002C - Nuclear magnetic resonance pulse sequency generator

Info

Publication number: CN1284002C
Application number: CN 03150591
Authority: CN
Inventors: 徐勤; 蒋瑜; 辛立静; 李鲠颖
Original assignee: East China Normal University
Current assignee: East China Normal University; Donghua University
Priority date: 2003-08-27
Filing date: 2003-08-27
Publication date: 2006-11-08
Anticipated expiration: 2023-08-27
Also published as: CN1515911A

Abstract

The present invention relates to a nuclear magnetic resonance spectrometer and a magnetic resonance imaging instrument, more specifically a nuclear magnetic resonance pulse sequence generator which is mainly composed of a field programmable gate array FPGA, a large capacity static memory (SRAM) and a PCI-CAN interface chip. The present invention has the advantages of simple structure, realization of controlling the output of a pulse sequence by means of the single chip FPGA, improvement of integrity and reliability, simplification of system design, reduction of production cost, convenient operation, high universality, high data transmission speed, small volume, etc. When the present invention is plugged, the present invention can be used. In addition, the present invention can be widely applied to various nuclear magnetic resonance devices and magnetic resonance imaging instruments.

Description

A kind of nuclear magnetic resonance pulse sequence generator

Technical field

The present invention relates to nuclear magnetic resonance spectrometer and magnetic resonance imager class, relate to a kind of nuclear magnetic resonance pulse sequence generator concretely.

Background technology

In nuclear magnetic resonance spectrometer, pulse-series generator is used to produce the required pulse train of nuclear magnetic resonance experiment as one of core component of spectrometer, and its function mainly is to control the co-ordination of parts such as receiver in the spectrometer system, transmitter and radio frequency source in real time.At present, the nuclear magnetic resonance pulse sequence generator mainly is to be realized by multimicroprocessor and traditional discrete digital logical circuit.Still there is following problem in these systems: 1, use the multimode multiple microprocessor structure, system complex and lack dirigibility.2, use traditional discrete digital logical circuit, function is single relatively.3, realize the timing controlled of pulse train by timer in software interruption or the inquiry microprocessor, timing is more coarse, temporal resolution is lower.4, adopt some special purpose interface or poor-performing interface as RS232 serial port etc.,, lack real-time though interface is simple.Although in application number 00128171.2 in the technology of disclosed a kind of nuclear magnetic resonance pulse programming controller, also used programmable logic controller (PLC) spare, only as the converter of bus interface, but the core of pulse-series generator still is the host-guest architecture of multimicroprocessor to its purposes.

Summary of the invention

The objective of the invention is according to above-mentioned the deficiencies in the prior art part, have high-performance for modern nuclear magnetic resonance spectrometer and NMR imaging instrument provide, a low cost, nuclear magnetic resonance pulse sequence generator that versatility is good, easy to use.

The realization of the object of the invention is finished by following technical scheme:

The present invention mainly forms (as Fig. 1) by on-site programmable gate array FPGA (Field Programmable Gate Array), high capacity static memory (SRAM) and PCI (Peripheral Component Interconnect) interface chip.

In nuclear magnetic resonance pulse sequence, the variation each time of any execution unit duty of spectrometer, sampling starts, opens or closes radio frequency gate etc. as receiver, we think the change of an incident, simultaneously, the time interval between the adjacent events then is the time that previous incident continues, and the change of these parts duties can add that corresponding time-delay controls by the set of number level.Fig. 2 has provided 90 degree monopulse nuclear magnetic resonance pulse sequences with two-way output, FC0 is radio-frequency transmissions (RF) passage, the control radio-frequency (RF) switch produces excitation pulse, T1 is a pulse width, and FC1 is for triggering sampling channel, and the T3 time begins to trigger sampling, the finish time, sampling was finished, at initial time T0, the output of each passage is low level, and T2 is the dead time of spectrometer system receiving cable.Thus, we can obtain the relation table (as Fig. 3) of time and incident.

Definite kernel magnetic resonance pulse sequence at first in use, convert thereof into the relation table of Time And Event and deposit static memory on the plate in by the software on the main frame, like this, we can be by the logic state machine of FPGA inside, in each finish time time, export next incident successively.

We have adopted FPGA to realize the logic function (as Fig. 4) of pulse-series generator in the present invention.Wherein inner main functional modules comprises: address decoder, address counter, address selector, data selector, finite state machine, timer, output register and control register.The generation of whole pulse train is realized by the finite state machine of FPGA inside that mainly at first, main frame is determining that good nuclear magnetic resonance pulse sequence is converted into incident and time relationship table, by pci bus, sends in the static memory of pulse-series generator; The function of code translator is that static memory and control register are carried out address assignment, so that host service function; Come the initialization pulse sequencer by the control register that FPGA inside is set then, the state machine of FPGA inside reads in digital level value and the corresponding delay value of waiting to export particular event in advance by address selector and data selector; When main frame sent startup command, FPGA started inner timer; When timer overflows, incident value to be exported is write output register, address counter increases progressively one simultaneously, chooses the internal storage location of next resting period and incident; When the incident value of reading in advance was specific end mark, state machine jumped to reset mode from normal burst sequence output services state, the control register by FPGA inside is set or by interrupting notice main frame (as Fig. 5).Because the topworks of this pulse-series generator is all finished by hardware, between execution pulse train period of output, do not need the intervention of main frame at whole pulse-series generator, and do not have extra timing error, realized the pulse output of higher time precision.

Pci bridge chip is as the express passway of main frame and pulse-series generator transmission data.It for this reason device easy, quick, general calculation machine interface is provided.Static memory on the plate is mainly used to deposit pulse train incident and the time corresponding value that is passed down by main frame.

The present invention has following advantage: total system mainly is made of FPGA, pci interface chip and three core devices of internal memory, and structure is very simple, has very high cost performance simultaneously.

1, compare with multimode, multi-processor structure that traditional pulse-series generator adopts, this device has only used the output of monolithic FPGA gating pulse sequence, has improved integrated level and reliability, has simplified system design, has reduced production cost simultaneously.

2, native system has adopted pci bus as interface, can be connected with present main flow PC or industrial computer easily, can be compatible and do not need to insert specific slot with the slot of miscellaneous equipment, and can with other equipment concurrent workings.It has advantages such as plug and play, easy to use, highly versatile, data rate be fast.

3, this device has adopted finite state machine and timer based on programmable hardware to produce pulse train, has replaced to control the scheme that timer internal produces pulse train by the software that moves in the microprocessor in the prior art.It can produce the nuclear magnetic resonance pulse sequence with accurate timing, high time resolution, does not need the intervention of main frame when producing pulse train, can reduce unnecessary software overhead, further reduces system cost.

4, adopt the incident and the time corresponding value of monolithic high capacity static memory storage nuclear magnetic resonance pulse sequence, make the pulse-series generator designs simplification.

5, used flexible novel programmable logic device (PLD)-FPGA, total system can be carried out easily at system upgrade according to user's demand.

6, this device volume is small and exquisite, and has very strong versatility, can be widely used in all kinds of nuclear magnetic resonance equipments and magnetic resonance imager.

Summary of drawings

Accompanying drawing 1 is formed synoptic diagram for the present invention;

Accompanying drawing 2 has 90 degree monopulse nuclear magnetic resonance pulse sequences of two-way output for the present invention;

Accompanying drawing 3 is the relation table of the represented Time And Event of Fig. 2 of the present invention;

Accompanying drawing 4 is FPGA internal logic block diagram of the present invention;

Accompanying drawing 5 is FPGA state machine workflow diagram of the present invention;

Concrete technical scheme

Feature of the present invention and other correlated characteristic are described in further detail by example below in conjunction with accompanying drawing, so that technician's of the same trade understanding:

Shown in Fig. 1-5, total system work mainly is made up of FPGA, high capacity static memory and pci interface chip.

FPGA reads in the pulse train parameter from internal memory and exports required nuclear magnetic resonance pulse sequence and control the collaborative work of spectrometer miscellaneous part through its inner state machine core mainly as the generating unit of pulse train.In order to make more steady operation of finite state machine, we have adopted hardware description language (Very High SpeedIntegrated circuit Hardware Description Language, VHDL) in conjunction with the device property of FPGA, state machine is carried out the one-hot coding, and when state machine design, considered redundancy for illegal error condition.In addition, use the VHDL hardware description language to carry out the comprehensive of large scale digital system logic, simplified design greatly, saved design and cost of development.FPGA the initial phase of pulse-series generator also as plate on the interface chip of static memory and pci bus, be responsible for the pulse train parameter on the main frame is imported into static memory on the plate apace.In order further to improve integrated level, also made up control register in FPGA inside and be used to start nuclear magnetic resonance pulse sequence, and carried out in whole pulse train and to notify main frame by interruption or mode that zone bit is set after finishing.For the requirement of the medical magnetic resonance imaging (MRI) that adapts to more complicated, on FPGA, also reserved the input control line that can accept the TTL signal, be used to import outer synchronous signal (after one's own heart electric switch control etc.).In order to make whole nuclear magnetic resonance spectrometer on reality is used, have more security, in case of emergency, in case need the anxious whole NMR system of stopping, can suddenly stop control bit in the control register of set FPGA inside, all pulse train trigger ports all are changed to low level immediately, close might produce harm passage as radio frequency gate, high power gradient amplifier etc., can guarantee the particularly safety of medical magnetic resonance imaging of whole NMR system like this.

Pci interface chip is at the pulse-series generator initial phase, mainly be responsible for when start according to user's needs to the required resource of operating system application as application memory-mapped and interruption etc., from the pci bus protocol conversion static memory on the microprocessor read-write sequence tablet of standard then required experimental data (time-event form), also be responsible for the control register of read-write FPGA inside simultaneously, start bit be set or transmit end signal to main frame by the PCI interruption.

High capacity static memory on the plate then is used for storage time incident form, and its data layout as shown in Figure 3.In ending place of whole time-event form, we have defined one group of special incident value as end mark, when state machine reads in this state whole nuclear magnetic resonance pulse sequence that just automatically resets.

Total system only is made up of FPGA, pci interface chip, high capacity static memory, and is very succinct, reduced production cost, improved the reliability of system simultaneously.

When pulse-series generator was worked, at first main frame by pci bus, was sent into corresponding nuclear magnetic resonance pulse sequence parameter in the static memory on the plate; Then, start nuclear magnetic resonance pulse sequence by the starting state position that FPGA internal control register is set, when state machine is read pulse train end mark in the internal memory, state machine resets, all trigger action output lines all are low level, and by interrupting or set end mark position notice main frame.In case of emergency, also can stop control bit, promptly stop whole nuclear magnetic resonance pulse sequence, protect the safety of whole NMR system by being provided with suddenly.

Claims

1, a kind of nuclear magnetic resonance pulse sequence generator, it is characterized in that this generator is mainly by on-site programmable gate array FPGA, high capacity static memory and pci interface chip are formed, fpga chip as nuclear magnetic resonance pulse sequence generator core, its inner main functional module mainly comprises: address decoder, address counter, address selector, data selector, finite state machine, timer, output register and control register, adopt finite state machine as the nuclear magnetic resonance pulse sequence generating unit in FPGA inside, at first, determine that good nuclear magnetic resonance pulse sequence is converted into incident and time relationship table by main frame, pass through pci bus, send in the described static memory, described code translator carries out address assignment to described static memory and control register, carry out initialization by control register then, finite state machine is by address selector and data selector, read in digital level value and the corresponding delay value of waiting to export particular event in advance, when main frame sends startup command, FPGA starts inner timer, when timer overflows, incident value to be exported is write output register, address counter increases progressively one simultaneously, choose the internal storage location of next resting period or incident, when running into end mark or the anxious control bit that stops when being set, pulse-series generator resets, and all trigger ports are changed to low level.

2, a kind of nuclear magnetic resonance pulse sequence generator according to claim 1 is characterized in that, during carrying out pulse train, pulse train is produced by hardware fully, does not need the intervention of main frame.