CN102315840B - Pulse generation method and device - Google Patents
Pulse generation method and device Download PDFInfo
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- CN102315840B CN102315840B CN201110111259.XA CN201110111259A CN102315840B CN 102315840 B CN102315840 B CN 102315840B CN 201110111259 A CN201110111259 A CN 201110111259A CN 102315840 B CN102315840 B CN 102315840B
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Abstract
The invention discloses a pulse generation method and device. The pulse generation device disclosed by the invention can simultaneously obtain a waveform control command and a waveform command for carrying out decoding processing; a plurality of decoders simultaneously decode and represent line production; in the decoding of a production line mode, the decoding course of one piece of command is carried out in multiple steps; each level of circuit only processes one step in the multiple steps, thus the multiple levels of circuits simultaneously process the multiple commands on a production line; t the waveform is output while the command is analyzed, thereby enabling one piece of command which can be analyzed in multiple clock periods to be shortened to one average clock period; and time for decoding is shortened and the decoding efficiency is improved, thereby improving speed and frequency for generating pulse waveform.
Description
Technical field
The application relates to digit pulse technical field, particularly relates to a kind of method for generating pulse and device.
Background technology
Programmable pulse producing method, to describe impulse waveform by the mode that is similar to computer programming language, pulse generating unit receives the Waveform Control code of certain forms, by resolving described Waveform Control code and carrying out corresponding operation, common Waveform Control mode has order, circulation, redirect etc., can realize by Waveform Control code the Waveform Control of more complicated.
The pulse generator that prior art is used, Waveform Control code and waveform are stored in same instruction, like this, when resolving control code, can not produce new waveform, can only after being parsed, control code obtain, resolve waveform output, thereby limited the minimum pulse sheet length of its generation, also just cannot produce Pulse of Arbitrary waveform according to minimum clock cycle, such as the operating frequency of SpinCore company is 500MHz Pulse Blaster ESR-PRO pulse generator is minimum under normal mode to produce the impulse waveform that width is 12ns, because, this kind of pulse generating device needs at least 6 work clock cycles to decode, so also just restrict programmable pulse producing method and produced the speed of pulse, the frequency of the pulse producing is lower.At present, urgently to be resolved hurrily is how to improve the speed that programmable pulse producing method produces pulse.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present application provides a kind of method for generating pulse and device, and to improve the frequency of the pulse of programmable way generation, technical scheme is as follows:
, the method comprises:
A, the current Waveform Control instruction resolve obtaining, obtain the memory address of the waveform instruction that current Waveform Control instruction carries and the memory address of next Waveform Control instruction;
The waveform instruction that B, parsing are obtained according to the memory address of described waveform instruction, obtain output waveform, meanwhile, next Waveform Control instruction that the memory address of described next the Waveform Control instruction of foundation obtains, as current Waveform Control instruction, is returned to execution step A.
Preferably, Waveform Control instruction is stored at least one first storage area in advance, waveform instruction is stored at least one second storage area.
Preferably, in advance Waveform Control instruction and waveform instruction are stored in a storage area with a plurality of independently reading-writing port.
Preferably, in advance Waveform Control instruction and waveform instruction are stored in a plurality of storage areas with a plurality of independently reading-writing port, described in each, storage area at least comprises two independent reading-writing port, and stores Waveform Control instruction and waveform instruction simultaneously.
, comprising: memory cell, Waveform Control instruction decoder and waveform decoder, wherein, in described memory cell, store Waveform Control instruction and waveform instruction, comprise the first reading-writing port and the second reading-writing port;
Described memory cell is sent to described Waveform Control instruction decoder by the first reading-writing port by current Waveform Control instruction and resolves, obtain the memory address of the corresponding waveform instruction of described current Waveform Control instruction, and the memory address of next Waveform Control instruction;
Described memory cell is by the first reading-writing port, next Waveform Control instruction that the memory address of next the Waveform Control instruction providing according to described Waveform Control instruction decoder is obtained, as current Waveform Control instruction, being sent to described Waveform Control instruction decoder resolves, and by the second reading-writing port, the waveform instruction that the memory address of the waveform instruction providing according to described Waveform Control instruction decoder is obtained, be sent to waveform decoder and resolve, obtain output waveform.
Preferably, described memory cell comprises: at least one stores the storage area of Waveform Control instruction and waveform instruction simultaneously, and this storage area has independently the first reading-writing port and the second reading-writing port.
Preferably, described memory cell comprises: at least one is connected with described the first reading-writing port, and for the first storage area of stored waveform control command, and at least one is connected with described the second reading-writing port, and for the second storage area of stored waveform instruction.
Preferably, above-mentioned pulse generating device, also comprises: microcontroller, and for carrying out initialization, and the operating state of controlling described Waveform Control instruction decoder and waveform decoder and memory cell.
Apply the technical scheme that above the application provides, pulse generating device can obtain Waveform Control instruction and the waveform instruction processing of decoding simultaneously, a plurality of decoders are decoded simultaneously and are presented continuous productive process, the decoding of pipeline system is the decode procedure of an instruction to be divided into multistep carry out, every one-level circuit is only processed a step wherein, multi-level pmultistage circuit is processed a plurality of instructions on streamline simultaneously like this, realization is when resolving instruction, output waveform, an instruction could resolving within a plurality of clock cycle before making shortened in the average clock cycle, reduced the decoding time used, improved decoding efficiency, and then improved speed and the frequency that impulse waveform produces.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flow chart of a kind of method for generating pulse of the embodiment of the present application;
Fig. 2 is the structural representation of a kind of pulse generating device of the embodiment of the present application;
Fig. 3 a is the structural representation of the another kind of pulse generating device of the embodiment of the present application;
Fig. 3 b is the structural representation of the another kind of pulse generating device of the embodiment of the present application.
Embodiment
The embodiment of the present application provides a kind of method for generating pulse, for improving the pulse of programmable pulse producing method, produce speed and frequency, Waveform Control instruction can be obtained simultaneously and dissection process is carried out in waveform instruction, and adopt pipeline system to resolve instruction, because pipeline system is the decode procedure of an instruction to be divided into multistep carry out, every one-level circuit is only processed a step wherein, multi-level pmultistage circuit is processed many instructions on streamline simultaneously like this, an instruction could resolving in the cycle at a plurality of work clock before making shortens to an average work clock cycle and completes with interior.Reduce the decoding time used, improved decoding efficiency, and then improved speed and frequency that impulse waveform produces.
For the application's above-mentioned purpose, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the application is described in further detail.
Referring to Fig. 1, Fig. 1 is the schematic flow sheet of a kind of method for generating pulse of the embodiment of the present application, and the method comprises:
S101, resolves the current Waveform Control instruction obtaining, and obtains the waveform instruction memory address that described current Waveform Control instruction is carried, and the memory address of next Waveform Control instruction.
According to the memory address of Waveform Control instruction, obtain corresponding Waveform Control instruction, it is current Waveform Control instruction, resolve described current Waveform Control instruction, obtain the memory address of the corresponding waveform instruction of current Waveform Control instruction, and the memory address of next Waveform Control instruction.
Concrete, described Waveform Control instruction comprises three partial informations respectively: memory address, the cyclical information of the waveform instruction that this Waveform Control instruction is entrained, and cycle-index information, wherein:
When described cyclical information is circulation execution information, the memory address of next Waveform Control instruction is, the memory address of current Waveform Control instruction adds 1.Number of times is carried out in the circulation that described cycle-index information is Waveform Control instruction;
Concrete, such as the cyclical information in the instruction of i bar Waveform Control is for starting circulation, cyclical information in the instruction of n bar Waveform Control is for stopping circulation, circulation is carried out the instruction of i+1 bar Waveform Control to all instructions of n bar Waveform Control instruction, cycle-index, i.e. information corresponding to cycle-index in the instruction of i bar Waveform Control.
When described cyclical information is carried out the information of Waveform Control instruction for not circulating, described cycle-index information is specially the memory address of next Waveform Control instruction.
S102, resolve the waveform instruction according to the memory address acquisition of described waveform instruction, obtain output waveform, simultaneously, memory address according to described next Waveform Control instruction obtains next Waveform Control instruction, as current Waveform Control instruction, return and carry out S101, until all Waveform Control instructions all execute.
During concrete enforcement, resolve the memory address of the resulting waveform instruction of described current Waveform Control instruction, it is address block address, the initial address and the address block length that comprise waveform instruction place storage area, memory cell can not directly utilize address block to carry out addressing, therefore this address block information analysis need to be become memory cell can directly carry out the addressing address of addressing, and then obtain waveform instruction according to this addressing address.
Resolve described waveform instruction, obtain output waveform, and the lasting time of this waveform, the impulse waveform that obtains wishing output.
Meanwhile, according to the memory address of next Waveform Control instruction, obtain next Waveform Control instruction, as current Waveform Control instruction, return to execution step S101, until all Waveform Control instructions have all been resolved.
As shown in the above, the obtaining of Waveform Control instruction, parsing and waveform instruction obtain, resolve and present pipeline system, on this streamline, can process many Waveform Control instructions simultaneously, until resolved END instruction, stop, i.e. all Waveform Control instructions have all been resolved.
Below with an instantiation explanation pipeline system resolving:
Obtain the instruction of article one Waveform Control, as current Waveform Control instruction, resolve the memory address that the instruction of article one Waveform Control obtains the first waveform instruction, and the memory address of second Waveform Control instruction.
Memory address according to described the first waveform instruction obtains the first waveform instruction, and resolves this first waveform instruction, obtains output waveform.When obtaining and resolving described the first waveform instruction, according to the memory address of described second Waveform Control instruction, obtain the instruction of second Waveform Control, as current Waveform Control instruction, carry out dissection process.
In other words, the obtaining of the obtaining of second Waveform Control instruction, dissection process and the first waveform instruction, dissection process can be carried out simultaneously, the rest may be inferred, the processing of many Waveform Control instructions and waveform instruction presents continuous productive process, pipeline system decoding is that the decode procedure of an instruction is divided into multistep, by multi-level pmultistage circuit, is undertaken, every one-level circuit is only processed a step wherein, and multi-level pmultistage circuit is processed a plurality of instructions on streamline simultaneously like this.Instruction decoding streamline in the present embodiment can be processed Waveform Control instruction and waveform instruction simultaneously, thereby shortened the processing latency of every Waveform Control instruction, the dissection process time of an instruction was shortened in the average clock cycle by a plurality of clock cycle, in macroscopic view, see, shortened the time of output pulse waveform, therefore, speed and frequency that pulse produces have been improved.
Preferably, in the embodiment of the corresponding method for generating pulse of Fig. 1, for realizing, obtain Waveform Control instruction and dissection process is carried out in waveform instruction simultaneously, can Waveform Control instruction be stored at least one first storage area in advance, waveform instruction is stored at least one second storage area.
It will be appreciated by persons skilled in the art that storage area is the least unit that forms memory cell, memory cell consists of at least one storage area.Therefore, described at least one first storage area and described at least one second storage area can form one or more memory cell.
When being a plurality of memory cell, can be that described the first storage area forms at least one memory cell, described the second storage area forms at least one memory cell, can also be, includes the first storage area and two kinds of storage areas of the second storage area in each memory cell.
Preferably, in the method for generating pulse embodiment shown in Fig. 1, for realizing, obtain Waveform Control instruction and dissection process is carried out in waveform instruction simultaneously, all right, in advance by Waveform Control instruction and waveform instruction, store in a storage area with a plurality of independently reading-writing port, a plurality of reading-writing port share a storage area simultaneously, but read-write operation between a plurality of port is independent of each other;
It will be appreciated by persons skilled in the art that and can store all Waveform Control instructions and waveform instruction with a plurality of storage areas with a plurality of independent reading-writing port.
Corresponding to embodiment of the method above, the application also provides a kind of pulse generating device, and referring to Fig. 2, this device comprises: memory cell 1, Waveform Control instruction decoder 2, waveform decoder 3.
Memory cell 1, for the storage area of stored waveform control command and waveform instruction, comprises the first reading-writing port and the second reading-writing port.
Described memory cell 1 is sent to described Waveform Control instruction decoder 2 by the first reading-writing port by current Waveform Control instruction and resolves, obtain the memory address of the corresponding waveform instruction of described current Waveform Control instruction, and the memory address of next waveform instruction;
Next Waveform Control instruction that described memory cell 1 by the first reading-writing port, the memory address of next the Waveform Control instruction providing according to described Waveform Control instruction decoder 2 is provided, as current Waveform Control instruction, being sent to Waveform Control instruction decoder 2 resolves, and by the second reading-writing port, the waveform instruction that the memory address of the waveform instruction providing according to described Waveform Control instruction decoder 2 is obtained, be sent to waveform decoder 3 and resolve, obtain output waveform.
During concrete enforcement, dissection process is carried out in the current Waveform Control instruction of 2 pairs of acquisitions of Waveform Control instruction decoder, obtains the waveform instruction memory address that described current Waveform Control instruction is carried, and the memory address of next Waveform Control instruction.
Described Waveform Control instruction comprises three partial informations, respectively: and memory address, the cyclical information of the waveform instruction that this Waveform Control instruction is entrained, and cycle-index information, wherein:
When described cyclical information is circulation execution information, the memory address of next Waveform Control instruction is, the memory address of current Waveform Control instruction adds 1, and number of times is carried out in the circulation that described cycle-index information is Waveform Control instruction;
Concrete, such as the cyclical information in the instruction of i bar Waveform Control is for starting circulation, cyclical information in the instruction of n bar Waveform Control is for stopping circulation, circulation is carried out the instruction of i+1 bar Waveform Control to all instructions of n bar Waveform Control instruction, cycle-index, i.e. information corresponding to cycle-index in the instruction of i bar Waveform Control.
When described cyclical information is carried out the information of Waveform Control instruction for not circulating, described cycle-index information is specially the memory address of next Waveform Control instruction.
Concrete, described Waveform Control instruction decoder 2 is resolved described current Waveform Control instruction, obtain the memory address of waveform instruction and the memory address of next Waveform Control instruction that current Waveform Control instruction is carried, be back to described memory cell 1, memory cell 1 is according to the memory address of described waveform instruction, obtain the waveform instruction that current Waveform Control instruction comes into force, and this waveform instruction is sent to waveform decoder 3.Next Waveform Control instruction that meanwhile memory cell 1 obtains the memory address according to described next Waveform Control instruction, is sent to Waveform Control instruction decoder 2 as current Waveform Control instruction and resolves.
Because memory cell 1 can meet the instruction that addressing simultaneously obtains two kinds of functions, be Waveform Control instruction and waveform instruction, therefore, described Waveform Control instruction decoder 2 and waveform decoder 3 can be carried out parse operation simultaneously, and two the Waveform Control instructions of take are elaborated as example:
Waveform Control instruction decoder 2 is resolved article one Waveform Control instruction obtaining, and obtains the memory address of the waveform instruction that the instruction of article one Waveform Control carries, and the memory address of second Waveform Control instruction.
When the memory address of the waveform instruction of carrying according to the instruction of article one Waveform Control is obtained waveform instruction, according to the memory address acquisition second Waveform Control instruction of second Waveform Control instruction.
When waveform decoder 3 is resolved the waveform instruction that article one Waveform Control instruction of receiving comes into force, the second Waveform Control instruction that Waveform Control instruction decoder 2 dissection process obtain, like this, has shortened the processing latency of second Waveform Control instruction.When having many Waveform Control instructions, the processing of can simultaneously decoding of instruction decoder 2 and waveform decoder 3, presents continuous productive process, has improved decoding efficiency.
Continuous productive process is the decode procedure of an instruction to be divided into multistep carry out, every one-level circuit is only processed a step wherein, multi-level pmultistage circuit is processed many instructions on streamline simultaneously like this, the instruction completing in the cycle at a plurality of work clock before making, can shorten to an average work clock completed in the cycle, shorten the decoding time used, improved decoding efficiency, therefore, improved speed and frequency that pulse produces.
Preferably, referring to Fig. 2, described pulse generating device, also comprises: microcontroller 4, for data initialization, and control described memory cell 1, described Waveform Control instruction decoder 2, and the operating state of described waveform decoder 3.
Concrete, described data initialization is specially Waveform Control instruction and waveform instruction is stored in respectively in a plurality of storage areas, can obtain Waveform Control instruction and waveform instruction simultaneously.This microcontroller 4 is controlled described memory cell 1, Waveform Control instruction decoder 2, and waveform decoder 3 start working and out-of-work state, when this pulse generating device of needs emergent stopping, can quit work by microcontroller 4 control store unit 1, Waveform Control instruction decoder 2 and waveform decoder 3.
Preferably, referring to Fig. 3 a, the memory cell 1 in embodiment corresponding to Fig. 2 can comprise: store the storage area 10 of Waveform Control instruction and waveform instruction, and this storage area has independently the first reading-writing port 11 and the second reading-writing port 12 simultaneously.
It will be appreciated by persons skilled in the art that storage area is the least unit that forms memory cell, memory cell can consist of one or more storage areas.Therefore, the number of described storage area 10 can have a plurality of, each storage area 10 has two independently reading-writing port, i.e. the first reading-writing port 11 and the second reading-writing port 12, by these two reading-writing port, can obtain the instruction of two kinds of difference in functionalitys simultaneously, by the first reading-writing port 11 and the second reading-writing port 12, obtain respectively Waveform Control instruction and waveform instruction.
Preferably, referring to Fig. 3 b, in the corresponding pulse generating device embodiment of Fig. 2, memory cell 1 can comprise: for the first storage area 100 of stored waveform control command, its reading-writing port is the first reading-writing port, for the second storage area 110 of stored waveform instruction, its reading-writing port is the second reading-writing port.
The pulse generating device that the present embodiment provides, the instruction of difference in functionality is stored in to different storage areas, being about to Waveform Control instruction is stored in the first storage area 100, by the first reading-writing port, read and write, waveform instruction is stored in the second storage area 110, by the second reading-writing port, reads and writes, and can obtain the instruction of difference in functionality simultaneously, thereby realize, when resolving Waveform Control instruction, resolve the waveform that obtains wishing output, thereby improved speed and speed that impulse waveform produces.
Preferably, referring to Fig. 3 b, the Waveform Control instruction decoding implement body in above-described embodiment comprises: instruction decoder 21 and address decoder 22, wherein:
Described instruction decoder 21, for the Waveform Control instruction obtaining is carried out to instruction decoding processing, obtain waveform instruction that described Waveform Control instruction comes into force in the memory address of the second storage area, through a buffering, line up to send to address decoder 22, simultaneously, also obtain the memory address of next Waveform Control instruction, and this memory address is back to the Waveform Control location of instruction, carry out next round addressing operation.
Described address decoder 22, for described waveform instruction is carried out to dissection process in the memory address of the second storage area, obtains the memory address that this second storage area can directly be processed.
Waveform Control instruction is carried out after instruction decoding processing through instruction decoder 21, obtain the memory address piece of waveform instruction in the second storage area, but, storage area can not directly carry out addressing according to this address block, must first this address block be resolved, obtain the second storage area and can directly carry out the memory address of addressing operation, and then obtain corresponding waveform instruction, the waveform instruction of the acquisition impulse waveform that output needs after the dissection process of waveform decoder again.
The number that it will be appreciated by persons skilled in the art that described memory cell can be one or more, and the application does not limit this.
While for convenience of description, describing above device, with function, being divided into various unit describes respectively.Certainly, function that can Ba Ge unit when implementing the application realizes in same or a plurality of software and/or hardware.
As seen through the above description of the embodiments, those skilled in the art can be well understood to the mode that the application can add essential general hardware platform by software and realizes.Understanding based on such, the part that the application's technical scheme contributes to prior art in essence in other words can embody with the form of software product, this software product can be stored in storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that computer or microcontroller apparatus are carried out the method described in some part of each embodiment of the application or embodiment.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually referring to, each embodiment stresses is the difference with other embodiment.Especially, for device embodiment, because it is substantially similar in appearance to embodiment of the method, so describe fairly simplely, relevant part is referring to the part explanation of embodiment of the method.Device embodiment described above is only schematic, the wherein said unit as separating component explanation can or can not be also physically to separate, the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in a plurality of network element.Can select according to the actual needs some or all of module wherein to realize the object of the present embodiment scheme.Those of ordinary skills, in the situation that not paying creative work, are appreciated that and implement.
The above is only the application's embodiment; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection range.
Claims (8)
1. a method for generating pulse, is characterized in that, comprising:
A, according to the memory address of Waveform Control instruction, obtain corresponding current Waveform Control instruction, resolve the current Waveform Control instruction obtaining, obtain the memory address of the waveform instruction that current Waveform Control instruction carries, and the memory address of next Waveform Control instruction;
The waveform instruction that B, parsing are obtained according to the memory address of described waveform instruction, obtain output waveform, meanwhile, next Waveform Control instruction that the memory address of described next the Waveform Control instruction of foundation obtains, as current Waveform Control instruction, is returned to execution step A.
2. method according to claim 1, is characterized in that:
Waveform Control instruction is stored at least one first storage area in advance, waveform instruction is stored at least one second storage area.
3. method according to claim 1, is characterized in that:
By Waveform Control instruction and waveform instruction, store in a storage area with a plurality of independently reading-writing port in advance.
4. method according to claim 1, is characterized in that:
By Waveform Control instruction and waveform instruction, store in a plurality of storage areas with a plurality of independently reading-writing port in advance, described in each, storage area at least comprises two independent reading-writing port, and stores Waveform Control instruction and waveform instruction simultaneously.
5. a pulse generating device, is characterized in that, comprising: memory cell, Waveform Control instruction decoder and waveform decoder, wherein:
In described memory cell, store Waveform Control instruction and waveform instruction, comprise the first reading-writing port and the second reading-writing port;
Described memory cell obtains corresponding current Waveform Control instruction according to the memory address of Waveform Control instruction, and by the first reading-writing port, current Waveform Control instruction is sent to described Waveform Control instruction decoder and resolves, obtain the memory address of the corresponding waveform instruction of described current Waveform Control instruction, and the memory address of next Waveform Control instruction;
Described memory cell is by the first reading-writing port, next Waveform Control instruction that the memory address of next the Waveform Control instruction providing according to described Waveform Control instruction decoder is obtained, as current Waveform Control instruction, being sent to described Waveform Control instruction decoder resolves, and by the second reading-writing port, the waveform instruction that the memory address of the waveform instruction providing according to described Waveform Control instruction decoder is obtained, be sent to waveform decoder and resolve, obtain output waveform.
6. pulse generating device according to claim 5, it is characterized in that, described memory cell comprises: at least one stores the storage area of Waveform Control instruction and waveform instruction simultaneously, and this storage area has independently the first reading-writing port and the second reading-writing port.
7. pulse generating device according to claim 5, it is characterized in that, described memory cell comprises: at least one is connected with described the first reading-writing port, and the first storage area for stored waveform control command, and at least one is connected with described the second reading-writing port, and for the second storage area of stored waveform instruction.
8. according to the pulse generating device described in claim 5-7 any one, it is characterized in that, also comprise: microcontroller, for carrying out initialization, and the operating state of controlling described Waveform Control instruction decoder and waveform decoder and memory cell.
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| CN105162437B (en) * | 2015-08-11 | 2018-01-30 | 中国科学技术大学 | A kind of waveshape generating device and method |
| CN105718404B (en) * | 2016-01-18 | 2018-12-14 | 中国科学技术大学 | A kind of square-wave generator and method based on FPGA |
| CN106339027A (en) * | 2016-09-08 | 2017-01-18 | 合肥迈威德智能科技有限公司 | Pulse signal generator |
| CN107314145B (en) * | 2017-06-15 | 2019-04-09 | 华电电力科学研究院 | The multistage pulses control method of thermal power plant's regulating valve |
| CN110995285B (en) * | 2019-12-27 | 2023-05-05 | 成都达安众科技有限公司 | UHF RFID step-by-step instruction decoding method and chip |
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| CN1469547A (en) * | 2003-06-10 | 2004-01-21 | 湘潭师范学院 | High-precision optional waveform generator based on FPGA |
| CN1515911A (en) * | 2003-08-27 | 2004-07-28 | 华东师范大学 | Nuclear magnetic resonance pulse sequency generator |
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| CN1176699A (en) * | 1995-12-28 | 1998-03-18 | 摩托罗拉公司 | LNS-based computer processor and method of use thereof |
| CN1206145A (en) * | 1997-06-30 | 1999-01-27 | 索尼公司 | Signal processor having pipeline processing circuit and method of the same |
| CN1469547A (en) * | 2003-06-10 | 2004-01-21 | 湘潭师范学院 | High-precision optional waveform generator based on FPGA |
| CN1515911A (en) * | 2003-08-27 | 2004-07-28 | 华东师范大学 | Nuclear magnetic resonance pulse sequency generator |
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