CN102315840A - Pulse generation method and device - Google Patents
Pulse generation method and device Download PDFInfo
- Publication number
- CN102315840A CN102315840A CN201110111259A CN201110111259A CN102315840A CN 102315840 A CN102315840 A CN 102315840A CN 201110111259 A CN201110111259 A CN 201110111259A CN 201110111259 A CN201110111259 A CN 201110111259A CN 102315840 A CN102315840 A CN 102315840A
- Authority
- CN
- China
- Prior art keywords
- waveform
- instruction
- waveform control
- control instruction
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000002224 dissection Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
Images
Abstract
The invention discloses a pulse generation method and device. The pulse generation device disclosed by the invention can simultaneously obtain a waveform control command and a waveform command for carrying out decoding processing; a plurality of decoders simultaneously decode and represent line production; in the decoding of a production line mode, the decoding course of one piece of command is carried out in multiple steps; each level of circuit only processes one step in the multiple steps, thus the multiple levels of circuits simultaneously process the multiple commands on a production line; t the waveform is output while the command is analyzed, thereby enabling one piece of command which can be analyzed in multiple clock periods to be shortened to one average clock period; and time for decoding is shortened and the decoding efficiency is improved, thereby improving speed and frequency for generating pulse waveform.
Description
Technical field
The application relates to the digit pulse technical field, particularly relates to a kind of method for generating pulse and device.
Background technology
The programmable pulse producing method; Be to use the mode that is similar to computer programming language to describe impulse waveform; Pulse generating unit receives the Waveform Control sign indicating number of a definite form; Through resolving said Waveform Control sign indicating number and carrying out corresponding operation, common Waveform Control mode has order, circulation, redirect etc., can realize the Waveform Control of more complicated through the Waveform Control sign indicating number.
The pulse generator that prior art is used; Waveform Control sign indicating number and waveform are stored in same the instruction, like this, when resolving control code, can not produce new waveform; Can only, control code obtain, resolve waveform and output after resolving completion; Thereby limited the minimum pulse leaf length of its generation, and also just can't produce any impulse waveform according to minimum clock cycle, be that Pulse Blaster ESR-PRO pulse generator minimum under normal mode of 500MHz can only produce the impulse waveform that width is 12ns such as the operating frequency of SpinCore company; Because; This kind pulse generating device needs at least 6 work clock cycles to decode, and has so also just restricted the programmable pulse producing method and has produced the speed of pulse, and the frequency of the pulse that promptly produces is lower.What need to be resolved hurrily at present, is how to improve the speed that the programmable pulse producing method produces pulse.
Summary of the invention
For solving the problems of the technologies described above, the application embodiment provides a kind of method for generating pulse and device, and to improve the frequency of the pulse that programmable way produces, technical scheme is following:
A kind of method for generating pulse, this method comprises:
A, the current Waveform Control instruction that resolve to obtain obtain the memory address of the waveform instruction that current Waveform Control instruction carries and the memory address of next bar Waveform Control instruction;
The waveform instruction that B, parsing are obtained according to the memory address of said waveform instruction; Obtain output waveform; Simultaneously, next bar Waveform Control instruction that the memory address of instructing according to said next bar Waveform Control obtains is returned execution in step A as current Waveform Control instruction.
Preferably, in advance with the Waveform Control instruction storage at least one first storage area, with the waveform instruction storage at least one second storage area.
Preferably, in advance with Waveform Control instruction and waveform instruction storage in a storage area with a plurality of independently reading-writing port.
Preferably, in advance with Waveform Control instruction and waveform instruction storage in a plurality of storage areas with a plurality of independently reading-writing port, each said storage area comprises two independent reading-writing port at least, and stores the Waveform Control instruction simultaneously and waveform instructs.
A kind of pulse generating device comprises: memory cell, Waveform Control instruction decoder and waveform decoder, wherein, store Waveform Control instruction and waveform instruction in the said memory cell, and comprise first reading-writing port and second reading write port;
Said memory cell is sent to said Waveform Control instruction decoder through first reading-writing port with current Waveform Control instruction and resolves; Obtain the memory address that said current Waveform Control instructs corresponding waveform to instruct, and the memory address of next bar Waveform Control instruction;
Said memory cell is through first reading-writing port; Next bar Waveform Control instruction that will obtain according to the memory address that next bar Waveform Control that said Waveform Control instruction decoder provides is instructed; Being sent to said Waveform Control instruction decoder as current Waveform Control instruction resolves; And through the second reading write port; The waveform instruction that the memory address that will instruct according to the waveform that said Waveform Control instruction decoder provides obtains is sent to waveform decoder and resolves, and obtains output waveform.
Preferably, said memory cell comprises: at least one stores the storage area of Waveform Control instruction and waveform instruction simultaneously, and this storage area has independently first reading-writing port and second reading write port.
Preferably; Said memory cell comprises: at least one links to each other with said first reading-writing port; And first storage area that is used for the stored waveform control command, and at least one links to each other with said second reading write port, and be used for second storage area of stored waveform instruction.
Preferably, above-mentioned pulse generating device also comprises: microcontroller, be used to carry out initialization, and the operating state of controlling said Waveform Control instruction decoder and waveform decoder and memory cell.
Use the technical scheme that above the application provides; Pulse generating device can obtain Waveform Control instruction simultaneously and instruct with waveform and carry out decoding processing, and a plurality of decoders are decoded simultaneously and demonstrated continuous productive process, and the decoding of pipeline system is that the decode procedure with an instruction is divided into multistep and carries out; Each grade circuit is only handled a step wherein; Multi-level pmultistage circuit is handled a plurality of instructions on the streamline simultaneously like this, is implemented in when resolving instruction output waveform; An instruction in a plurality of clock cycle, could resolving before making shortened in the average clock cycle; Reduce the used time of decoding, improved decoding efficiency, and then improved speed and frequency that impulse waveform produces.
Description of drawings
In order to be illustrated more clearly in the application embodiment or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiment that put down in writing among the application, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of a kind of method for generating pulse of the application embodiment;
Fig. 2 is the structural representation of a kind of pulse generating device of the application embodiment;
Fig. 3 a is the structural representation of the another kind of pulse generating device of the application embodiment;
Fig. 3 b is the structural representation of the another kind of pulse generating device of the application embodiment.
Embodiment
The application embodiment provides a kind of method for generating pulse; Be used to improve the pulse generation speed and the frequency of programmable pulse producing method; Can obtain Waveform Control instruction simultaneously instructs with waveform and carries out dissection process; And adopt pipeline system to resolve instruction, and being divided into multistep and carrying out because pipeline system is a decode procedure with an instruction, each grade circuit is only handled a step wherein; Multi-level pmultistage circuit is handled many instructions on the streamline simultaneously like this, and an instruction could resolving in the cycle at a plurality of work clock before making shortens to an average work clock cycle with interior completion.Reduce the used time of decoding, improved decoding efficiency, and then improved speed and frequency that impulse waveform produces.
For above-mentioned purpose, the feature and advantage that make the application can be more obviously understandable, the application is done further detailed explanation below in conjunction with accompanying drawing and embodiment.
Referring to Fig. 1, Fig. 1 is the schematic flow sheet of a kind of method for generating pulse of the application embodiment, and this method comprises:
S101 resolves the current Waveform Control instruction that obtains, and obtains the waveform instruction storage address that said current Waveform Control instruction is carried, and the memory address of next bar Waveform Control instruction.
Memory address according to the Waveform Control instruction obtains corresponding Waveform Control instruction; It is current Waveform Control instruction; Resolve said current Waveform Control instruction, obtain the memory address that current Waveform Control instructs corresponding waveform to instruct, and the memory address of next bar Waveform Control instruction.
Concrete, said Waveform Control instruction comprises three partial informations and is respectively: memory address, the cyclical information of the waveform instruction that this Waveform Control instruction is entrained, and cycle-index information, wherein:
When said cyclical information was circulation execution information, then the memory address of next bar Waveform Control instruction did, the memory address of current Waveform Control instruction adds 1.Said cycle-index information is that number of times is carried out in the circulation of Waveform Control instruction;
Concrete; Circulate for beginning such as the cyclical information in the instruction of i bar Waveform Control; Cyclical information in the instruction of n bar Waveform Control is for stopping circulation; Then all instructions that i+1 bar Waveform Control instructs n bar Waveform Control to instruct are carried out in circulation, cycle-index, the i.e. corresponding information of cycle-index in the i bar Waveform Control instruction.
When said cyclical information was carried out the information of Waveform Control instruction for not circulating, then said cycle-index information was specially the memory address of next bar Waveform Control instruction.
S102; Resolve waveform instruction according to the memory address acquisition of said waveform instruction; Obtain output waveform, simultaneously, according to next bar Waveform Control instruction of memory address acquisition of said next bar Waveform Control instruction; Return execution S101 as current Waveform Control instruction, all execute up to all Waveform Control instructions.
During practical implementation; Resolve the memory address that said current Waveform Control instructs resulting waveform to instruct; Be the address block address, comprise the initial address and the address block length of waveform instruction place storage area, memory cell can not directly utilize address block to carry out addressing; Event needs to become memory cell can directly carry out the addressing address of addressing this address block information analysis, and then obtains the waveform instruction according to this addressing address.
Resolve the instruction of said waveform, obtain output waveform, and time of continuing of this waveform, promptly obtain hoping the impulse waveform of exporting.
Meanwhile,,, return execution in step S101, all resolved up to all Waveform Control instructions as current Waveform Control instruction according to next bar Waveform Control instruction of memory address acquisition of next bar Waveform Control instruction.
Can know by foregoing; The obtaining of Waveform Control instruction, parsing is instructed with waveform and is obtained, resolve and demonstrate pipeline system; Can handle the instruction of many Waveform Control on this streamline simultaneously, stop up to the parsing Shu Zhiling that finishes, promptly all Waveform Control instructions have all been resolved.
Below with an instantiation explanation pipeline system resolving:
Obtain the instruction of article one Waveform Control,, resolve the memory address that the instruction of article one Waveform Control obtains the instruction of first waveform as current Waveform Control instruction, and the memory address of second Waveform Control instruction.
Memory address according to said first waveform instruction obtains the instruction of first waveform, and resolves this first waveform instruction, obtains output waveform.When obtaining and resolving said first waveform instruction,, carry out dissection process as current Waveform Control instruction according to the memory address acquisition second Waveform Control instruction of said second Waveform Control instruction.
In other words; The obtaining of second Waveform Control instruction, dissection process and first waveform instruct obtains, dissection process can be carried out simultaneously; The rest may be inferred, and the processing of instruction of many Waveform Control and waveform instruction then presents continuous productive process, and the pipeline system decoding is that the decode procedure with an instruction is divided into multistep, is undertaken by multi-level pmultistage circuit; Each grade circuit is only handled a step wherein, and multi-level pmultistage circuit is handled a plurality of instructions on the streamline simultaneously like this.Instruction decoded stream waterline in the present embodiment can be handled Waveform Control instruction and waveform instruction simultaneously; Thereby shortened the processing latency of every Waveform Control instruction; Make the dissection process time of an instruction shorten in the average clock cycle, see on the macroscopic view, shortened the time of output pulse waveform by a plurality of clock cycle; Therefore, speed and frequency that pulse produces have been improved.
Preferably; In the embodiment of the pairing method for generating pulse of Fig. 1; Waveform Control is instructed and dissection process is carried out in the waveform instruction for realization is obtained simultaneously; Can be in advance with the Waveform Control instruction storage at least one first storage area, with the waveform instruction storage at least one second storage area.
It will be appreciated by persons skilled in the art that storage area is a least unit of forming memory cell, promptly memory cell is made up of at least one storage area.Therefore, said at least one first storage area and said at least one second storage area can be formed one or more memory cell.
When being a plurality of memory cell; Can be that said first storage area is formed at least one memory cell; Said second storage area is formed at least one memory cell, can also be to include first storage area and two kinds of storage areas of second storage area in each memory cell.
Preferably; In method for generating pulse embodiment shown in Figure 1, Waveform Control is instructed and dissection process is carried out in the waveform instruction for realization is obtained simultaneously, and is all right; In advance with Waveform Control instruction and waveform instruction; Store into simultaneously in the storage area with a plurality of independently reading-writing port, the shared storage area of promptly a plurality of reading-writing port, but the read-write operation between a plurality of port is independent of each other;
It will be appreciated by persons skilled in the art that and to use a plurality of storage areas to store all Waveform Control instructions and waveform instruction with a plurality of independent reading-writing port.
Corresponding to top method embodiment, the application also provides a kind of pulse generating device, and referring to Fig. 2, this device comprises: memory cell 1, Waveform Control instruction decoder 2, waveform decoder 3.
Memory cell 1 is used for the storage area that stored waveform control command and waveform instruct, and comprises first reading-writing port and second reading write port.
Said memory cell 1 is sent to said Waveform Control instruction decoder 2 through first reading-writing port with current Waveform Control instruction and resolves; Obtain the memory address that said current Waveform Control instructs corresponding waveform to instruct, and the memory address of next bar waveform instruction;
Next bar Waveform Control instruction that said memory cell 1 will obtain according to the memory address that next bar Waveform Control that said Waveform Control instruction decoder 2 provides is instructed through first reading-writing port; As current Waveform Control instruction; Being sent to Waveform Control instruction decoder 2 resolves; And through the second reading write port; The waveform instruction that the memory address that will instruct according to the waveform that said Waveform Control instruction decoder 2 provides obtains is sent to waveform decoder 3 and resolves, and obtains output waveform.
During practical implementation, dissection process is carried out in the current Waveform Control instruction of 2 pairs of acquisitions of Waveform Control instruction decoder, obtains the waveform instruction storage address that said current Waveform Control instruction is carried, and the memory address of next bar Waveform Control instruction.
Said Waveform Control instruction comprises three partial informations, is respectively: memory address, the cyclical information of the waveform instruction that this Waveform Control instruction is entrained, and cycle-index information, wherein:
When said cyclical information was circulation execution information, then the memory address of next bar Waveform Control instruction did, the memory address of current Waveform Control instruction adds 1, and said cycle-index information is that number of times is carried out in the circulation of Waveform Control instruction;
Concrete; Circulate for beginning such as the cyclical information in the instruction of i bar Waveform Control; Cyclical information in the instruction of n bar Waveform Control is for stopping circulation; Then all instructions that i+1 bar Waveform Control instructs n bar Waveform Control to instruct are carried out in circulation, cycle-index, the i.e. corresponding information of cycle-index in the i bar Waveform Control instruction.
When said cyclical information was carried out the information of Waveform Control instruction for not circulating, then said cycle-index information was specially the memory address of next bar Waveform Control instruction.
Concrete; Said Waveform Control instruction decoder 2 is resolved said current Waveform Control instruction; Obtain the memory address of the waveform instruction that the instruction of current Waveform Control carries and the memory address of next bar Waveform Control instruction, be back to said memory cell 1, memory cell 1 is according to the memory address of said waveform instruction; Obtain the waveform instruction that current Waveform Control instruction comes into force, and this waveform instruction is sent to waveform decoder 3.Memory cell 1 next bar Waveform Control instruction that will obtain according to the memory address of said next bar Waveform Control instruction meanwhile is sent to Waveform Control instruction decoder 2 as current Waveform Control instruction and resolves.
Because memory cell 1 can satisfy the instruction that addressing simultaneously obtains two kinds of functions; Be Waveform Control instruction and waveform instruction; Therefore, said Waveform Control instruction decoder 2 can carry out parse operation simultaneously with waveform decoder 3, is that example is elaborated with two Waveform Control instructions:
Waveform Control instruction decoder 2 is resolved article one Waveform Control instruction that obtains, and obtains the memory address of the waveform instruction that the instruction of article one Waveform Control carries, and the memory address of second Waveform Control instruction.
When the memory address that the waveform that carries according to the instruction of article one Waveform Control instructs is obtained the waveform instruction, according to the memory address acquisition second Waveform Control instruction of second Waveform Control instruction.
When the waveform that article one Waveform Control instruction that receives when waveform decoder 3 parsings comes into force instructed, the second Waveform Control instruction that Waveform Control instruction decoder 2 dissection process obtain like this, had been shortened the processing latency that the second Waveform Control is instructed.When many Waveform Control instructions, instruction decoder 2 can carry out decoding processing simultaneously with waveform decoder 3, demonstrates continuous productive process, has improved decoding efficiency.
Continuous productive process is that the decode procedure with an instruction is divided into multistep and carries out; Each grade circuit is only handled a step wherein, and multi-level pmultistage circuit is handled many instructions on the streamline simultaneously like this, an instruction of accomplishing in the cycle at a plurality of work clock before making; Can shorten in the average work clock cycle and accomplish; Shorten the used time of decoding, improved decoding efficiency, therefore, improved speed and frequency that pulse produces.
Preferably, referring to Fig. 2, said pulse generating device also comprises: microcontroller 4, and be used for data initialization, and control said memory cell 1, said Waveform Control instruction decoder 2, and the operating state of said waveform decoder 3.
Concrete, said data initialization is specially Waveform Control instruction and waveform instruction is stored in respectively in a plurality of storage areas, can obtain Waveform Control instruction and waveform instruction simultaneously.The said memory cell of this microcontroller 4 controls 1, Waveform Control instruction decoder 2; And waveform decoder 3 start working with out-of-work state; When needs promptly stop this pulse generating device, can quit work through microcontroller 4 control store unit 1, Waveform Control instruction decoder 2 and waveform decoder 3.
Preferably, referring to Fig. 3 a, the memory cell 1 among the embodiment of Fig. 2 correspondence can comprise: store the storage area 10 of Waveform Control instruction and waveform instruction simultaneously, and this storage area has independently first reading-writing port 11 and second reading write port 12.
It will be appreciated by persons skilled in the art that storage area is a least unit of forming memory cell, promptly memory cell can be made up of one or more storage areas.Therefore; The number of said storage area 10 can have a plurality of; Each storage area 10 all has two independently reading-writing port; I.e. first reading-writing port 11 and second reading write port 12 can obtain the instruction of two kinds of difference in functionalitys simultaneously through these two reading-writing port, promptly obtain the Waveform Control instruction respectively through first reading-writing port 11 and second reading write port 12 and instruct with waveform.
Preferably; Referring to Fig. 3 b; Among the pairing pulse generating device embodiment of Fig. 2, memory cell 1 can comprise: be used for first storage area 100 of stored waveform control command, its reading-writing port is first reading-writing port; Be used for second storage area 110 of stored waveform instruction, its reading-writing port is the second reading write port.
The pulse generating device that present embodiment provides in different storage regions, is about to the Waveform Control instruction storage with the instruction storage of difference in functionality in first storage area 100; Read and write through first reading-writing port; The waveform instruction storage is read and write through the second reading write port at second storage area 110, can obtain the instruction of difference in functionality simultaneously; Obtain hoping the waveform exported thereby be implemented in to resolve when resolving the Waveform Control instruction, thereby improved speed and speed that impulse waveform produces.
Preferably, referring to Fig. 3 b, the Waveform Control instruction decoder in the foregoing description specifically comprises: instruction decoder 21 and address decoder 22, wherein:
Said instruction decoder 21; Be used for the Waveform Control that obtains is instructed decoding processing, obtain waveform that said Waveform Control instruction comes into force and instruct the memory address at second storage area, line up to send to address decoder 22 through a buffering; Simultaneously; Also obtain the memory address of next bar Waveform Control instruction, and this memory address is back to the Waveform Control location of instruction, carry out the next round addressing operation.
Said address decoder 22 is used for said waveform instruction is carried out dissection process in the memory address of second storage area, obtains the memory address that this second storage area can directly be handled.
The Waveform Control instruction is after instruction decoder 21 instructs decoding processing; Obtain the memory address piece of waveform instruction in second storage area, still, storage area can not directly carry out addressing according to this address block; Must earlier this address block be resolved; Obtain the memory address that second storage area can directly carry out addressing operation, and then obtain corresponding waveform instruction, the impulse waveform that the waveform instruction of acquisition needs through output after the dissection process of waveform decoder again.
The number that it will be appreciated by persons skilled in the art that said memory cell can be one or more, and the application does not limit this.
For the convenience of describing, be divided into various unit with function when describing above the device and describe respectively.Certainly, when implementing the application, can in same or a plurality of softwares and/or hardware, realize the function of each unit.
Description through above execution mode can know, those skilled in the art can be well understood to the application and can realize by the mode that software adds essential general hardware platform.Based on such understanding; The part that the application's technical scheme contributes to prior art in essence in other words can be come out with the embodied of software product; This software product can be stored in the storage medium; Like ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that computer or microcontroller apparatus are carried out the described method of some part of each embodiment of the application or embodiment.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and identical similar part is mutually referring to getting final product between each embodiment, and each embodiment stresses all is the difference with other embodiment.Especially, for device embodiment, because it is basically similar in appearance to method embodiment, so describe fairly simplely, relevant part gets final product referring to the part explanation of method embodiment.Device embodiment described above only is schematic; Wherein said unit as the separating component explanation can or can not be physically to separate also; The parts that show as the unit can be or can not be physical locations also; Promptly can be positioned at a place, perhaps also can be distributed on a plurality of NEs.Can realize the purpose of present embodiment scheme according to the needs selection some or all of module wherein of reality.Those of ordinary skills promptly can understand and implement under the situation of not paying creative work.
The above only is the application's a embodiment; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; Can also make some improvement and retouching, these improvement and retouching also should be regarded as the application's protection range.
Claims (8)
1. a method for generating pulse is characterized in that, comprising:
A, the current Waveform Control instruction that resolve to obtain obtain the memory address of the waveform instruction that current Waveform Control instruction carries and the memory address of next bar Waveform Control instruction;
The waveform instruction that B, parsing are obtained according to the memory address of said waveform instruction; Obtain output waveform; Simultaneously, next bar Waveform Control instruction that the memory address of instructing according to said next bar Waveform Control obtains is returned execution in step A as current Waveform Control instruction.
2. method according to claim 1 is characterized in that:
In advance with the Waveform Control instruction storage at least one first storage area, with the waveform instruction storage at least one second storage area.
3. method according to claim 1 is characterized in that:
With Waveform Control instruction and waveform instruction, store in the storage area with a plurality of independently reading-writing port in advance.
4. method according to claim 1 is characterized in that:
With Waveform Control instruction and waveform instruction, store in a plurality of storage areas with a plurality of independently reading-writing port in advance, each said storage area comprises two independent reading-writing port at least, and stores Waveform Control instruction and waveform instruction simultaneously.
5. a pulse generating device is characterized in that, comprising: memory cell, Waveform Control instruction decoder and waveform decoder, wherein:
Store Waveform Control instruction and waveform instruction in the said memory cell, comprise first reading-writing port and second reading write port;
Said memory cell is sent to said Waveform Control instruction decoder through first reading-writing port with current Waveform Control instruction and resolves; Obtain the memory address that said current Waveform Control instructs corresponding waveform to instruct, and the memory address of next bar Waveform Control instruction;
Said memory cell is through first reading-writing port; Next bar Waveform Control instruction that will obtain according to the memory address that next bar Waveform Control that said Waveform Control instruction decoder provides is instructed; Being sent to said Waveform Control instruction decoder as current Waveform Control instruction resolves; And through the second reading write port; The waveform instruction that the memory address that will instruct according to the waveform that said Waveform Control instruction decoder provides obtains is sent to waveform decoder and resolves, and obtains output waveform.
6. pulse generating device according to claim 5; It is characterized in that; Said memory cell comprises: at least one stores the storage area of Waveform Control instruction and waveform instruction simultaneously, and this storage area has independently first reading-writing port and second reading write port.
7. pulse generating device according to claim 5; It is characterized in that; Said memory cell comprises: at least one links to each other with said first reading-writing port; And first storage area that is used for the stored waveform control command, and at least one links to each other with said second reading write port, and be used for second storage area of stored waveform instruction.
8. according to each described pulse generating device of claim 5-7, it is characterized in that, also comprise: microcontroller, be used to carry out initialization, and the operating state of controlling said Waveform Control instruction decoder and waveform decoder and memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110111259.XA CN102315840B (en) | 2011-04-29 | 2011-04-29 | Pulse generation method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110111259.XA CN102315840B (en) | 2011-04-29 | 2011-04-29 | Pulse generation method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102315840A true CN102315840A (en) | 2012-01-11 |
| CN102315840B CN102315840B (en) | 2014-01-15 |
Family
ID=45428703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110111259.XA Active CN102315840B (en) | 2011-04-29 | 2011-04-29 | Pulse generation method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102315840B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105162437A (en) * | 2015-08-11 | 2015-12-16 | 中国科学技术大学 | Waveform generating device and method |
| CN105718404A (en) * | 2016-01-18 | 2016-06-29 | 中国科学技术大学 | Square-wave generator and generating method based on FPGA |
| CN106339027A (en) * | 2016-09-08 | 2017-01-18 | 合肥迈威德智能科技有限公司 | Pulse signal generator |
| CN107314145A (en) * | 2017-06-15 | 2017-11-03 | 华电电力科学研究院 | The multistage pulses control method of thermal power plant's regulating valve |
| CN110995285A (en) * | 2019-12-27 | 2020-04-10 | 成都达安众科技有限公司 | UHF RFID step-by-step instruction decoding method and chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1176699A (en) * | 1995-12-28 | 1998-03-18 | 摩托罗拉公司 | LNS-based computer processor and method of use thereof |
| CN1206145A (en) * | 1997-06-30 | 1999-01-27 | 索尼公司 | Signal processor having pipeline processing circuit and method of the same |
| CN1469547A (en) * | 2003-06-10 | 2004-01-21 | 湘潭师范学院 | High-precision optional waveform generator based on FPGA |
| CN1515911A (en) * | 2003-08-27 | 2004-07-28 | 华东师范大学 | Nuclear magnetic resonance pulse sequency generator |
| US20090254691A1 (en) * | 2005-08-22 | 2009-10-08 | Nxp B.V. | Microcontroller waveform generation |
-
2011
- 2011-04-29 CN CN201110111259.XA patent/CN102315840B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1176699A (en) * | 1995-12-28 | 1998-03-18 | 摩托罗拉公司 | LNS-based computer processor and method of use thereof |
| CN1206145A (en) * | 1997-06-30 | 1999-01-27 | 索尼公司 | Signal processor having pipeline processing circuit and method of the same |
| CN1469547A (en) * | 2003-06-10 | 2004-01-21 | 湘潭师范学院 | High-precision optional waveform generator based on FPGA |
| CN1515911A (en) * | 2003-08-27 | 2004-07-28 | 华东师范大学 | Nuclear magnetic resonance pulse sequency generator |
| US20090254691A1 (en) * | 2005-08-22 | 2009-10-08 | Nxp B.V. | Microcontroller waveform generation |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105162437A (en) * | 2015-08-11 | 2015-12-16 | 中国科学技术大学 | Waveform generating device and method |
| CN105718404A (en) * | 2016-01-18 | 2016-06-29 | 中国科学技术大学 | Square-wave generator and generating method based on FPGA |
| CN105718404B (en) * | 2016-01-18 | 2018-12-14 | 中国科学技术大学 | A kind of square-wave generator and method based on FPGA |
| CN106339027A (en) * | 2016-09-08 | 2017-01-18 | 合肥迈威德智能科技有限公司 | Pulse signal generator |
| CN107314145A (en) * | 2017-06-15 | 2017-11-03 | 华电电力科学研究院 | The multistage pulses control method of thermal power plant's regulating valve |
| CN107314145B (en) * | 2017-06-15 | 2019-04-09 | 华电电力科学研究院 | The multistage pulses control method of thermal power plant's regulating valve |
| CN110995285A (en) * | 2019-12-27 | 2020-04-10 | 成都达安众科技有限公司 | UHF RFID step-by-step instruction decoding method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102315840B (en) | 2014-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110299131B (en) | Voice synthesis method and device capable of controlling prosodic emotion and storage medium | |
| CN102315840A (en) | Pulse generation method and device | |
| CN105657574A (en) | Video file making method and device | |
| CN100495310C (en) | Method and system for designing a memory controller | |
| WO2005083534A3 (en) | Method for initializing and utilizing a memory device for a plc | |
| CN103747339A (en) | Method and apparatus for resolving no response condition of on-line video by using android device | |
| US20100103762A1 (en) | Memory device and method | |
| CN110175029A (en) | The forming method of front-end and back-end automatically dispose tool based on data analysis | |
| CN102279766A (en) | Method and system for concurrently simulating processors and scheduler | |
| CN106648666A (en) | User interface generating method and user interface generating system | |
| CN109739784A (en) | A kind of data processing method, device, system and FPGA accelerator card | |
| CN105487987A (en) | Method and device for processing concurrent sequential reading IO (Input/Output) | |
| CN103714724A (en) | Information processing method and electronic device | |
| CN107886988A (en) | Tiltedly become during memory program and suppress voltage | |
| CN103135049B (en) | Test patterns generation device, test program generation device, generation method and proving installation | |
| CN102508822A (en) | Thai display method, device and system | |
| CN102339031B (en) | Method and device for calling subprogram and PLC (Programmable Logic Controller) control system | |
| CN105446788B (en) | A kind of information processing method and electronic equipment | |
| CN109062830B (en) | Control system of nonvolatile memory | |
| CN102739203A (en) | Output method and device for impulse waveform | |
| CN109144518A (en) | A kind of image file construction method and device based on jenkins | |
| CN104199808A (en) | Method and device for typesetting document framework | |
| CN104539769B (en) | The method and system that a kind of flash lamp of control mobile terminal is rotated | |
| CN102682794A (en) | Multi-code-stream mixed direct burning control method and system | |
| CN104281544B (en) | Memory Controller and its signal generating method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170712 Address after: 230001, Hefei province hi tech Zone, 2800 innovation Avenue, two innovation industrial park, E2 building, A District, 1-4 floor, B District, 3-4 floor, Anhui Patentee after: Hefei quantum Precision Instrument Co.,Ltd. Address before: 230026 Jinzhai Road, Anhui, China, No. 96, No. Patentee before: University of Science and Technology of China |
|
| TR01 | Transfer of patent right | ||
| CP03 | Change of name, title or address |
Address after: 230000 Levels 1-4 and 3-4 in Area A and B of E2 Building, Second Stage of Innovation Industrial Park, 2800 Innovation Avenue, Hefei High-tech Zone, Anhui Province Patentee after: Guoyi Quantum (Hefei) Technology Co.,Ltd. Address before: 23 000 1-4 floors in zone A and 3-4 floors in zone B of E2 floor, phase II, Innovation Industrial Park, 2800 Innovation Avenue, Hefei Hi-tech Zone, Anhui Province Patentee before: Hefei quantum Precision Instrument Co.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 230000 Levels 1-4 and 3-4 in Area A and B of E2 Building, Second Stage of Innovation Industrial Park, 2800 Innovation Avenue, Hefei High-tech Zone, Anhui Province Patentee after: Guoyi Quantum Technology (Hefei) Co.,Ltd. Address before: 230000 Levels 1-4 and 3-4 in Area A and B of E2 Building, Second Stage of Innovation Industrial Park, 2800 Innovation Avenue, Hefei High-tech Zone, Anhui Province Patentee before: Guoyi Quantum (Hefei) Technology Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |