CN1278132A - Asynchronous transmitting mode main arrangements interconnecting means - Google Patents
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Abstract
It includes three data channels which are (101) from end UTOPIA2to end UTOPIA1, (102) form end UTOPIA1 to end UTOPIA2 and (103) end ITOPIA1 in self loop, four correlative stater for controlling said three data channels. The invention can realizes abutment of main arrangement, supports signal element self-loop function of end UTOPIA1, supports UTOPIA1 speed rate in 8bit/25MHZ and UTOPIA2 speed rate in 16bit/50MHZ. It can be realized by ont-chip, so the device volume is smaller, the cost is lower.
Description
The present invention relates to asynchronous transfer mode (the Asynchronous Transfer Mode in the data communication field, be called for short ATM) technology, specifically, relate to the device that carries out the ATM cell transmission between UTOPIA first order standard main equipment and the UTOPIA second level standard main equipment.
Universal Test ﹠ Operations PHY Interface for ATM (Universal Test ﹠amp; Operations PHY Interface forATM is called for short UTOPIA) be the interface that cell transmits between a kind of ATM of finishing layer equipment and physical layer (physical device the is called for short PHY) equipment, in atm technology, occupy an important position.Atm forum has defined UTOPIA first order standard (UTOPIA Level 1, abbreviation UTOPIA1), UTOPIA second level standard (UTOPIA Level2, be called for short UTOPIA2) and higher level standard, typical UTOPIA1 has defined the interface of 8 25MHz, and typical UTOPIA2 has defined 16 50MHz, supported the interface of many physical layer equipments.The UTOPIA interface is a kind of asymmetric coupling, generally ATM layer equipment is called the UTOPIA main equipment, and physical layer equipment is called the UTOPIA slave unit.
Slave unit is by the reiving/transmitting state of " it is effective to send cell " and " it is effective to receive cell " signalisation main equipment cell, and main equipment is then initiated the transmitting-receiving process of cell by active tranmitting data register signal, transmitting-receiving enable signal.UTOPIA other main equipment of same level and slave unit signal mate mutually, can directly dock; If two equipment do not satisfy the condition that signal mates mutually, want to realize that cell transmits, often need certain middle device to achieve a butt joint.
Realize that the usual means that cell transmits has: (1) UTOPIA1 slave unit is to the cell conveyer between the UTOPIA2 slave unit, and two groups of slave units can use common clock, and cell need not to carry out buffer memory, and it is relatively easy to implement; (2) single UTOPIA2 main equipment is to the tap and the multiple devices of a plurality of UTOPIA1 slave units, and for example the chip id T77310 of IDT company just belongs to this kind equipment; (3) a plurality of UTOPIA1 main equipments connect the tap and the multiple devices of single UTOPIA2 slave unit, as application number is that 98119980 Chinese patent " asynchronous transfer mode system " just belongs to this class, this system adopts method relatively more commonly used, its data path uses first in first out (First In First Out) structure, UTOPIA1 is carried out 8 to 16 conversion and compound to the data of a plurality of UTOPIA1 paths of UTOPIA2 direction, the slave unit of giving the UTOPIA2 interface then sends, and then selects the trend of UTOPIA1 cell according to the Virtual Path VPI the cell (Virtual Path Identifier) value from UTOPIA2 to the UTOPIA1 direction.
For two main equipments, because their an each have their own cover clock signal and transmitting-receiving enable signals, signal does not each other match, and therefore can not realize direct butt joint.But a lot of occasions press for the butt joint of main equipment, such as at the ATM layer processor that has only the UTOPIA1 host device interface with have the situation that transmits ATM cell between the switching network of UTOPIA2 host device interface.In order to realize that the cell between main equipment and main equipment transmits, need between main equipment and main equipment, add a docking facilities, make up the bridge that a cell transmits.In general, more more to the butt joint between the UTOPIA1-UTOPIA2 main equipment than the butt joint demand between UTOPIA1-UTOPIA1 main equipment, and the latter is the former subclass on implementation method, so the docking facilities of UTOPIA1-UTOPIA2 main equipment is a kind of exemplary practical device of the UTOPIA of connection main equipment.
Company of U.S. Motorola (Motorola) is releasing its band ATM segmentation and convergence layer (Segmentation ﹠amp; Reassembly, be called for short SAR) processor MPC860 the time, a material once was provided, about a kind of typical main equipment docking facilities, its exercise question is " Double Slave; A double sided UTOPIA bridge; emulating a physical device (PHY) .Assisting an ATM Switch to use a secondary ATMlayer device as a co-processor; " mainly be to say to set up the UTOPIA bridge that is equivalent to two slave units, make the ATM switching network can add other ATM layer equipment of use as its coprocessor, it is the exemplary device that a kind of UTOPIA2 main equipment connects the UTOPIA1 main equipment, this device adopts the programming device FLEX10K30 of altera corp, use the memory space of its internal memory as cell, and support the UTOPIA1 end from ring, but its UTOPIA2 end has only 8 bit wides and 25MHz clock, do not relate to because some technological difficulties that 16 bit wides and 50MHz clock cause, and design is succinct inadequately.
Also has a kind of employing enhancement mode programmable logic device (Enhanced Programmable Logical Device, be called for short EPLD) add the biplate external FIFO as the main equipment docking facilities, its controller and data path are discrete, the self-loop function that does not have UTOPIA1 end cell, bring difficulty for the debugging and the failure diagnosis of UTOPIA1 main equipment, and cost is higher, and it is bigger to take system bulk.
The object of the present invention is to provide a kind of asynchronous transfer mode main equipment docking facilities, both can finish the butt joint of main equipment, support the cell self-loop function of UTOPIA1 end again, some shortcomings of prior art have been overcome, and device is succinct reliable, realizes easily, can save cost.
In order to achieve the above object, main equipment docking facilities of the present invention comprises:
UTOPIA2 holds the data channel of UTOPIA1 end, receives the data that UTOPIA2 main equipment transmitting terminal sends, and will send to UTOPIA1 main equipment receiving terminal after this data transaction;
UTOPIA1 holds the data channel of UTOPIA2 end, receives the data that UTOPIA1 main equipment transmitting terminal sends, and will send to UTOPIA2 main equipment receiving terminal after this data transaction;
The UTOPIA1 end receives the data that UTOPIA1 main equipment transmitting terminal sends from the loop data passage, and this storage is transmitted to UTOPIA1 main equipment receiving terminal;
The state machine that management UTOPIA1 end sends is controlled the internal work state of described main equipment docking facilities with the Signal Matching of UTOPIA1 main equipment transmitting terminal;
The state machine that management UTOPIA1 termination is received is controlled the internal work state of described main equipment docking facilities with the Signal Matching of UTOPIA1 main equipment receiving terminal;
The state machine that management UTOPIA2 end sends is controlled the internal work state of described main equipment docking facilities with the Signal Matching of UTOPIA2 main equipment transmitting terminal; With
The state machine that management UTOPIA2 termination is received is controlled the internal work state of described main equipment docking facilities with the Signal Matching of UTOPIA2 main equipment receiving terminal;
Interrelated between described 4 state machines, 3 data passages are realized accurately control, finish effectively UTOPIA1 main equipment and UTOPIA2 main equipment to connection function.
Described main equipment docking facilities can adopt the programming device of a band internal memory as carrier, and all data paths and control logic are integrated in this programming device, forms single chip architecture.
Below in conjunction with drawings and Examples, the present invention is described in detail further.
Fig. 1 is the position view of docking facilities 10 of the present invention in the ATM system.
Fig. 2 is the structural representation of docking facilities 10 of the present invention.
Fig. 3 is the state machine state transition diagram of control data path 10 1.
Fig. 4 is the state machine state transition diagram of control data path 10 2.
Fig. 5 is the state machine state transition diagram of control from loop data path 10 3.
Fig. 6 is the schematic diagram of three data passages in the docking facilities 10 of the present invention.
Fig. 7 is the application example of docking facilities 10 of the present invention in the ATM system.
The UTOPIA standard has cell level and two kinds of handshake methods of byte level, and current device generally all uses cell level handshake method, so the present invention designs according to cell level handshake method.
Fig. 1 has provided main equipment docking facilities 10 of the present invention residing position in the ATM system.Can see, main equipment docking facilities 10 1 ends are linked on the UTOPIA2 bus as the UTOPIA2 slave unit and dock with the UTOPIA2 main equipment, the other end docks with the UTOPIA1 main equipment as the UTOPIA1 slave unit, like this UTOPIA2 main equipment and UTOPIA1 main equipment is docked.
As shown in Figure 2, UTOPIA1-UTOPIA2 main equipment docking facilities of the present invention comprises that UTOPIA2 holds data channel 101, the UTOPIA1 of UTOPIA1 end to hold data channel 102, the UTOPIA1 of UTOPIA2 end to hold from 3 three data passages of loop data path 10 the one of four states machine: the state machine 107 that state machine 106 that the state machine 105 that the state machine 104 that management UTOPIA1 end sends, management UTOPIA1 termination are received, management UTOPIA2 end send and management UTOPIA2 termination are received.Control to three data passages realizes by four state machines that are mutually related, state machine 106 and state machine 105 control data path 10s 1; State machine 104 and state machine 107 control data path 10s 2; State machine 104 and state machine 105 control data path 10s 3.
Because the clock of two state machines of each data channel of the control main equipment clock with corresponding this data channel end respectively is identical, and the clock of these two main equipments may be asynchronous, thereby the clock of corresponding states machine is also just asynchronous, the state that state machine collected occurring easily is the situation of the labile state of another state machine, for avoiding this state mistake to adopt, can adopt the way of twice affirmation; Also can adopt state is locked as single holding wire with this state machine clock, give the method that another state machine is gathered again.For instance, suppose that state machine 104 is by one group of d type flip flop＜D0, D1, D2〉the cooperation expression, state 104S is its state, and concrete value is＜1,0,1 〉, state machine 107 will judge whether state machine 104 is in the 104S state, to judge next step state transitions.The criterion of the method for " twice affirmation " is, " if D1, D2 are all satisfied＜D0 in the last clock of state machine 107 and present clock upper edge 〉=＜1,0,1, state machine 107 thinks that state machine 104 is in the 104S state so." a kind of method in back then will add and use a d type flip flop D3; value is as follows; " if D1, D2 are satisfied＜D0 in state machine 104 present clock upper edges 〉=＜1,0,1 〉, d type flip flop D3=1 so, otherwise d type flip flop D3=0; " criterion is as follows: " if state machine 107 present clock upper edge D3=1, state machine 104 is in the 104S state so.”
The peripheral signal of this docking facilities 10 has: UTOPIA2 clock line, control line, address wire and data wire, UTOPIA1 clock line, control line and data wire.
Fig. 3 has described the state transition diagram that the state machine 106 (left side) of control data path 10 1 and state machine 105 (right side) form, and dotted line is represented is two state machines parts that are mutually related.
The state of data channel 101 is from " sending idle " state of state machine 106, the state that breaks away from " receiving idle " when state machine 105, enter " emptying memory " state and empty after the address of internal memory, state machine 106 " can send cell ", and signal is changed to high level, if this moment, the UTOPIA2 main equipment was inquired about, just obtain the response of " can send cell ", according to this response, the UTOPIA2 main equipment sends data, and this moment, UTOPIA2 end main equipment " transmission enables " signal was a low level, " sending cell begins " signal is a high level, the service of connection devices address of " transmission cell addresses " signal for setting.After state machine 106 receives these signals, enter " sending " state, begin to receive the data that the UTOPIA2 main equipment sends, and start a transmitting counter.When this rolling counters forward value was 8, state machine 106 " can be sent cell ", and signal was changed to low level; When the rolling counters forward value was 27, a cell finished receiving, and state machine 106 enters " cell is sent completely " state.According to this state, state machine 105 enters " receive ready " state, and " can receive cell " signal is changed to high level.The UTOPIA1 main equipment is changed to low level with " reception enables " signal after finding that " can receive cell " signal is height, begins to receive data.After state machine 105 receives low level " reception enables " signal, enter " receiving " state, send data to the UTOPIA1 main equipment, and start a count pick up device, state machine 106 enters " sending idle " state according to " receiving " state of state machine 105 simultaneously.When count pick up device count value was 32, configuration state machine 105 " can receive cell " and be low level, and when count pick up device count value was 52, data transmitted and finish, and state machine 105 enters " receiving idle " state.After this repeat said process.
Fig. 4 has described the state machine 104 (left side) of control data path 10 2 and the state transition diagram that state machine 107 (right side) forms.The state of data channel 102 is from " sending idle " state of state machine 104, when state machine 107 breaks away from " receiving idle " state, after entering " emptying memory " state and emptying the internal memory address, state machine 104 " can be sent cell ", and signal is changed to high level, according to this signal,, then send data if the UTOPIA1 main equipment has cell to need to send, this moment, UTOPIA1 end main equipment " transmission enables " signal was a low level, and " sending cell begins " signal is a high level.State machine 104 receives after these signals, enters " sending " state, receives the data that the UTOPIA1 main equipment is sent, and starts a transmitting counter.When the transmitting counter count value is 48, " can send cell " signal of delivering to UTOPIA1 end main equipment is changed to low level, nearly send and finish, change " sending last 4 bytes " state over to, change " being sent completely " state over to after continuing to receive last 4 data.During this period, if " transmission enables " signal accident lose, make Data Receiving less than, then state machine 104 also changes " being sent completely " state over time automatically over to, to prevent because the deadlock that causes of dropout.After state machine 104 entered " being sent completely " state, state machine 107 entered " receive ready " state according to this state, and " can receive cell " signal is changed to high level.The UTOPIA2 main equipment sends low level " reception enables " signal after being polled to this signal, begin to receive data.After state machine 107 receives low level " reception enables " signal, enter " receiving " state, send data to the UTOPIA2 main equipment, start a count pick up device simultaneously, state machine 104 " receives " state according to state machine 107 and enters " sending idle " state simultaneously.When count pick up device count value is 8, UTOPIA2 end " can receive cell " signal is changed to low level, when count pick up device count value was 27, data transmitted and finish, and state machine 107 enters " receiving idle " state, repeats said process later on.
When the UTOPIA1 end encircled certainly, data channel 103 worked, and this data channel 103 is used state machine 104 and state machine 105, forms new state transition diagram, and the state exchange in the state machine is constant, and the signal that just is associated changes to some extent.Fig. 5 has described the state transition diagram of UTOPIA1 from loop data path 10 3.State is from state machine 104 " transmission is idle " state, when state machine 105 breaks away from " receiving idle " state, after entering " emptying memory " state and emptying storage address, " can send cell " signal of delivering to UTOPIA1 end main equipment is changed to high level, if this moment, the transmitting terminal main equipment had cell to need to send, then send data, at this moment, UTOPIA1 end main equipment " transmission enables " signal is a low level, and " sending cell begins " signal is a high level.After state machine 104 receives this signal, enter " sending " state, receive the data that the UTOPIA1 main equipment sends, and start a transmitting counter.When the transmitting counter count value was 48, state machine 104 " can be sent cell ", and signal was changed to low level, and state machine 104 changes " sending last 4 bytes " state over to, changed " being sent completely " state over to after continuing to receive last 4 data.If during this period " transmission enables " signal accident lose make Data Receiving less than, state machine 104 also changes " being sent completely " state, the deadlock that causes in case stop signal is lost over time automatically over to.After state machine 104 entered " being sent completely " state, state machine 105 " was sent completely " state according to state machine 104 and enters " receive ready " state, and " can receive cell " signal is changed to high level.The receiving terminal main equipment sends low level " reception enables " signal after finding that " can receive cell " signal is high level, begins to receive data.After state machine 105 receives low level " reception enables " signal, enter " receiving " state, send data to the receiving terminal main equipment, and start a count pick up device, state machine 104 enters " sending idle " state according to " receiving " state of state machine 105 simultaneously.When count pick up device count value was 32, it was low level that state machine 105 is put " can receive cell " signal, and when count pick up device count value was 52, data transmitted and finish, and state machine 105 enters " receiving idle " state.
Because the UTOPIA main equipment respectively has the clock of oneself, therefore, need carry out buffer memory to data for realizing the adaptive of utopia bus two ends rhythm.Metadata cache can adopt with first in first out buffer FIFO, and this is existing common practices.The present invention selects for use the programming device of band internal memory as carrier, can save external FIFO like this, and memory built-in can be saved device pin, reduces device volume, saves the time delay that data turnover chip brings, easier realization high speed processing and ring certainly.If internal memory is supported the twoport operation, i.e. separate the clock of read and write, address, and the design of data channel is just relatively easy.If internal memory is not supported the twoport operation, i.e. read and write is shared one group of clock, address, then needs clock and address are selected, and makes that the data sync difficulty is bigger, need take way to guarantee that the sequential that writes with sense data is reliable.The present invention mainly is at latter event, and the implementation method of the previous case is a subclass of latter event.
As can be seen from the foregoing description, the control structure of three data passages is near symmetry, and data channel is because data width and speed different and asymmetric according to three data passages characteristics separately, are selected different data channel institutional frameworks for use.Fig. 6 is exactly the structured flowchart of three data passages.
Data channel 101 comprises two groups of input register R1, R2, two internal memory EAB1, EAB2 as data space, public data outlet selector MUX, one group of data output register R3.Data write among internal memory EAB1, the EAB2 simultaneously with 16 bit wides, substantially alternately read from two memories with 8 bit wides then, in header checksum location exception, reason is that ATM cell length is 53 bytes, and UTOPIA2 transmits 54 bytes, and a byte is vacated in the centre.This data channel 101 is positioned at the top of Fig. 6.
Data channel 102 comprises, one group of input register R4, two internal memory EAB3, EAB4 as data space.Data substantially alternately write among internal memory EAB3, the EAB4 with 8 bit wides, make an exception at the header checksum location; Data are read from two memories simultaneously with 16 bit wides.This data channel 102 is positioned at the lower part of Fig. 6.
Use internal memory EAB3, EAB4 as data space from loop data path 10 3, also comprise public data outlet selector MUX, one group of data output register R3; Basic over-over mode is all adopted in writing and reading of its data.The data channel that connects top and the bottom among Fig. 6 is exactly the intermediate link of this data channel 103.
Read and write a shared group address and clock, that gives data correctly writes a proposition difficult problem, because the address must be selected from the read and write address through a selector, selector has brought the time delay that is difficult to predict, accidentally just can not and alignment of data, the consequence that address and data do not line up is the position that data can not be written to expection.According to actual conditions, the present invention has adopted effective way to solve this difficult problem to each data channel.
For data channel 101, its writing rate is 16/50MHz, and read-out speed is 8/25MHz, and read-out speed is lower, can adopt the 50MHz clock to come all data and the address of synchronous internal memory, realizes the alignment of data and address.At input, by the 50MHz clock the internal memory end synchronously, data can be write well, specifically, earlier by 50MHz clock lock input data, deliver to internal memory EAB1 then, EAB2 writes inbound port, simultaneously at the rearmounted internal memory EAB1 of the 1st low level " transmission enables " input clock, " WE " of EAB2 is high level, behind the clock of the 2nd low level " transmission enables ", begin to add up and write the address, and adopt the 50MHz clock synchronization to write, can be with the data that receive write memory EAB1 well, among the EAB2.At output, though internal memory EAB1, EAB2 readout clock (50MHz) are asynchronous with data output clock (25MHz), but between two rising edges of 25MHz clock there are two 50MHz clock cycle, even if like this under worst case concerning 25MHz output clock, reading the address also has stabilization time of common clock half period (10ns), can guarantee that data can read from internal memory EAB1, EAB2 like clockwork.
For data channel 102, its speed that writes is 8/25MHz, read-out speed is 16/50MHz, because read-out speed is higher, if both guaranteed to write fashionable data, address align with the clock of a high speed, reading the address when guaranteeing read data again has enough stabilization time, and the speed of this high-frequency clock must reach about 100MHz so, and cost is higher.It is slower that the present invention considers that 25MHz writes clock speed, writes data correctness and can adopt the way of restriction write time to guarantee.By using a time-delay clock to write useful signal with conduct with writing enable signal, though the address with write that data are not strict aligns, write when effective, the clock level of delaying time is low, address and data are all stable, can realize that data write like clockwork.Sense data is not then used clock synchronization, because effective a period of time of address (about 5ns)) data are effective, just in time satisfy the sequential requirement of UTOPIA2 standard.
Use the selector MUX and the output register R3 of input control, internal memory EAB3, EAB4 and the data channel 101 of data channel 102 from loop data path 10 3.Writing of situation that data write and data channel 102 is in full accord, and it then is that the UTOPIA1 end is exclusive from loop data path 10 3 that data are read the address, is produced by the output clock count.The same with data channel 102, data are read from internal memory EAB1, EAB2 and are not also used clock synchronization, and data are read from one of two internal memorys and delivered to output register R3 by selector MUX, realize clock synchronization by output register R3.
Fig. 7 has provided an application examples of UTOPIA1-UTOPIA2 main equipment docking facilities.The ATM switching network generally has several groups of UTOPIA2 host device interface, and 50MHz and 16 s' data-interface ability is provided, and just can possess this class interface of 4 622M such as the switching network of a 2.5G.Monitoring and management to this switching network need a CPU usually, so that signaling processing ability to be provided.The chip MPC860SAR CPU of motorola inc has an ATM SAR, and has stronger disposal ability, can be used for realizing above-mentioned functions, is the UTOPIA1 host device interface but the atm interface of this chip uses, can not directly dock with the ATM switching network.Therefore can adopt main equipment docking facilities of the present invention, just in time can realize docking of a port of MPC860 SAR and ATM switching network, and utilize UTOPIA1 end self-loop function, make MPC860AR have the function of self-looped testing.
In sum, the present invention adopts unique control state machine and data channel processing method, and the interface arrangement that docks between UTOPIA1 and the UTOPIA2 main equipment is provided, and design is succinct reliable; The present invention can support the UTOPIA1 speed of 8/25MHz and the UTOPIA2 speed of 16/50MHz, adopts the monolithic design, and device volume is less, and cost is lower; In addition, the present invention can use the standard VHDL language to realize having good transplantability, can select different types of programming device for use, goes back portable in the ASIC design.
Claims (5)
1. an asynchronous transfer mode main equipment docking facilities (10) is characterized in that: comprising:
UTOPIA2 holds the data channel (101) of UTOPIA1 end, receives the data that UTOPIA2 main equipment transmitting terminal sends, and will send to UTOPIA1 main equipment receiving terminal after this data transaction;
UTOPIA1 holds the data channel (102) of UTOPIA2 end, receives the data that UTOPIA1 main equipment transmitting terminal sends, and will send to UTOPIA2 main equipment receiving terminal after this data transaction;
The UTOPIA1 end receives the data that UTOPIA1 main equipment transmitting terminal sends from loop data passage (103), and this storage is transmitted to UTOPIA1 main equipment receiving terminal;
The state machine (104) that management UTOPIA1 end sends is controlled the internal work state of described main equipment docking facilities (10) with the Signal Matching of UTOPIA1 main equipment transmitting terminal;
The state machine (105) that management UTOPIA1 termination is received is controlled the internal work state of described main equipment docking facilities (10) with the Signal Matching of UTOPIA1 main equipment receiving terminal;
The state machine (106) that management UTOPIA2 end sends is controlled the internal work state of described main equipment docking facilities (10) with the Signal Matching of UTOPIA2 main equipment transmitting terminal; With
The state machine (107) that management UTOPIA2 termination is received is controlled the internal work state of described main equipment docking facilities (10) with the Signal Matching of UTOPIA2 main equipment receiving terminal;
Interrelated between described 4 state machines, described 3 data passages are realized accurately control.
2. main equipment docking facilities as claimed in claim 1 (10), it is characterized in that: described UTOPIA2 holds the data channel (101) of UTOPIA1 end to comprise: two groups of input register R1, R2, two internal memory EAB1, EAB2 as data space, public data outlet selector MUX, one group of data output register R3.
3. main equipment docking facilities as claimed in claim 1 (10) is characterized in that: described UTOPIA1 holds the data channel (102) of UTOPIA2 end to comprise: one group of input register R4, two internal memory EAB3, EAB4 as data space.
4. main equipment docking facilities as claimed in claim 1 (10), it is characterized in that: described UTOPIA1 end comprises internal memory EAB3, EAB4 as data space from loop data passage (103), public data outlet selector MUX, one group of data output register R3.
5. as one of any described main equipment docking facilities (10) of claim 1-4, it is characterized in that: described main equipment docking facilities (10) adopts the programming device of a band internal memory as carrier, all data channel and control logic are integrated in this programming device, form single chip architecture.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 00116987 CN1118988C (en) | 2000-06-29 | 2000-06-29 | Asynchronous transmitting mode main arrangements interconnecting means |
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| CN 00116987 CN1118988C (en) | 2000-06-29 | 2000-06-29 | Asynchronous transmitting mode main arrangements interconnecting means |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103067310A (en) * | 2012-12-28 | 2013-04-24 | 中国电子科技集团公司第五十四研究所 | Interconnection device and method supporting UTOPIA MASTER port |
| CN114047714A (en) * | 2021-09-27 | 2022-02-15 | 中天海洋系统有限公司 | Multiprocessor cooperative control system and method |
-
2000
- 2000-06-29 CN CN 00116987 patent/CN1118988C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103067310A (en) * | 2012-12-28 | 2013-04-24 | 中国电子科技集团公司第五十四研究所 | Interconnection device and method supporting UTOPIA MASTER port |
| CN114047714A (en) * | 2021-09-27 | 2022-02-15 | 中天海洋系统有限公司 | Multiprocessor cooperative control system and method |
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| Publication number | Publication date |
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| CN1118988C (en) | 2003-08-20 |
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