CN1271003C - TiO2 doped low pressure pressure-sensitive ceramic and its preparing method - Google Patents

Abstract

The present invention discloses a TiO2 doped low voltage voltage-sensitive ceramic. An analytical pure TiO2 is used as a main body, Ta2 O5 is used as a semiconduction dopant, SrCO 3 is used as an acceptor doping object, and the TiO 2 doped low voltage voltage-sensitive ceramic is formed by that an amount of Bi2 O3 and an amount of SiO2 are doped as comburent agents in the mode of sintering. The present invention is characterized in that the Ta2 O5 replaces five metal oxides, such as Nb2 O5, etc., and is used as the semiconduction dopant so that the voltage-sensitive ceramic based on the TiO2 has low varistor voltage and high dielectric coefficient, the doping amount of the acceptor SrCO 3 is changed, and the relevant electrical performance parameters of the material can be regulated. Compared with low voltage voltage-sensitive ceramic of a srtio3 system, the present invention has the advantages of reltively simple process and equipment and reduced cost. The apparent dielectric coefficient epsilon of a ceramic material made by the present invention can generally achieve more than 10<5>, E<10mA> is generally from 1 to 10 v/mm, the alpha value can achieve more than 3.0, and the performance parameters can be changed by adjusting compossition and sintering conditions.

Description

Doped Ti O 2Low voltage varistor ceramics and making method

Technical field

The invention belongs to electronic devices and components material field, particularly a kind of doped Ti O ₂Low voltage varistor ceramics.

Background technology

For the protection of the superpotential and the electromagnetic interference of low-voltage apparatus, can be by means of a kind of piezoresistive element that has than high capacitance.The I-E characteristic of voltage dependent resistor generally is expressed as:

$I={\left(\frac{V}{C}\right)}^{\mathrm{\&alpha;}}$

I is an electric current in the formula, and V is a device voltage, and C is a material constant, and α is a nonlinear factor, and α=1 o'clock element is a fixed resistor.On engineering, nonlinear factor is defined as:

$\mathrm{\&alpha;}=\frac{\log (I_2/I_1)}{\log (V_2/V_1)}$ Or $\mathrm{\&alpha;}=\frac{\log (J_2/J_1)}{\log (E_2/E_1)}$

Generally use preceding formula, V in the formula for ZnO varistor ₁, V ₂For the electric current of flowing through is I ₁, I ₂The time sample terminal voltage, and the definition I ₁, I ₂Be respectively 0.1mA and 1mA; And for non-ZnO varistor back formula, and define the current density, J of flowing through ₁, J ₂Be respectively 1mA/cm ²And 10mA/cm ²The time sample field intensity be E ₁, E ₂General V ₂And E ₂Be referred to as pressure sensitive voltage, wherein E ₂Note is made E again ₁₀(or E _10mA).In addition, use for anti-high-frequency electrical interferential, dielectric coefficient also is an important index parameter, and high dielectric coefficient could guarantee big interelectrode capacity.

For example in the application of the protection of DC micromotor sparking of brushes, be extensive use of a kind of annular voltage-sensitive resistor, present employed material is generally doping SrTiO ₃Or ZnO voltage-sensitive ceramic.But the pressure sensitive voltage of ZnO voltage-sensitive ceramic is higher, and dielectric coefficient is very little, and anti-high-frequency electromagnetic interference capability is poor; And SrTiO ₃The voltage-sensitive ceramic element must burn till in reducing atmosphere, oxidation in oxidizing atmosphere then, and complex manufacturing technology, cost height, and the pressure sensitive voltage of this class surface type element adjustment difficulty are unfavorable for the seriation of product.

Summary of the invention

For addressing the above problem, the purpose of this invention is to provide and a kind ofly be applicable to low voltage and have the high-dielectric coefficient value, manufacture craft simple doped Ti O ₂Low voltage varistor ceramics.

Another object of the present invention provides a kind of doped Ti O ₂The making method of low voltage varistor ceramics.

The object of the present invention is achieved like this: a kind of doped Ti O ₂Low voltage varistor ceramics is characterized in that: compositing formula is pressed the net value mol ratio by following raw material and is calculated:

Main body TiO ₂1

Semiconductor hotchpotch Ta ₂O ₅0.0005～0.0010

Sintering agent Bi ₂O ₃0.001～0.005

Sintering agent SiO ₂0.005～0.015

Acceptor doping thing SrCO ₃0.005～0.012

A kind of doped Ti O ₂The making method of low voltage varistor ceramics is characterized in that: may further comprise the steps: prepare burden-ball milling-drying-pre-burning-ball milling-drying-granulation-dry-pressing formed-sintering by above-mentioned compositing formula.

The present invention is with analytical pure TiO ₂Be main body, Ta ₂O ₅Be semiconductor (alms giver) hotchpotch, SrCO ₃Be the acceptor doping thing, mix an amount of Bi again ₂O ₃, SiO ₂Make sintering agent; Adopt traditional electronic ceramics manufacture craft, adopt when being sintering and bury sintering with the composition powder, sintering temperature is 1200～1300 ℃.With SrTiO ₃Be that low voltage varistor ceramics is compared, technology, equipment are all simple relatively, and cost reduces.And the apparent dielectric coefficient of prepared stupalith generally can reach 10 ⁵More than, E _10mABe generally 1-10V/mm, the value of α can reach more than 3.0.

Embodiment

A kind of doped Ti O of the present invention ₂Low voltage varistor ceramics, its raw material are TiO ₂, Ta ₂O ₅, Bi ₂O ₃, SiO ₂And SrCO ₃, it is formed proportioning and presses net value mol ratio calculating: TiO by following raw material ₂(1): Ta ₂O ₅(0.0005～0.0010): Bi ₂O ₃(0.001～0.005): SiO ₂(0.005～0.015): SrCO ₃(0.005～0.012) can suitably change as requested within the scope of the present invention.

Calculate and take by weighing each raw material at first in molar ratio; Add deionized water or distilled water then and on planetary ball mill, carried out ball mill mixing 2～6 hours, the pre-burning 1～2 hour under 900～1100 ℃ of temperature of oven dry back, pre-burning helps reducing pressure sensitive voltage and increases the apparent dielectric coefficient; Material after the pre-burning adds the ball mill pulverizing 2～6 hours on planetary ball mill of deionized water or distilled water once more, and oven dry is sieved, and granulation is dry-pressing formed; The base sheet is stacked in the corundum crucible after the moulding, adopts and to bury sintering technology (the same composition powder with granulation is buried print, and corundum crucible is added a cover and is the half opening shape), 1200-1300 ℃ of sintering 1～3 hour, promptly makes pottery of the present invention.

The present invention is described further below in conjunction with specific embodiment, but scope of the present invention is not limited to these specific examples.

Embodiment 1:

Each component mol ratio (net value) is TiO during preparation ₂(1): Ta ₂O ₅(0.00075): Bi ₂O ₃(0.003): SiO ₂(0.01): SrCO ₃(0.008,0.010 or 0.012).

Making step: at first calculate and take by weighing each raw material by above-mentioned mol ratio; Carried out the wet ball-milling batch mixing 4 hours with distilled water then; Dry behind the batch mixing, 1000 ℃ of pre-burnings 1 hour; Carried out wet ball-milling 4 hours with distilled water once more, sieve after the drying, granulation, dry-pressing formed is the print of  12 * 1.1mm; Print is stacked in the corundum crucible after the moulding, adopts the method for burying burning at 1250 ℃ of sintering, is incubated 2 hours, promptly makes sample 1～3.Sample size behind the sintering is the wafer sample of  9 * 0.9mm, fires an ohm silver electrode in the both ends of the surface of sample then, and its main performance index is as shown in table 1 after tested.

The different SrCO of table 1 ₃The Specifeca tion speeification of content sample

The sample sequence number	SrCO 3Volume (mol)	Pressure sensitive voltage E 10mA (V/mm)	Nonlinear factor α	Relative dielectric coefficient (1KHz)
					1	0.008	9.50	3.82	7.18×10 4
2	0.010	5.62	3.41	1.19×10 5
					3	0.012	5.92	3.42	1.21×10 5

Comparative example 1:

The preparation comparative sample is TiO by component mol ratio (net value) ₂(1): Ta ₂O ₅(0.00075) or Nb ₂O ₅(0.00075): Bi ₂O ₃(0.003): SiO ₂(0.01): SrCO ₃(0.010) carries out proportioning, use technology and the firing condition identical, make similar sample 4,5 with embodiment 1.After tested, its main performance index contrast is as shown in table 2.

Table 2 Ta ₂O ₅And Nb ₂O ₅The Specifeca tion speeification of doped samples relatively

The sample sequence number	Different doped element volumes (mol)	Pressure sensitive voltage E 10mA (V/mm)	Nonlinear factor α	Relative dielectric coefficient (1KHz)
					4	Ta 2O 5	5.62	3.41	1.19×10 5
5	Nb 2O 5	33.1	5.00	2.85×10 4

As can be seen from the above table, except nonlinear factor less than Nb ₂O ₅Outside the doped samples, every performance index of stupalith of the present invention are better than existing with Nb ₂O ₅Deng the stupalith of 5 valent metal oxides as the semiconductor hotchpotch.

Comparative example 2:

The preparation sample is TiO by component mol ratio (net value) ₂(1): Ta ₂O ₅(0.00075): Bi ₂O ₃(0.003): SiO ₂(0.01): SrCO ₃(0.010) carry out proportioning, the green compact print that makes adopts technology and the firing condition identical with embodiment 1 respectively, promptly buries sintering and makes similar sample 6, adopts traditional naked burning sintering process to make sample 7.After tested, its main performance index contrast is as shown in table 3.

The Specifeca tion speeification that table 3 is buried sintering and traditional naked burning sample compares

The sample sequence number	Sintering condition	Pressure sensitive voltage E 10mA (V/mm)	Nonlinear factor α	Relative dielectric coefficient (1KHz)
					6	Bury sintering (1250 ℃)	5.62	3.41	1.19×10 5
7	Naked burning (1250 ℃)	6.98	3.51	8.39×10 4

In the table as seen, bury sintered sample except non-property coefficient than naked burning sample smaller, its pressure sensitive voltage is lower, dielectric coefficient is bigger.

Claims (4)

1. doped Ti O ₂Low voltage varistor ceramics is characterized in that: compositing formula is pressed the net value mol ratio by following raw material and is calculated:

Main body TiO ₂1

Semiconductor dopant Ta ₂O ₅0.0005～0.0010

Sintering agent Bi ₂O ₃0.001～0.005

Sintering agent SiO ₂0.005～0.015

Acceptor doping material SrCO ₃0.005～0.012.

2. doped Ti O ₂The making method of low voltage varistor ceramics is characterized in that: may further comprise the steps: prepare burden-ball milling-drying-pre-burning-ball milling-drying-granulation-dry-pressing formed-sintering according to the described compositing formula of claim 1.

3. doped Ti O according to claim 2 ₂The making method of low voltage varistor ceramics is characterized in that: described agglomerating sintering temperature is 1200-1300 ℃.

4. doped Ti O according to claim 2 ₂The making method of low voltage varistor ceramics is characterized in that: described sintering adopts and buries sintering process with the composition powder.