CN1261723A - 防止在晶片的边缘上形成黑硅的方法和装置 - Google Patents

防止在晶片的边缘上形成黑硅的方法和装置 Download PDF

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CN1261723A
CN1261723A CN99126740A CN99126740A CN1261723A CN 1261723 A CN1261723 A CN 1261723A CN 99126740 A CN99126740 A CN 99126740A CN 99126740 A CN99126740 A CN 99126740A CN 1261723 A CN1261723 A CN 1261723A
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D·－C·佩恩格
D·M·多布什斯基
T·H·王
K·洛伊斯纳
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International Business Machines Corp
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Abstract

一种通过减少黑硅的沉积增加芯片成品率的方法包括以下步骤:提供适合于制造半导体芯片的硅晶片,在晶片的整个表面上淀积第一层,除去部分第一层露出适合形成半导体器件的区域,以及腐蚀晶片使第一层的其余部分防止在晶片上腐蚀材料的再沉积。一种减少黑硅淀积其上的半导体组件包括适合于制造半导体芯片的硅晶片,晶片具有形成半导体器件的正面、背面和边缘。淀积层形成在晶片上覆盖背面和边缘,防止腐蚀期间晶片的背面和边缘上硅的再沉积。

Description

防止在晶片的边缘上形成黑硅的方法和装置
本发明涉及半导体器件，特别涉及防止在晶片上形成黑硅的方法和装置。
腐蚀工艺通过例如化学反应要除去的部分表面从衬底上除去材料。然而在腐蚀期间，被腐蚀的材料经常地再沉积，通常这是不希望的。在半导体工业中，在集成电路芯片的处理中广泛地使用腐蚀。在集成电路芯片的制造工艺中，硅晶片作为半导体器件形成其上的衬底。在包括存储单元的集成电路中，如深沟槽电容器等的电容器需要将深沟槽腐蚀到硅衬底内。所述腐蚀通常促进了硅材料在晶片的其它区域中的再沉积。这些其它区域包括硅晶片的背表面和边缘。
黑硅是描述通过腐蚀半导体芯片中的硅形成的硅沉淀物使用的术语。黑硅通常为长度约4到6微米之间的小尖峰(spike)形。这些尖峰经常形成在硅衬底的露出区域上，特别是沿晶片的外边缘形成。尖峰从晶片脱离并在处理期间影响晶片上器件的形成。尖峰的存在影响了芯片成品率。
如上所述，尖峰经常形成在晶片的边缘和背面上。常规的技术尝试在附加的处理之前通过清洗晶片的背面或除去边缘的熔珠(bead)去除尖峰。漂洗技术使用液体漂洗掉形成在晶片边缘和/或背面上形成的尖峰。使用如抛光等的机械工艺除去边缘熔珠的同时除去这些尖峰。然而，这两种技术都不能确保处理期间尖峰不存在关键的区域内。
因此，在半导体芯片的制造期间需要防止形成黑硅。还需要通过消除黑硅沉积增加芯片的成品率。
根据本发明通过减少黑硅沉积增加芯片成品率的方法包括以下步骤：提供适合于制造半导体芯片的硅晶片，在晶片的整个表面上淀积第一层，除去部分第一层露出适用形成半导体器件的区域，以及腐蚀晶片使第一层的其余部分阻止在晶片上腐蚀材料的再沉积。
在本发明非常有用的方法中，第一层优选氧化层。淀积的步骤包括通过低压汽相淀积淀积第一层。除去的步骤包括通过反应离子腐蚀除去第一层。还包括在第一层和用于形成半导体器件的露出区域上形成衬垫层的步骤以及在衬垫层上形成玻璃层的步骤。腐蚀晶片的步骤还包括通过反应离子腐蚀腐蚀晶片。
根据本发明制造期间处理半导体器件的硅晶片减少硅的再沉积的方法包括在晶片的整个表面上形成第一层；在第一层的第一部分上形成抗蚀剂层留在晶片上，第一部分位于晶片的背面和边缘，通过曝光抗蚀剂层除去留下的第一层的第二部分，由此露出适合于半导体器件形成其上的晶片的正面，并除去抗蚀剂层。
在根据本发明的另一方法中，第一层优选氧化层。形成第一层的步骤包括通过低压汽相淀积淀积第一层。除去第二部分的步骤包括通过反应离子腐蚀除去第二部分。还包括在第一层和用于形成半导体器件的露出的正面上形成衬垫层的步骤。还包括在形成半导体器件的衬垫层上形成玻璃层的步骤。还优选通过反应离子腐蚀腐蚀晶片的步骤。
减少黑硅沉积其上的半导体组件包括适于制造半导体芯片的硅晶片，晶片具有形成半导体器件的正面、背面和边缘。淀积层形成在晶片上覆盖背面和边缘，防止腐蚀期间晶片的背面和边缘上硅的再沉积。
淀积层优选为氧化层，最好为TEOS。淀积层的厚度优选在约1,000和约10,000之间。半导体器件包括深沟槽电容器。淀积层优选为低压淀积的层。
通过下面结合附图对示例性实施例的详细介绍，本发明的这些和其它目的、特点和优点将很显然。
下面为参考以下附图对优选实施例的详细介绍。
图1为硅晶片的剖面图；
图2为根据本发明层具有淀积在图1的硅晶片上的剖面图；
图3为根据本发明具有抗蚀剂层形成在背面上的淀积层上的图2的晶片剖面图；
图4为根据本发明倒装之后的图3的晶片剖面图，晶片正面上的部分淀积层已除去；
图5为根据本发明抗蚀剂层已除去的图4的硅晶片剖面图；
图6为根据本发明具有衬垫层和玻璃层形成在图5的硅晶片上的剖面图。
本发明涉及半导体器件，特别涉及防止在晶片上形成黑硅的方法和装置。本发明可以防止在半导体晶片的露出区域上形成黑硅。在制造期间，特别是硅衬底的腐蚀期间，可以保护露出的区域不受腐蚀硅的再沉积影响。露出的区域由芯片的制造期间留在原位的掩膜层保护。
现在参考附图的具体内容，其中几个图中类似的参考数字在表示类似或相同的元件，图1示出了制造半导体芯片使用的硅晶片10。晶片10放置在台板上(未示出)，在处理期间固定晶片。
参考图2，晶片10有适合于在晶片10上制造器件的正面14。层16形成在晶片10的整个表面上。层16优选由如二氧化硅等的氧化物形成，最好为TEOS或热氧化物。此外，可以使用如氮化硅等的氮化物，然而这里介绍的其它工艺应相应地修改。层16的厚度从约1,000到约10,000，优选约3,000到约8,000。使用必须覆盖晶片10的整个表面(如图所示的前面、背面和侧面)的淀积工艺淀积层16。在一个实施例中，使用低压化学汽相淀积工艺淀积层16。也可以使用其它的淀积工艺。
参考图3，抗蚀剂层18淀积在晶片10的背面20上。背面20与正面14相对。因此，需要倒装晶片10将抗蚀剂层18提供其上。形成抗蚀剂层18，使层16在晶片10的背面20和边缘22上被覆盖。抗蚀剂层18可以为本领域的技术人员公知的相对于抗蚀剂层18选择性腐蚀层16的任何材料。
参考图4，定位晶片10从正面14上除去层16。这包括再次倒装晶片10。在正面14上进行覆盖(blanket)腐蚀，除去露出的那部分层16。仅除去正面14上的层16。层16的其余部分仍由抗蚀剂层18保护。层16的其余部分覆盖边22和背面20，同时露出正面14。覆盖腐蚀工艺必须定向，必须保护边缘22。这优选通过反应离子腐蚀(RIE)工艺，或使用阴影环(未示出)进行。
参考图5和6，除去抗蚀剂层18露出层16的其余部分。通过湿法腐蚀工艺除去抗蚀剂层18。衬垫层24淀积在晶片10的整个表面和层16的其余部分上。衬垫层24优选由如氮化硅等的氮化物形成。此外，可以使用如氧化硅等的氧化物，然而，这里的其它工艺需要相应地修改。层24的厚度从约1,000到约10,000，优选约3,000到约8,000。使用低压淀积工艺淀积层24，例如低压化学汽相淀积工艺(LPCVD)。
LPCVD或其它的淀积工艺对淀积衬垫层24很有用。玻璃层26淀积在正面14上。玻璃层26包括硼硅玻璃(BSG)、硼磷硅玻璃(BPSG)或本领域中公知的其它玻璃层。
使用公知的方法继续进一步处理晶片。关于在动态随机存取存储器(DRAM)芯片的一个例子中，需要形成深沟槽电容器以实现存储器单元。此时进一步的处理包括深沟槽光刻腐蚀晶片10沟槽位置处的玻璃层26。通过例如反应离子腐蚀腐蚀晶片10，在硅晶片10中形成深沟槽。
由于层16的其余部分接触晶片10，因此腐蚀硅的再沉积不会发生在保留层16的晶片10上。以此方式，层16作为掩模防止黑硅尖峰形成在晶片的表面上。通过消除黑硅尖峰，减小了尖峰脱离和影响其它处理步骤的可能性。因此，芯片的成品率增加。在以后的处理步骤期间，优选已进行了大部分硅腐蚀之后，可以除去该掩模。如本领域中公知的那样进行晶片10的进一步处理。
现已介绍了防止在晶片的边缘上形成黑硅的方法和装置(意在示例而不是限定)，应该注意本领域的技术人员鉴于以上教导可以进行修改和变化。因此应该理解可以对在附带的权利要求书划定的本发明的范围和精神内公开的本发明的特定实施例进行修改。现已根据专利法的要求具体和详细地介绍了本发明，向专利法要求和保护的权利陈述在附带的权利要求书中。

Claims (20)

1.一种通过减少黑硅沉积增加芯片成品率的方法，包括以下步骤：
提供适于制造半导体芯片的硅晶片；
在晶片的整个表面上淀积第一层；
除去部分第一层露出适用于形成半导体器件的区域；以及
腐蚀晶片使第一层的其余部分阻止在晶片上腐蚀材料的再沉积。
2.根据权利要求1的方法，其中第一层为氧化层。
3.根据权利要求1的方法，其中淀积的步骤包括通过低压汽相淀积淀积第一层。
4.根据权利要求1的方法，其中除去的步骤包括通过反应离子腐蚀除去第一层。
5.根据权利要求1的方法，还包括在第一层和用于形成半导体器件的露出区域上形成衬垫层的步骤。
6.根据权利要求5的方法，还包括在用于形成半导体器件的衬垫层上形成玻璃层的步骤。
7.根据权利要求1的方法，其中腐蚀晶片的步骤还包括通过反应离子腐蚀腐蚀晶片。
8.一种处理半导体器件的硅晶片减少制造期间硅的再沉积的方法，包括以下步骤：
在晶片的整个表面上形成第一层；
在第一层的第一部分上形成抗蚀剂层留在晶片上，第一部分位于晶片的背面和边缘；
通过曝光抗蚀剂层除去留下的第一层的第二部分，由此露出适合于半导体器件形成其上的晶片的正面，以及
除去抗蚀剂层。
9.根据权利要求8的方法，其中第一层为氧化层。
10.根据权利要求8的方法，其中形成第一层的步骤包括通过低压汽相淀积淀积第一层。
11.根据权利要求8的方法，其中除去第二部分的步骤包括通过反应离子腐蚀除去第二部分。
12.根据权利要求8的方法，还包括在第一层和用于形成半导体器件的露出区域上形成衬垫层的步骤。
13.根据权利要求12的方法，还包括在形成半导体器件的衬垫层上形成玻璃层的步骤。
14.根据权利要求8的方法，还包括通过反应离子腐蚀腐蚀晶片的步骤。
15.一种具有减少的黑硅沉积于其上的半导体组件，包括：
适合于制造半导体芯片的硅晶片，晶片具有用于形成半导体器件的正面、背面和边缘；以及
形成在晶片上覆盖背面和边缘的淀积层，用于防止腐蚀期间晶片的背面和边缘上硅的再沉积。
16.根据权利要求15的半导体组件，其中所说淀积层为氧化层。
17.根据权利要求16的半导体组件，其中所说淀积层为TEOS。
18.根据权利要求15的半导体组件，其中所说淀积层的厚度在约1,000和约10,000之间。
19.根据权利要求15的半导体组件，其中半导体器件包括深沟槽电容器。
20.根据权利要求15的半导体组件，其中所说淀积层为低压淀积的层。
CN99126740A 1998-12-10 1999-12-10 防止在晶片的边缘上形成黑硅的方法和装置 Pending CN1261723A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346078A (zh) * 2013-06-26 2013-10-09 上海宏力半导体制造有限公司 化学机械研磨的方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821900B2 (en) 2001-01-09 2004-11-23 Infineon Technologies Ag Method for dry etching deep trenches in a substrate
KR100423754B1 (ko) * 2001-12-03 2004-03-22 주식회사 실트론 실리콘 웨이퍼의 고온 열처리 방법
US6713236B2 (en) * 2002-07-03 2004-03-30 Infineon Technologies North America Corp. Lithography method for preventing lithographic exposure of peripheral region of semiconductor wafer
US20050014364A1 (en) * 2003-07-18 2005-01-20 Infineon Technologies North America Corp. Method of suppressing the effect of shining spots present at the edge of a wafer
DE102004017747A1 (de) * 2004-04-06 2006-01-05 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauelementen und ein strukturiertes Substrat
DE102004052644A1 (de) * 2004-10-29 2006-05-04 Infineon Technologies Ag Abschattungseinrichtung für den Randbereich eines Halbleiterwafers
KR100842502B1 (ko) 2006-12-27 2008-07-01 동부일렉트로닉스 주식회사 실리콘 웨이퍼 제조방법
TWI346360B (en) * 2007-07-18 2011-08-01 Nanya Technology Corp Method of forming shadow layer on the wafer bevel
JP5458608B2 (ja) * 2009-03-10 2014-04-02 富士電機株式会社 半導体装置の製造方法
US8501283B2 (en) * 2010-10-19 2013-08-06 Lam Research Corporation Methods for depositing bevel protective film
KR101695901B1 (ko) * 2011-02-22 2017-01-23 에스케이하이닉스 주식회사 반도체소자 제조를 위한 기판 형성방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768036A (en) * 1980-10-14 1982-04-26 Nec Corp Semiconductor device
US4335503A (en) * 1980-12-24 1982-06-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method of making a high voltage V-groove solar cell
US4925809A (en) * 1987-05-23 1990-05-15 Osaka Titanium Co., Ltd. Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor
JPH0222818A (ja) * 1988-07-11 1990-01-25 Nec Corp 半導体装置の製造方法
JPH02122543A (ja) * 1988-10-31 1990-05-10 Fujitsu Ltd ウェハ
US5256594A (en) * 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
DE69106240T2 (de) * 1990-07-02 1995-05-11 Seiko Epson Corp Mikropumpe und Verfahren zur Herstellung einer Mikropumpe.
JPH04163907A (ja) * 1990-10-29 1992-06-09 Fujitsu Ltd 半導体基板
US5665622A (en) * 1995-03-15 1997-09-09 International Business Machines Corporation Folded trench and rie/deposition process for high-value capacitors
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates
KR100544596B1 (ko) * 1998-03-11 2006-01-24 지멘스 악티엔게젤샤프트 반도체 장치 제조시 블랙 실리콘 감소 방법 및 반도체 장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346078A (zh) * 2013-06-26 2013-10-09 上海宏力半导体制造有限公司 化学机械研磨的方法

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