CN1258104A - Semiconductor device and its mfg. method - Google Patents
Semiconductor device and its mfg. method Download PDFInfo
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- CN1258104A CN1258104A CN99120259A CN99120259A CN1258104A CN 1258104 A CN1258104 A CN 1258104A CN 99120259 A CN99120259 A CN 99120259A CN 99120259 A CN99120259 A CN 99120259A CN 1258104 A CN1258104 A CN 1258104A
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- nickel
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- tft
- intermediate layer
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- 238000000034 method Methods 0.000 title description 63
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- 239000010409 thin film Substances 0.000 claims abstract description 27
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- 229940078494 nickel acetate Drugs 0.000 description 1
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- KBJMLQFLOWQJNF-UHFFFAOYSA-N nickel(ii) nitrate Chemical compound [Ni+2].[O-][N+]([O-])=O.[O-][N+]([O-])=O KBJMLQFLOWQJNF-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
Nickel is introduced to a predetermined region of a peripheral circuit section, other than a picture element section, on an amorphous silicon film to crystallize from that region. After forming gate electrodes and others, sources, drains and channels are formed by doping impurities, and laser is irradiated to improve the crystallization. After that, electrodes/wires are formed. Thereby an active matrix type liquid crystal display whose thin film transistors (TFT) in the peripheral circuit section are composed of the crystalline silicon film whose crystal is grown in the direction parallel to the flow of carriers and whose TFTs in the picture element section are composed of the amorphous silicon film can be obtained.
Description
The present invention relates to be installed in the TFT on the insulating substrate (as glass)
sThe semiconductor device of (thin-film transistor).Be particularly related to the semiconductor device that is used for active matrix-type liquid crystal display device.
Has the TFT that is installed on the insulating substrate (as glass)
sSemiconductor device, be used in active matrix-type liquid crystal display device, image sensor and the similar device thereof, use TFT
sMaking the excitation picture element, is known.
Usually, the TFT that makes with the thin film silicon semiconductor is used for these devices.The thin film silicon semiconductor can roughly be divided into two classes: a class is by amorphous (amorphous) silicon (α-S
i) semiconductor that constitutes, another kind of is the semiconductor that is made of silicon metal.The common usefulness of amorphous si semiconductor at most because its manufacturing temperature is low, use the vapour phase processes manufacturing easily, and can make in a large number.But, compare with crystal silicon semiconductor, aspect physical property as the conductivity, the poor-performing of amorphous si semiconductor.Urgent need will seek a kind ofly to make the method for TFT by silicon metal, so that obtain stable properties.And as silicon metal, known also have polysilicon, and microcrystal silicon contains the amorphous silicon of crystallization composition, the half amorphous end of the intermediate state between silicon metal and amorphous silicon.
The following method that obtains with above-mentioned crystalline membrane Si semiconductor is known:＜1〉directly form crystalline membrane,＜2〉form amorphous semiconductor film, and can make its crystallization,＜3 with laser〉the formation amorphous semiconductor film, and add heat energy and make its crystallization.
But, with method＜1〉and on the whole surface of substrate, form semiconductive thin film with the physical property that contains people's satisfaction, technical difficulty is arranged.And, also there is price problem, because the film formation temperature is up to more than 600 ℃, thereby can not use inexpensive glass substrate.Method＜2〉problem be that its production efficiency is low because the swept area of the excimer laser of normal use is little now.And laser can not be handled to stable and uniform all surfaces of large area substrates.Therefore, need to consider follow-on technical problem.With method＜1〉with＜2〉compare, although method＜3〉have and be common to large-area advantage, it also must add up to the high temperature more than 600 ℃.And when using the inexpensive glass substrate, need to reduce heating-up temperature.Particularly LCD Panel is increasing now, thereby needs big glass substrate.When using this big glass substrate, the big problem that substrate shrinkage that causes in the necessary heat treatment process in making semiconductor technology and distortion produce has reduced the precision of mask plate positional precision and analog thereof.In fact, because the deformation temperature of 7059 glass that the most generally use is 593 ℃ now, common heating method for crystallising causes the large area deformation of substrate.And except that the problem that temperature causes, crystallization is wanted more than tens hours required heating time in method in common, thereby, need this heating time to shorten.
Therefore, the objective of the invention is, a kind of method is provided, film with the heating amorphous silicon constitutes makes its crystallization, makes the crystal silicon semiconductor film, it is temperature required to realize both having reduced crystallization in this manufacture method, shortens required heating time again, solves described problem.With the physical property that crystal silicon semiconductor had that the method for the invention is made, equal or exceed the physical property of the Si semiconductor made from prior art, and can be used as TFT
sThe active layer district.
The present inventor has carried out following experiments, and to studying with CVD method or sputtering method and heating makes the method for its crystallization form the Si semiconductor film to film method.
At first on glass substrate, formed amorphous si film, then, by experiment, studied and heated the mechanism that film makes its crystallization, the at the interface crystal of discovery between glass substrate and amorphous silicon begins growth, when film thickness during greater than certain thickness, crystal perpendicular to the direction of substrate surface with columnar growth.
Above-mentioned phenomenon can be considered to that following reason causes, because have nucleus (seed crystal) at the interface between glass substrate and amorphous silicon, nucleus is that basis, the crystal of crystal growth formed by nucleus growth.This nucleus is considered to have impurity metallic elements and crystal composition (crystal composition of silica is considered to be present in the surface of the glass substrate that is referred to as glass ceramics), and there is seldom amount in they at substrate surface.
The inventor thinks, positively introduces nucleus and may reduce crystallization temperature.In order further to confirm this effect, the inventor tests, and forms very a spot of other metallic films on glass substrate, forms amorphous si film thereon, and heating makes its crystallization then.As a result, proved that crystallization temperature reduces when forming several metal on substrate, inferred thus that crystal growth concentrates on the described material as nucleus.Then, the inventor has carried out more detailed mechanism research to the plurality of impurities metal, to reduce temperature.Determination of Multi-Impurities is Ni, Fe, Co, P
bAnd P
t
Can think that crystallization has two stages, promptly generate the initial period of nucleus and by stage of nucleus growth crystal.Test generates crystallite point under fixed temperature time just can be learnt the speed of the initial period that nucleus produces.When using foreign metal to make substrate formation amorphous si film, this time can shorten any time, and has verified the effect that nucleus reduces crystallization temperature of introducing.In addition, when when studying nucleus the heating time that changes and produce the growth of back crystal boundary, in the crystallisation procedure does after amorphous si film on being formed at a certain metal forms, the rate of crystalline growth of also unexpectedly observing after nucleus produces also increases significantly.Jin manages this mechanism and does not also have confirmation, can think that some catalytic action is effective.
Under any circumstance, find, on glass substrate, form certain metallic film of minute quantity, on this metallic film, be formed on the setting silicon thin film, then to its heating and make its crystallization, because above-mentioned two kinds of effects, be lower than under 580 ℃ the temperature through about 4 hours, the enough degree of crystallinity that just can obtain, and this is impossible in the past.
Nickel is a kind of metal with most pronounced effects in the foreign metal of this effect, is the element that the inventor selects for use.
Confirm now how nickel works.
Upward form amorphous si film at substrate (corning glass 7059) with plasma CVD method, and be more than 10 hours required heating time at the nickel film that does not form minute quantity on the substrate, in the crystallization of the amorphous thin film that forms is like this crossed kind, and heating is 600 ℃ in nitrogen.To handle be through just obtaining the crystalline state identical with above-mentioned film in about 4 hours under 580 ℃ heating-up temperature to the crystallization of the amorphous si film that forms at the nickel film then.The crystallization situation of this moment is formulated with Raman (Raman) spectrum.As can be seen, only in this regard, the effect of nickel is very big.
Because above-mentioned explanation is significantly, when amorphous si film was formed on the nickel film of minute quantity, the required time of crystallization can shorten, and crystallization temperature can reduce.Suppose that this process application is at manufacturing TFT
sIn, be described in more detail now.By the way, even the nickel film is formed on the amorphous si film, rather than when only being formed on the substrate, also having same effect, and also have same effect when nickel injects as ion, this also will describe in detail afterwards.Therefore, such series of process is referred to as the ＂ trace and adds nickel ＂.The technical trace of might realizing adds nickel (Nickel micro-ddding) in forming the amorphous si film process.
At first, illustrate that trace adds nickel.Adding minor amount of nickel has two kinds of methods, and a kind of is that formation minor amount of nickel film on substrate forms amorphous si film then on the nickel film that forms earlier.Another kind method is at first to form amorphous si film on substrate, then formation minor amount of nickel film on formed amorphous si film.These the two kinds methods that add minor amount of nickel have same purpose to reducing heating-up temperature.And understand in film forms, adopting any in sputtering method, vacuum deposition method, spin coating method and the plasma method.Then, when a spot of nickel film was formed on the substrate, the effect that a spot of nickel film is formed directly on 7059 glass substrates was more obvious compared with the effect that forms a spot of nickel film on substrate earlier.Its reason is, under the situation of using 7059 glass substrates, silicon directly contacts with nickel, and other components beyond the silica removal all have obstruction to contact or reaction, and this is very important for low temperature crystallization of the present invention.
And, add the method for nickel about trace, prove, except that on amorphous si film or below the formation contact membrane method and, adding with ion implantation that nickel (introducing) can access almost is same effect.About nickel, prove, when addition greater than 1 * 10
15Atom/centimetre
3The time, temperature can reduce.Yet, owing to work as the nickel addition greater than 5 * 10
19Atom/centimetre
3The time, the peak shape of the spectrum of single silicon chip is obviously different with the peak shape of Raman spectrum, and in fact spendable scope is considered to 1 * 10
15Atom/centimetre
3To 1 * 10
19Atom/centimetre
3Between.When the concentration of nickel less than 1 * 10
15Atom/centimetre
3The time, to the catalytic action reduction of crystallization.And, when concentration greater than 1 * 10
19Atom/centimetre
3The time, can locally generate NiSi, semiconducting behavior is reduced.Under crystalline state, use lower nickel concentration more favourable to semiconductor.
Then, illustrate that trace adds the structure of nickel to crystal.Know, when not adding nickel, nucleus is to generate randomly, from the nucleus of the interface piece that is in substrate and analog, crystal is grown in the direction perpendicular to substrate by the pillar-shaped crystal that arrange (110) from nucleus begin to grow randomly thickness until certain, as mentioned above, usually grow up to a thicker film, certainly, see it almost is uniform crystal growth from the cross section of whole film.In contrast, when having added a spot of nickel, the crystal growth in the zone that adds nickel be partly a crystal growth difference around.That is to say that by the confirmation of transmission electron beam microphotograph, in the zone that adds nickel, the compound of nickel that is added or nickel and silicon becomes nucleus, and the pillar-shaped crystal growth is similar with the crystal growth in the zone that does not add nickel almost perpendicular to substrate.Confirm that also crystallization at low temperatures is row in the peripheral region that does not add nickel also.In (111), arranging special crystal growth in direction, in being parallel to the direction of substrate, seeing crystal growth needle-like or column that part is arranged perpendicular to substrate.Find, by in the zone that has added minor amount of nickel along the horizontal direction that is parallel to substrate by some big crystal of having grown, its length reaches the hundreds of micron, also finds the crystal growth increase and the rising of temperature and than the increase of ratio in time.For example, be 550 ℃ in heating-up temperature, heated 4 hours, the growth length be 40 microns.But also confirm that the megacryst in laterally is monocrystalline entirely, with taken with the transmitted electron beam microscope picture shown in situation similar.When the part that is added with minor amount of nickel is detected nickel concentration, near cross growth part with to other pars amorpha far away (low temperature crystallization can not take place in the part of being considered far away, and still keep its pars amorpha) detect nickel concentration with SIMS (secondary ion mass spectroscopy determination method), in the zone that has added minor amount of nickel, detected nickel content than partly survey with cross growth nickel content lack 1 order of magnitude, and fix in the amorphous silicon and spread.The content of finding nickel in amorphous silicon is also few with the order of magnitude.Although the relation between this fact and the crystal structure is not clear,, the addition of control nickel and the position of interpolation can form the crystal silicon film with required crystal structure.
Next, illustrate that the trace that has added minor amount of nickel adds the electrical property of nickel part and close cross growth part.The electrical property that adds the nickel part about trace, conductivity with do not add nickel film conductivity much at one, that is to say, with the conductivity of film after handling through tens hours crystallization under 600 ℃ much at one, when from the temperature dependence of conductivity, finding out activation energy, when the nickel addition 10
17Atom/centimetre
3To 10
18Atom/centimetre
3The time, do not have to find by the caused desired properties of the addition of nickel.With regard to this situation, if in the active layer of TFT the nickel content in the used film or the nickel content in other used films less than 10
18Atom/centimetre
3The time, can affirm, in the work of TFT, do not have problem.
In contrast, to add the conductivity of nickel part than trace big one more than the order of magnitude for the conductivity of cross growth part.For silicon metal is suitable height.This is considered to electronics passes seldom to be had crystal or almost do not have crystal between the electrode border, because electric current causes by direction crystal cross growth direction is consistent, this result with penetrating electrons beam microscope photo is consistent, does not have contradiction.That is to say, consistent with the situation of aciculiform in the viewed direction that is parallel to substrate or pillar-shaped crystal.
Here, the various performances according to above-mentioned illustrate the method that is applied to TFT.When using TFT, in the active liquid crystal display of having used TFT, suppose that here it is used as the excitation picture element.
As above institute's art this, it is important suppressing in the highest large-screen active type LCD that glass substrate shrinks, and adds nickel with trace of the present invention and handles and allow crystallization processing under than the enough low temperature of the deformation temperature of glass, and be particularly suitable.The present invention allows to replace the generally amorphous silicon of use with the silicon metal that has added minor amount of nickel, and the crystallization through 4 hours is handled under 451 ℃ to 550 ℃.Although may need to change design criterion, go forward side by side the Xingqi he change accordingly therewith, its is suitable for conventional equipment and technology fully, and it has very big superiority.
In addition, the present invention allows to constitute the TFT as pixel
s, and allow to utilize the crystal structure corresponding with each characteristic, form the TFT of peripheral circuit driver
s, therefore, it is specially adapted to the active type LCD.That is to say that the TFT that is used as figure does not require very high mobility, but wishes that cut-off current (off curent) is less.Then, the present invention also allows to become the TFT zone as picture element, keeps not carrying out that trace adds nickel and as the amorphous region, and with the method that adds minor amount of nickel, the crystalline membrane of growing on this zone is used to form the peripheral circuit driver.That is to say,, need to reduce cut-off current, to improve qualification rate and to keep electric charge although the TFT that is formed in the picture element part does not require so high mobility.Therefore, use the TFT that adopts amorphous si film to constitute
sBe favourable, it allows to adopt manufacturing techniques available, and their performance is easy to control in the picture element part.On the other hand, consider the LCD that is applied in work station and later application, constitute the TFT of peripheral circuit
sExigent mobility.Give the TFT that constitutes the peripheral circuit driver
sNear zone add minor amount of nickel, and zone beginning thus, along a direction (growth in laterally) grown crystal, make crystal growth direction with electric current by direction (charge carrier moving direction) unanimity, have the very TFT of high mobility thereby produce effectively
s
That is to say, the objective of the invention is in semiconductor device, to provide a zone, in this zone, make optionally crystallization and keep the amorphous region of Si semiconductor film, thereby optionally on substrate, make TFT with required feature
sOn substrate, constitute the many thin-film transistors (so-called TFT) that are included in this semiconductor device resemble the glass substrate.Another object of the present invention is, the TFT with high mobility optionally is provided, and this is by making crystal growth direction consistent with charge carrier direction among the TFT, making this direction and substrate parallel.
According to the present invention, the TFT that can obtain to adopt the TFT of crystal silicon film on each required area field selectivity ground and adopt amorphous si film, its method is, make TFT the charge carrier moving direction and basic the TFT of crystal growth direction in when work with high mobility optionally to obtain, and other regioselectivity the TFT of employing amorphous si film is provided.
As mentioned above, the method with adding minor amount of nickel can make crystal growth direction select arbitrarily, or perpendicular to substrate, or be parallel to substrate.And, charge carrier moving direction when TFT work can optionally be determined in the direction (direction of connection source and leakage) of the TFT that selection is constituted and position and the relation of crystal growth direction, for example, when the insulated-gate type field effect semiconductor device was used as TFT, the flow direction of above-mentioned charge carrier was exactly the direction of connection source and leakage.
The present invention can be used as active matrix-type liquid crystal display device.And the crystal silicon film that is parallel to substrate surface with crystal growth direction can obtain to have the TFT of high mobility.
In addition, the invention still further relates to the above-mentioned TFT of acquisition
sManufacture method.The technology that the present invention uses is optionally to make the crystallization district with adding minor amount of nickel.
And feature of the present invention is, forms TFT in the peripheral circuit part of LCD with crystal silicon film
s, and it is basic identical to comprise the moving direction of charge carrier among the crystal growth direction of the crystal silicon film among the TFT and the TFT.And, the TFT of the picture element part of composition LCD
sAdopt amorphous silicon to constitute simultaneously.The method that adds nickel with selectivity can be implemented in and optionally constitutes crystal silicon film and amorphous si film on the same substrate.That is to say, because required crystallized temperature was lower than 550 ℃ in adding the zone of micro-nickel, and (although think its through can crystallization behind hundreds of hour, down can crystallization through several hrs at 550 ℃) can be retained in the zone that does not add nickel in amorphous region that can crystallization under 550 ℃.
Although is that the typical case is effective with nickel as a small amount of metallic element that promotes crystallization, with cobalt (Co), iron (Fe) and platinum (Pt) also can obtain similar effects.And, although the kind of substrate is not particularly limited,, use glass substrate, when particularly making substrate, compare, can become more remarkable being lower than the practicality that obtains the inventive method of crystalline membrane under 600 ℃ the low temperature with conventional method with the large-area glass substrate.
Optionally crystallization is handled and can be obtained crystal silicon film, but after crystallization is handled, with the strong illumination crystal silicon film of laser or equivalent, can further improve the characteristic of this crystal silicon film.That is to say, can make the partially crystallizable that does not have sufficient crystallising of staying crystal edge part and other zones in this way.By the way, constitute the required zone of TFT with amorphous silicon and do not use this strong illumination, because make the amorphous silicon crystallization with this strong illumination.
Fig. 1 is the structural representation of expression by the LCD of one embodiment of the present of invention;
Fig. 2 A to 2D, the method for circuit is made in expression, and NTFT in the circuit and PTFT complementally constitute the peripheral circuit part of LCD by the embodiment of the invention;
Fig. 3 is the structure chart that obtains from top 2D with the aid of pictures;
Fig. 4 A to 4D has represented the manufacture process of NTFT, and this NTFT is formed on by in the part of the picture element in the LCD of the embodiment of the invention;
Fig. 5 A to 5E has expressed the manufacture process of TFT circuit, and this TFT circuit belongs to peripheral circuit part and the picture element part in the liquid crystal display of an alternative embodiment of the invention.
Fig. 6 A and 6B are the SEM photos on every side of the crystal region end of growth crystallization silicon thin film in the horizontal direction of the TFT of manufacturing.
Referring now to accompanying drawing, most preferred embodiment of the present invention is described.
[the 1st embodiment]
Fig. 1 is the liquid crystal display device structure top view sketch of embodiments of the invention, the picture element electrode that picture element part 10 shown in the figure has many one-tenth rectangular (not shown)s to supply with, peripheral circuit part 20 is as driving the drive circuit that each picture element electrode is used.According to the present invention, drive thin-film transistor (TFT) that picture element uses and be formed on the insulating substrate (that is glass substrate) by the peripheral circuit that they constitute.In fact, peripheral circuit partly is constituted as cmos circuit, wherein P channel-type TFT
s(PTFT) and N channel-type TFT
s(NTFT) be to adopt the silicon thin film (being called monocrystal thin films) with the crystallization of growing at horizontal direction complementally to constitute, picture element partly is the TFT that constitutes NTFT with amorphous si film
s
Fig. 2 A is the schematic diagram of indication circuit manufacture process to 2D, and the NTFT and the PTFT that wherein constitute peripheral circuit part 20 complementally constitute.Fig. 4 A to 4D is that the back is described, is illustrated in the schematic diagram of the manufacture process of the NTFT that image component partly constitutes.Owing to finish two kinds of manufacturing process on same substrate, therefore public technology is just carried out simultaneously.That is to say that step shown in Fig. 2 A to 2D is corresponding mutually with processing step shown in Fig. 4 A to 4D, therefore, finish these processing steps simultaneously respectively.
At first, forming thickness with sputtering method on glass substrate (healthy and free from worry 7059 glass) 101 is the silica counterdie 102 of 2000 dusts.Shown in Fig. 2 A, on peripheral circuit part 20, become or the thin mould formation of silica mask 103 with metal mask.By the way, because the nickel of being introduced is easy to diffuse in the silicon oxide film in the operation of back, therefore, when selecting for use silicon oxide film to make mask 103, the thickness of silicon oxide film must be greater than 1000 dusts.Make counterdie 102 expose a flute profile with mask 103.That is to say that with what seen among above-mentioned Fig. 2 A, counterdie 102 exposes a flute profile by flute profile district 100, and remainder is masked.Shown in Fig. 4 A, all surfaces of picture element part 10 masked 103 covers.Counterdie 102 is covered by mask 103.
Behind the mask 103 that provides, and the nisiloy film (chemical formula is: NiSix, and 0.4≤x≤2.5, for example, x=2.07, thickness x=2.0) they are 5 to 200 dusts, for example, and 20 dusts, it forms with sputter.Consequently, on the entire area of peripheral circuit part 20 and picture element part 10, formed the nisiloy film.Then, remove mask 103, only on zone 100, optionally form the nisiloy film.That is to say, on zone 100, optionally carried out the micro-work that adds nickel.
Next, removing after the mask 103, is 500 to 1500 dusts with plasma CVD method deposit one layer thickness, for example the Intrinsical of 1000 dusts (I-type) amorphous si film 104.Then, with its in hydrogen reduction atmosphere 550 ℃ of annealing in process 4 hours, make thin film crystallization (preferably the dividing potential drop of hydrogen is 0.1 to 1 atmospheric pressure).Although temperature can be selected in 450 ℃ to 700 ℃ temperature range, preferred temperature range is 450 ℃ to 550 ℃, expends annealing time because if annealing temperature is hanged down it, if the temperature height, it has identical result with annealing time that prior art spends.By the way, this annealing can be carried out in inert atmosphere (for example, nitrogen atmosphere) or air.
In the zone 100 that has optionally formed the nisiloy film, silicon thin film 104 is at the direction intercrystalline perpendicular to substrate 101.On the other hand, in the external zones in zone 100, crystalline region 100 beginnings are by horizontal direction (direction that the is parallel to substrate) growth of arrow 105 indications.Locate to have kept amorphous si film in the picture element part 10 that mask 103 is provided (seeing Fig. 4 B), because can crystallization under 550 ℃ through 4 hours annealing amorphous si films.By the way, the distance that is parallel to crystal growth in substrate 101 directions at arrow 105 indications is about 40 microns.
Make the amorphous si film at peripheral circuit part 20 places can crystallization with said method.Here, shown in Fig. 2 B, in peripheral circuit part 20, crystal is in laterally (being parallel to the direction of substrate 101 in) growth, amorphous silicon reservation in picture element part 10 and can crystallization.
Then, between element with TFT
sSeparately, remove the part that silicon thin film 104 needs, constitute island shape element region.In the method, if the active layer length of TFT (source/drain region, channel formation region) is within 40 microns, source/drain region and channel region can constitute with the ingrown crystalline membrane of parallel substrate 101 sides.And, if the length that constitutes channel formation region, active area with crystalline membrane can prolong again.
Then, the thickness that forms as gate insulating film with sputtering method is the silicon oxide film 106 of 1000 dusts.Make target with silica in the sputter.Substrate temperature in the sputter is 200 ℃ to 400 ℃, for example 350 ℃.Make sputtering atmosphere with oxygen and argon, argon/oxygen ratio equals 0 to 0.5, less than 0.1.Then, forming thickness with sputtering method is the 6000-8000 dust, for example the aluminium film of 6000 dusts (siliceous 0.1 to 2%).By the way, the processing step that forms silicon oxide film 106 and formation aluminium film wishes to finish continuously.
To formed aluminium patterning thin film, to form gate electrode 107 and 109.As mentioned above,
Processing step shown in Fig. 2 C and Fig. 4 C is finished simultaneously.
By the way, because oxide layer 108 and 110 thickness are the thickness of the offset gate polar region of the ion doping operation of carrying out later (operation that the impurity material ion is injected) formation, in the anodization operation, can determine the length of offset gate polar region.
Next, make mask with gate electrode 107, on every side oxide layer 108, gate electrode 109 and oxide layer on every side 110 respectively, give silicon area implanted dopant (phosphorus and boron) as element region.With hydrogen phosphide (PH
3) and diborane (B
2H
6) make impurity gas.When using hydrogen phosphide, accelerating voltage is 60 to 90KV, for example 80KV.Accelerating voltage is 40 to 80KV during with diborane, for example is 65KV.Dosage is 1 * 10
15To 8 * 10
15Centimetre
-2Phosphorus, for example 2 * 10
15/ centimetre
2Phosphorus, 5 * 10
15/ centimetre
2Boron.In the doping, cover with photoresist and do not need doped regions, every kind of element selectively mixes.Consequently, formed N- type impurity range 114 and 116 and P- type impurity range 111 and 113, therefore, can form P-channel-type TFT (PTFT) district and N-channel-type TFT (NTFT) and distinguish.And, shown in Fig. 4 C, can form N-channel-type TFT simultaneously.
Then, finish annealing, so that the impurity that active ions inject with laser radiation.Although provide laser (wavelength is 248mm, and pulse duration is 20ns) with KrF excimer (eximer) laser, other activator appliances also can use.When annealing with laser radiation, every place irradiation 2 to 10 times is for example shone 2 times, and the laser energy density of each irradiation is 200 to 400mJ/cm
2, 250mJ/cm for example
2, in laser irradiation process, substrate is heated to about 200 to 450 ℃, and to have be sharp.Because nickel has diffused in the zone of crystallization in advance, promptly carries out crystallization again with laser radiation in the laser annealing process.Therefore, with the doped impurity range 111 of p type impurity and 113 and can be activated rapidly with the assorted doped impurity range 114 and 116 of N-type.
Subsequently, forming thickness with plasma CVD method at peripheral circuit part 20 places is the silicon oxide film 118 of 6000 dusts, as the intermediate layer, shown in Fig. 2 D.After forming connecting hole on the insulator of intermediate layer, form TFT with titanium nitride and aluminium plural layers
sElectrode 117,119 and 120.At picture element part 10 places, form intermediate layer insulator 211 with silica, and after forming connecting hole, form plain conductor 213,214 and as the ITO electrode 212 of picture element electrode, shown in Fig. 4 D.At last, in an atmospheric nitrogen atmosphere, under 350 ℃,, finish TFT circuit and TFT through 30 minutes annealing in process
s
The above-mentioned circuit of making has the CMOS structure, and wherein PTFT and NTFT complementally are provided with.Then, cut into two TFT by PTFT and the NTFT that will make simultaneously
s, in above-mentioned manufacture method, also can make simultaneously two TFT independently
s
Here, in order to express zone and the TFT that has optionally introduced nickel
sBetween position relation.Figure 3 illustrates figure from top 2D with the aid of pictures.Among Fig. 3, zone 100 has optionally been carried out trace and has been added nickel and handle, and thermal annealing makes its crystal begin from the position of known nickel and grows horizontal direction (thin slice laterally).Crystal growth forms as source/drain region 111 of PTFT and 113 and channel formation region 112 in this direction.Equally, form as source/drain region 114 of NTFT and 116 and channel formation region 115.
Because the direction of carrier flow is consistent with crystal growth direction in said structure, when charge carrier moved, it can not cross over crystal boundary.Therefore can improve TFT
sWork.For example, be 120 to 150cm with the mobility of the PTFT of processing step shown in Fig. 2 A to 2D preparation
2/ VS, this proof compares the mobility 50 of the PTFT that uses prior art for preparing to 60cm
2/ VS has had raising.And the mobility that obtains among the NTFT is 150 to 180cm
2/ VS, than the mobility 80 of the NTFT that makes with prior art to 100cm
2It is high that/VS wants.
By the way, the TFT of said prior art for preparing forms amorphous si film on the glass substrate here, and 600 ℃ of this films through annealing in 24 hours, are made its crystallization, makes crystal silicon film by this method, the TFT that makes.
And, in Fig. 2 C and 2D, below gate electrode, form gate insulating film and channel formation region.As shown in Figure 3, prolonging trace again adds the nickel district and can make a plurality of TFT simultaneously
s(in Fig. 3, prolonging) with vertical.
Although the method that optionally forms the nickel film on the surface of the counterdie 102 of employing below amorphous si film 104 is (because the nickel film as thin as a wafer, be difficult to it is observed system as film), and begin grain growth from the part that has added nickel, in this way as introducing the nickel method.But, also can adopt after forming amorphous si film 104 and optionally finish the method that trace adds nickel.That is to say, can begin grown crystal from the top and the bottom of amorphous si film.Can begin grown crystal from the top and the bottom of amorphous si film.And, also can adopt and be pre-formed amorphous si film, give the method for selectivity injection nickel ion in the amorphous si film 104 then with the ion doping method.This method has the advantage of may command nickel element concentration.
And, be not all to need to make crystal growth direction to be parallel to the method for carrier flow.Between the flow direction of carrier flow and crystal growth direction, an angle is set arbitrarily, can controls TFT
sPerformance.
[the 2nd embodiment]
The 2nd embodiment is shown among Fig. 5 A to 5E and Fig. 6 A and the 6B.Forming thickness on glass substrate 501 surfaces is 1000 to 5000 dusts, for example after the silicon oxide film 502 of 2000 dusts, forming thickness thereon with plasma CVD method is 300 to 1500 dusts, the amorphous si film of 500 dusts for example, then, forming thickness more in the above is 500 to 1500 dusts, for example, and the silicon oxide film 504 of 500 dusts.Preferably can form these films continuously.Then, optionally etching oxidation silicon thin film 50A constitutes a window region 506 introducing nickel.At the TFT that makes as peripheral circuit
sThe district forms window region 506, and does not form window region 506 in the picture element part.
Next, form nickel salt film 505 with spin coating method.Below spin coating method will be described.At first, water or alcohol dilution nickel acetate or nickel nitrate, its concentration is 25 to 200ppm, for example 100ppm is as film 505.
On the other hand, substrate is soaked or steeps in the mixed solution of hydrogenperoxide steam generator or hydrogen peroxide and ammoniacal liquor, window region 506 places formation silicon oxide film as thin as a wafer exposing amorphous si film improves the above-mentioned made nickel solution and the interface affinity of amorphous thin film.
To be placed in the centrifuge by the substrate that top method was handled and rotation at leisure.Then, on substrate, drip 1 to 10 milliliter of for example 2 milliliters of nickel solution, solution is spread out on all surfaces of substrate.This state was kept 1 to 10 minute for example 5 minutes.Then, increase rotary speed and finish Rotary drying.This operation can repeat repeatedly.Form rare nickel salt film 505 (Fig. 5 A) thus.
In heating furnace 520 ℃ to 580 ℃ through 4 to 12 hours, for example 550 ℃ through 8 hours, finish heat treatment.Heat-treating atmosphere is a nitrogen.Consequently, nickel diffuses into the just following zone of window region 506, and begins crystallization by this zone.Then, crystal region expands the into peripheral region of the indication of arrow 508.On the other hand, the zone of leaving window region 506 crystallization not.And remain amorphous silicon 509 (Fig. 5 B).
Then, with KrF excimer (eximer) laser (wavelength is 248nm) or XeCl excimer (excimer) laser (wavelength: 308nm) in the air or oxygen atmosphere, shine and for example shine (shots) 5 times 1 to 20 time, further improve degree of crystallinity.The energy density of laser is 200 to 350mJ/cm
2, substrate temperature is 200 to 400 ℃.By the way, image component partly covers with metal mask 510, makes it not by laser radiation.Perhaps, the shape of laser beam is configured to wire or other shapes again, makes laser can not be mapped to picture element part (Fig. 5 C).
After the laser radiation, etch silicon film 503 constitutes peripheral circuit and picture element TFT district partly.The former is made up of crystal silicon film, and the latter is made up of amorphous si film.Then, forming thickness on all surfaces is 1000 to 1500 dusts, the silicon oxide film 511 of 1200 dusts for example, and with aluminium and its anodic film formation gate electrode 512,513 and 514, identical with the situation of the 1st embodiment.Gate electrode 512 is used for the PTFT of peripheral circuit, and gate electrode 513 is used for the NTFT of peripheral circuit, and gate electrode 514 is used for the TFT of picture element part.
Identical with the 1st embodiment, make mask with these gate electrodes and N-type and P-type impurity are injected silicon thin film with ion implantation.Its result: constituted the source 515 of PTFT in the peripheral circuit, raceway groove 516 and leak 517, the source 520 of NTFT in the peripheral circuit, raceway groove 519 and leak 518, the source 521 of NTFT in the image component part, raceway groove 522 and leak 523.Then, identical with the 1st embodiment, use the laser radiation all surfaces, activate the impurity (Fig. 5 D) that mixes.
Forming thickness is 3000 to 8000 dusts, and for example the silicon oxide film of 5000 dusts is made the intermediate layer insulator.And forming thickness with sputtering method is 500 to 1000 dusts, the ito thin film of 800 dusts for example, and its needle drawing formed picture element electrode 525.At TFT
sSource/leak constitute connecting hole, the deposit Titanium Nitrate (thickness: 1000 dusts) and aluminium (thickness: double-layer films 5000 dusts) to its needle drawing, constitutes electrode and goes between 526 to 530.Therefore, peripheral circuit can constitute with silicon metal, and the picture element part can constitute (Fig. 5 E) with amorphous silicon.
According to coming embodiment, shown in Fig. 5 C, like that, be retained in the amorphous composition in the silicon crystal body of aciculiform generation with laser radiation, make its crystallization.Needle-shaped crystals is by crystallization, and therefore, it is the center chap with the needle-shaped crystals as nucleus.It causes that the zone that electric current flows through enlarges, and allows less leakage current and flow through.
Silicon thin film attenuate after those crystallizations uses transmission electron microscope (TEM) to observe then.Fig. 6 A is the end photo on every side of the crystallized regions of the silicon thin film of crystallization by cross growth, and can observe needle-shaped crystals.As shown in Figure 6A, in crystal, there is the amorphous region that does not much have crystallization.
When the condition of pressing present embodiment is used laser radiation, obtain the photo shown in Fig. 6 B.Although with this method make the amorphous region crystallization that accounts for most of area among Fig. 6 A, because the crystallization district generates randomly, therefore, electrical property is not so good.It should be noted the crystalline state in the zone, existing among near observed needle-shaped crystals this regional center, having or not the setting composition.In this zone, use the method that begins to grow from needle-shaped crystals, form coarse grain zone (Fig. 6 B).
Photo among Fig. 6 A and the 6B represents to have by observation the situation of the crystal end region of considerable amorphous existence, so that understand the crystal growth state on the photo rapidly.Crystal growth state around the nucleus is identical with middle growth conditions.Therefore, use laser radiation, pars amorpha may reduce, and needle-shaped crystals can chap, and can further improve the characteristic of TFT.
As mentioned above, in the active array type liquid crystal display, the TFT of peripheral circuit part
sBe by constituting at the crystalline membrane that is parallel to carrier flow direction growth, the TFT of picture element part is made of amorphous si film.Therefore, high speed operation can be realized, the switch element that needs to keep electric charge can be provided with little cut-off current in the picture element part at peripheral circuit part.
Claims (7)
1. a device comprises: the first film transistor comprises:
Be positioned at on-chip first semiconductor film, described semiconductor film comprises a source region.A drain region and a channel formation region,
The first grid electrode adjacent with described first semiconductor film;
Be positioned at first insulating film of intermediate layer on described first semiconductor film, described first grid electrode and described first grid dielectric film;
Be positioned on described first insulating film of intermediate layer and contact with it, and be connected to first electrode in the described source region of described first semiconductor film;
Be positioned on described first insulating film of intermediate layer and contact with it, and be connected to second electrode in the described drain region of described first semiconductor film;
The picture element electrode that is positioned on described first insulating film of intermediate layer and contacts with it;
At described on-chip at least one second thin-film transistor and the 3rd thin-film transistor, each comprises:
Be positioned at described on-chip second semiconductor film, described second semiconductor film comprises a source region, a drain region and a channel formation region,
Second gate electrode adjacent with described second semiconductor film;
Second gate insulating film between described second semiconductor film and described second gate electrode;
Be positioned at second insulating film of intermediate layer on described second semiconductor film, described second gate electrode and described second gate insulating film;
Be positioned on described second insulating film of intermediate layer and contact with it, and be connected to the third electrode on described second thin-film transistor; With
Be positioned on described second insulating film of intermediate layer and contact with it, and be connected to the 4th electrode on described the 3rd thin-film transistor;
The wherein said second and the 3rd thin-film transistor constitutes a CMOS structure.
2. according to the device of claim 1, wherein said the first film transistor is a N channel TFT.
3. according to the device of claim 1, wherein each described first insulating film of intermediate layer film and described the 3rd insulating film of intermediate layer comprise silica.
4. according to the device of claim 1, wherein said first insulating film of intermediate layer and described second insulating film of intermediate layer are same films.
5. according to the device of claim 1, each described first electrode wherein, described second electrode, described third electrode and described the 4th electrode comprise the multilayer film of titanium nitrogen and aluminium.
6. according to the device of claim 1, wherein said device has a picture element part and a peripheral circuit part, and described picture element partly comprises described the first film transistor and described peripheral circuit portion branch comprises described CMOS structure.
7. according to the device of claim 1, wherein said device is a liquid crystal display device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP147001/1993 | 1993-05-26 | ||
| JP14700193 | 1993-05-26 | ||
| JP147001/93 | 1993-05-26 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN94107606A Division CN1058584C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and fabrication method of the same |
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|---|---|
| CN1258104A true CN1258104A (en) | 2000-06-28 |
| CN100350627C CN100350627C (en) | 2007-11-21 |
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|---|---|---|---|
| CNB991202600A Expired - Lifetime CN100379017C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and its mfg. method |
| CNB2006101030033A Expired - Fee Related CN100501980C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and its production method |
| CN94107606A Expired - Fee Related CN1058584C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and fabrication method of the same |
| CNB991202597A Expired - Lifetime CN100350627C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and its mfg. method |
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| CNB991202600A Expired - Lifetime CN100379017C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and its mfg. method |
| CNB2006101030033A Expired - Fee Related CN100501980C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and its production method |
| CN94107606A Expired - Fee Related CN1058584C (en) | 1993-05-26 | 1994-05-26 | Semiconductor device and fabrication method of the same |
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|---|---|
| KR (1) | KR0180573B1 (en) |
| CN (4) | CN100379017C (en) |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1331189C (en) * | 2001-12-21 | 2007-08-08 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| CN100347820C (en) * | 2002-05-22 | 2007-11-07 | 统宝香港控股有限公司 | Active matrix display devices and the manufacture thereof |
| CN100365763C (en) * | 2003-06-03 | 2008-01-30 | 株式会社液晶先端技术开发中心 | Method and apparatus for forming crystallized semiconductor layer, and method for manufacturing semiconductor apparatus |
| CN100367487C (en) * | 2002-04-22 | 2008-02-06 | 因芬尼昂技术股份公司 | Method for the production of thin metal-containing layers having low electrical resistance |
| CN103903565A (en) * | 2014-01-13 | 2014-07-02 | 友达光电股份有限公司 | Pixel of display panel |
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| TW451284B (en) | 1996-10-15 | 2001-08-21 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
| TWI282126B (en) * | 2001-08-30 | 2007-06-01 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
| KR100514181B1 (en) * | 2003-09-03 | 2005-09-13 | 삼성에스디아이 주식회사 | series thin film transistor, active matrix oled using the same and fabrication method of the active matrix oled |
| CN101140940A (en) * | 2006-08-18 | 2008-03-12 | 株式会社液晶先端技术开发中心 | Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors |
| CN101419986B (en) * | 2008-12-05 | 2011-05-11 | 北京时代民芯科技有限公司 | Double edge total dose resistant radiation reinforcement pattern construction preventing edge electricity leakage |
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| JPS55162224A (en) * | 1979-06-06 | 1980-12-17 | Toshiba Corp | Preparation of semiconductor device |
| US4727044A (en) * | 1984-05-18 | 1988-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of making a thin film transistor with laser recrystallized source and drain |
| EP0178447B1 (en) * | 1984-10-09 | 1993-02-17 | Fujitsu Limited | A manufacturing method of an integrated circuit based on semiconductor-on-insulator technology |
| JPS61102628A (en) * | 1984-10-25 | 1986-05-21 | Sony Corp | Liquid crystal display device |
| JP2655865B2 (en) * | 1988-03-16 | 1997-09-24 | 株式会社日立製作所 | Manufacturing method of liquid crystal display device |
| JP2653099B2 (en) * | 1988-05-17 | 1997-09-10 | セイコーエプソン株式会社 | Active matrix panel, projection display and viewfinder |
| JPH0227320A (en) * | 1988-07-18 | 1990-01-30 | Hitachi Ltd | Thin film semiconductor display device and its manufacture |
| JPH0252419A (en) * | 1988-08-16 | 1990-02-22 | Sony Corp | Manufacture of semiconductor substrate |
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- 1994-05-25 TW TW083104759A patent/TW281786B/zh not_active IP Right Cessation
- 1994-05-26 CN CNB991202600A patent/CN100379017C/en not_active Expired - Lifetime
- 1994-05-26 CN CNB2006101030033A patent/CN100501980C/en not_active Expired - Fee Related
- 1994-05-26 KR KR1019940011756A patent/KR0180573B1/en not_active IP Right Cessation
- 1994-05-26 CN CN94107606A patent/CN1058584C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1331189C (en) * | 2001-12-21 | 2007-08-08 | 株式会社半导体能源研究所 | Semiconductor device and mfg. method thereof |
| US7319055B2 (en) | 2001-12-21 | 2008-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam |
| CN100367487C (en) * | 2002-04-22 | 2008-02-06 | 因芬尼昂技术股份公司 | Method for the production of thin metal-containing layers having low electrical resistance |
| CN100347820C (en) * | 2002-05-22 | 2007-11-07 | 统宝香港控股有限公司 | Active matrix display devices and the manufacture thereof |
| CN100365763C (en) * | 2003-06-03 | 2008-01-30 | 株式会社液晶先端技术开发中心 | Method and apparatus for forming crystallized semiconductor layer, and method for manufacturing semiconductor apparatus |
| CN103903565A (en) * | 2014-01-13 | 2014-07-02 | 友达光电股份有限公司 | Pixel of display panel |
| CN103903565B (en) * | 2014-01-13 | 2016-03-02 | 友达光电股份有限公司 | Pixel of display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW281786B (en) | 1996-07-21 |
| CN100379017C (en) | 2008-04-02 |
| KR940027187A (en) | 1994-12-10 |
| CN1881568A (en) | 2006-12-20 |
| CN1058584C (en) | 2000-11-15 |
| CN100501980C (en) | 2009-06-17 |
| CN100350627C (en) | 2007-11-21 |
| KR0180573B1 (en) | 1999-03-20 |
| CN1258102A (en) | 2000-06-28 |
| CN1101167A (en) | 1995-04-05 |
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