CN1236967A - 保险丝锁存电路 - Google Patents

保险丝锁存电路 Download PDF

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Publication number
CN1236967A
CN1236967A CN99107047A CN99107047A CN1236967A CN 1236967 A CN1236967 A CN 1236967A CN 99107047 A CN99107047 A CN 99107047A CN 99107047 A CN99107047 A CN 99107047A CN 1236967 A CN1236967 A CN 1236967A
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Prior art keywords
fuse
latch circuit
transistor
signal
control signal
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CN99107047A
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CN1192412C (zh
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T·T·勒
H·施奈德
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Infineon Technologies AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Fuses (AREA)

Abstract

本发明涉及保险丝锁存电路,其中,借助于彼此时间错开的第1和第2控制信号(FINIT,FSET)从保险丝(10)可读出保险丝信息进入并可在其中存储。这时借助一个延迟部件仅由一个总信号可获得两个控制信号(FINIT,FSET)。

Description

保险丝锁存电路
本发明涉及保险丝锁存电路，其中，借助彼此时间错开的第一和第二控制信号，可以从保险丝读出保险丝信息(例如保险丝是有毛病的或完好的)进入锁存部件内和可在其中存储。
在接通供电电压时，从保险丝读出保险丝信息之后，在保险丝锁存电路内，对于半导体器件例如半导体存储器运行的保险丝信息应当是可存储的。
图2给出这样一种现行的保险丝锁存电路，它由具有一个第1倒相器2，一个具有一个P沟道MOS晶体管3的第2倒相器和一个n沟道MOS晶体管4构成的锁存存储器部件1构成。晶体管3、4处于与一个n沟道晶体管5串联，后者的源电极与地相连。MOS晶体管3,4的控制极互连，并且与倒向器2的输出端相连。此外，倒相器2的输入端接到晶体管3、4之间的节点上。
具有图2所示曲线的保险丝初始化信号FINIT被引入到输入接线端6，并且加在P沟道MOS晶体管7的控制极和n沟道MOS晶体管5的控制极上。此外，保险丝设置信号FSET被引入到与n沟道MOS晶体管9连接的输入接线端8。晶体管7和9处于与保险丝10和供电电压串联。
在保险丝锁存电路起动时，首先起始信号FINIT被引入到输入接线端6，由此，一旦该信号变“高”(逻辑“1”)，晶体管5打开，而晶体管7闭合。在这时刻，晶体管9仍受阻塞。在输入接线端8上的保险丝设置信号FSET变高后，晶体管9打开，因此保险丝10的保险丝信息可写入锁存部件1里。在保险丝设置信号FSET又下降之后，晶体管9阻塞，因此，在锁存部件1内的信息保持写入。
图2的现行保险丝锁存电路绝对必要有两个总控制信号，即信号FINIT和FSET，这意味着总布线的高开支，并且很难预防在一只芯片上分布时两个总控制信号彼此之间的渡越时间问题。
因此本发明的任务是提供只有一个总控制信号也够用的保险丝锁存电路，以便因此降低总布线的开支，并且排除在总控制信号之间出现的渡越时间问题。
根据本发明在本文一开始所述类型的保险丝锁存电路情况下，本任务通过如下方式解决，即，借助于延时部件由一个总起始信号除获得第一控制信号之外还获得第二控制信号。
因此，在本发明的保险丝锁存电路情况下在现行的电路中另外增加了两个基本的其它措施：
(a)控制信号之一可由另外的总控制信号通过时间延迟获得，为此能以有利的方式使用倒相器。
(b)在经一开关，例如一NMOS晶体管，起始之后，保险丝才接地，以便在起始期间阻止在完好的保险丝情况下存在的分路电流。
本发明依靠附图详细说明如下。即：
图1示出用于说明本发明的保险丝锁存电路的线路图，以及
图2示出用于说明现行的保险丝锁存电路的线路图。
图2已经在本文一开始描述过了。在图1对于彼此相当的部件，使用如图2所示的相同的参考符号。
在本发明的保险丝锁存电路中，在现行电路中(试比较：尤其是处在虚线11左侧部分)还加有由一P沟道MOS晶体管14，一n沟道MOS晶体管15和一n沟道MOS晶体管17组成的延迟部件，其中这些晶体管14,15和17串联在地和供电电压之间。保险丝初始信号FINIT被引入到输入接线端16，如被引入到输入接线端6一样，从该保险丝初始信号FINIT借助于由晶体管14,15和17组成的延迟部件获得保险丝设置信号FSET，此信号被输送给晶体管9的控制极(如图2所示)。这时附加的一n沟道MOS晶体管15在信号FINIT和FSET之间即信号FINIT的低-高-脉冲沿和信号FSET的高-低-脉冲沿之间产生一时间延迟τ。
在初始化阶段，信号FINIT设置在逻辑“0”(“低”)，由此晶体管7接通，并且锁存电路部件1就用逻辑“1”(“高”)预初始化了。在锁存部件1的初始化阶段，信号FSET处于逻辑“1”。通过完好的保险丝的分路电流被晶体管T5所阻止。
在初始化后信号FINIT从逻辑“0”(“低”)变换为逻辑“1”(“高”)。基于由晶体管T14,T15和T17组成的延迟部件，在时间τ期间，信号FSET保持在逻辑“1”。因为现在晶体管T5接通，所以保险丝信息如下所示写入锁存部件1：
(a)如果保险丝10是完好的，倒相器2的输入端转向逻辑“0”，由此锁存部件1复位。
(b)反之，如果保险丝有毛病(例如通过激光照射)，于是逻辑“1”(“高”)被存储在锁存部件1内。
在时间延迟τ后，信号FSET变为低值，由此晶体管9关断，保险丝与锁存部件1脱耦。
与图2现行的保险丝锁存电路不同，本发明的保险丝锁存电路的保险丝10处在晶体管9和晶体管4、5的节点之间。由此，在电路起动时完好的保险丝实现无分路电流流过。
有时，为了延迟也还额外备配了两个倒相器12,13，然而这并不是必需的，因为延迟也能够单独“装进”晶体管14,15,17之中。
因此本发明仅由一个总信号实现本地产生必须的控制信号，所以实现了有关节约总布线和阻止在一只芯片上在分配时各总控制信号之间彼此渡越时间问题的主要优点。

Claims (3)

1．保险丝锁存电路，其中，借助彼此时间错开的第1和第2控制信号，可以从保险丝(10)读出与保险丝(10)状态相应的信息，进入锁存电路(1)并在其内储存，其特征为，
仅由一个总起始化信号借助延迟部件(14,15,17；12,13)除获得第1控制信号(FINIT)外，还获得第2控制信号(FSET)，并且
保险丝(10)处在同一导电类型的两个MOS晶体管(9,5)的源-漏电路段之间。
2．根据权利要求1所述的保险丝锁存电路，其特征为：延迟部件由晶体管(14,15,17)组成。
3．根据权利要求2所述的保险丝锁存电路，其特征为：此外为了延迟还配备了倒相器(12,13)。
CNB99107047XA 1998-05-27 1999-05-26 保险丝锁存电路 Expired - Fee Related CN1192412C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823687.5 1998-05-27
DE19823687A DE19823687A1 (de) 1998-05-27 1998-05-27 Fuselatch-Schaltung

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CN1236967A true CN1236967A (zh) 1999-12-01
CN1192412C CN1192412C (zh) 2005-03-09

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US (1) US6215351B1 (zh)
EP (1) EP0961291B1 (zh)
JP (1) JP3737908B2 (zh)
KR (1) KR100324811B1 (zh)
CN (1) CN1192412C (zh)
DE (2) DE19823687A1 (zh)
TW (1) TW425562B (zh)

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DE10051167B4 (de) 2000-10-16 2007-10-25 Infineon Technologies Ag Anordnung zur Fuseinitialisierung
US6288598B1 (en) * 2000-11-02 2001-09-11 Lsi Logic Corporation Laser fuse circuit design
US6426668B1 (en) * 2001-03-22 2002-07-30 International Business Machines Corporation Imbalanced sense amplifier fuse detection circuit
US6781437B2 (en) * 2001-07-11 2004-08-24 Infineon Technologies Aktiengesellschaft Zero static power programmable fuse cell for integrated circuits
US6839298B2 (en) 2001-07-11 2005-01-04 Infineon Technologies Aktiengesellschaft Zero static power fuse cell for integrated circuits
US6891404B2 (en) * 2002-06-11 2005-05-10 Infineon Technologies Auto-adjustment of self-refresh frequency
US6798272B2 (en) * 2002-07-02 2004-09-28 Infineon Technologies North America Corp. Shift register for sequential fuse latch operation
KR100615596B1 (ko) * 2004-12-22 2006-08-25 삼성전자주식회사 반도체 장치
US7567115B2 (en) * 2007-11-01 2009-07-28 Elite Semiconductor Memory Technology Inc. Fuse-fetching circuit and method for using the same

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US5640365A (en) * 1994-09-09 1997-06-17 Kabushiki Kaisha Toshiba Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency
US5566107A (en) * 1995-05-05 1996-10-15 Micron Technology, Inc. Programmable circuit for enabling an associated circuit
KR0147194B1 (ko) * 1995-05-26 1998-11-02 문정환 반도체 메모리 소자
US5680360A (en) * 1995-06-06 1997-10-21 Integrated Device Technology, Inc. Circuits for improving the reliablity of antifuses in integrated circuits
DE19631130C2 (de) * 1996-08-01 2000-08-17 Siemens Ag Fuse-Refresh-Schaltung

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Publication number Publication date
DE19823687A1 (de) 1999-12-09
EP0961291B1 (de) 2006-09-27
KR100324811B1 (ko) 2002-02-20
US6215351B1 (en) 2001-04-10
KR19990088553A (ko) 1999-12-27
CN1192412C (zh) 2005-03-09
JP3737908B2 (ja) 2006-01-25
TW425562B (en) 2001-03-11
JP2000057798A (ja) 2000-02-25
DE59913873D1 (de) 2006-11-09
EP0961291A1 (de) 1999-12-01

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