CN1235280C - Manufacture of deep-channel capacitor - Google Patents
Manufacture of deep-channel capacitor Download PDFInfo
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- CN1235280C CN1235280C CN 02118539 CN02118539A CN1235280C CN 1235280 C CN1235280 C CN 1235280C CN 02118539 CN02118539 CN 02118539 CN 02118539 A CN02118539 A CN 02118539A CN 1235280 C CN1235280 C CN 1235280C
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- deep trouth
- semiconductor substrate
- photoresist layer
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Abstract
The present invention firstly forms an embedded electrode at the bottom of a deep groove on the surface of a semiconductor substrate. A dielectric layer is formed on surfaces of the substrate and the deep groove and a photoresist layer is filled. Subsequently, an exposure and development process is performed to remove the photoresist layer with a preset depth in the deep groove and make the top of the photoresist layer which is residual in the deep channel level with the top of the embedded electrode slightly. Finally, the dielectric layer uncovered by the photoresist layer is removed, and one oxidation technology, two polysilicon deposition, one chemical and mechanical polishing and one polysilicon recessed etching technology are orderly performed to form one storage electrode.
Description
Technical field
(dynamic random access memory, the manufacture method of capacity cell DRAM) specifically provide the manufacture method of a kind of deep trouth (deep trench) electric capacity to the invention provides a kind of dynamic random access memory.
Background technology
Dynamic random access memory (DRAM) is to be assembled by the huge memory cell of number (memory cell) to form.Each memory cell all includes a switching transistor (pass transistor), be generally a metal oxide semiconductor transistor (metal-oxide-semiconductor field-effect transistor, and a storage capacitors (storage capacitor) MOSFET).And improving constantly along with the technology integrated level, the trend of making semiconductor integrated circuit now is to carry out DRAM memory cell array (memory cellarray) and high speed logic circuit element (high-speed logic circuit elements) integrated, be produced on simultaneously on the chip (chip), form a kind of embedded type dynamic random access memory (Embedded DRAM that combines memory array and logical circuit (logiccircuits) simultaneously, E-DRAM), significantly to save area and to accelerate Signal Processing speed.Wherein, the reservior capacitor of the memory cell stack capacitor (stack capacitor) that is designed to be stacked in substrate surface mostly and two kinds of the deep-channel capacitors of imbedding in the substrate (deep trenchcapacitor).
Please refer to Fig. 1 to Figure 10, Fig. 1 to Figure 10 has the method schematic diagram of making an E-DRAM deep-channel capacitor on the semiconductor chip now.As shown in Figure 1, substrate 14 surfaces of semiconductor chip 10 include a periphery circuit region 11 and a storage array district 12,12 surfaces, storage array district are formed with a laying 16, and laying 16 includes the substrate 14 of a plurality of deep trouths 17 sensible its belows, the degree of depth is about 7 to 7.5 microns (μ m), is used for forming follow-up deep-channel capacitor.
As shown in Figure 2, utilize an arsenic silex glass (ASG) to fill up deep trouth 17 subsequently, carry out a carving technology etching again and insert arsenic silex glass in the deep trouth 17, make the arsenic silex glass thickness that residue in the deep trouth 17 be about deep trouth 17 degree of depth 60% to 90% between (not shown), be used as a dopant source (dopant source).Then utilize the thermal diffusion process of 800 to 900 ℃ of temperature, make in the arsenic silex glass that residues in the deep trouth 17 the arsenic atom diffusion to substrate 14 that the arsenic silex glass contacts in, to form an embedded electrode (burieddiffused plate) 18.
After finishing thermal diffusion process, remove the arsenic silex glass that residues in the deep trouth 17 immediately.Then on substrate 14, deposit the silicon nitride layer 20 that a thickness is about 100 to 300 dusts again.In deep trouth 17, insert a photoresist layer 22 then, and photoresist layer 22 surface trim with embedded electrode 18 upper ends roughly.Wherein, silicon nitride layer 20 is covered on the surface of laying 16 and deep trouth 17 equably, and the method that forms photoresist layer 22 is earlier photoresist liquid to be inserted deep trouth 17 in the spin coating mode, treat that photoresist liquid is behind overbaking, utilize an oxygen gas plasma to return the photoresist of quarter again, to form the photoresist layer 22 of desired thickness through the overbaking drying.
As shown in Figure 3, next carry out a wet etching, for example utilize hot phosphoric acid solution, remove the silicon nitride layer 20 that is not covered, to expose substrate 14 surfaces at neck position, deep trouth 17 upper end 23 by photoresist layer 22.After having removed photoresist layer 22, then as shown in Figure 4, carry out a high temperature oxidation process, for example be heated to about 900 to 1000 ℃ rapid thermal oxidation process (rapid thermal process, RTP) under the environment that contains steam, go up generation one first oxide-film (not shown) in silicon nitride layer 20 surfaces, and substrate 14 surperficial the going up that exposed in neck position, upper end 23 simultaneously generate one second oxide-film.Wherein, first oxide-film and silicon nitride layer 20 form (nitride-oxide) capacitance dielectric layer 24 of mononitride-oxide (NO) jointly on embedded electrode 18, be used for isolating the storage electrode and the embedded electrode 18 of follow-up formation, and second oxide-film, be called neck oxide layer 26 again, the thickness that generates is about 200 to 300 dusts, in the hope of reaching the purpose that reduces parasitic leakage current (parasitic leakage).
Subsequently as shown in Figure 5, at semiconductor chip 10 surface depositions one doped polysilicon layer 28, and make it fill up deep trouth 17 fully.(chemical mechanical polish, CMP) technology are removed part doped polysilicon layer 28, make rough the trimming in laying 16 surfaces in doped polysilicon layer 28 surfaces to utilize laying 16 to carry out a chemico-mechanical polishing as the polishing stop layer then.
As shown in Figure 6, carry out one first polysilicon and concavely etch technology, with reactive ion etching (reactiveion etching, RIE) the part doped polysilicon layer 28 in the deep trouth 17 is removed on process choice ground, make doped polysilicon layer 28 surfaces be lower than the hundreds of approximately dusts in substrate 14 surfaces, forming a groove, and expose the neck oxide layer 26 of part.As shown in Figure 7, then carry out an etch process, remove the neck oxide layer 26 that exposes, the substrate 14 of deep trouth 17 upper end neck position 23a is exposed.
As shown in Figure 8, carry out a CVD technology subsequently at semiconductor chip 10 surface depositions one undoped polycrystalline silicon layer 30, and make undoped polycrystalline silicon layer 30 fill up groove.As shown in Figure 9, utilize laying 16, carry out a CMP technology, remove part undoped polycrystalline silicon layer 30 so that undoped polycrystalline silicon layer 30 surface and rough the trimming in laying 16 surfaces as stop layer.Then carry out one second polysilicon and concavely etch technology, return with RIE and carve undoped polycrystalline silicon layer 30, make undoped polycrystalline silicon layer 30 surface be lower than laying 16 surfaces.
At last as shown in figure 10, carry out a wet etching process to remove laying 16 fully.Because the hydrophobicity of undoped polycrystalline silicon layer 30 and oxidation resistance are all than doped polysilicon layer the last 28, therefore in follow-up cleaning process, undoped polycrystalline silicon layer 30 can be considered a top cover protective layer (cap layer), is used for protecting doped polysilicon layer 28.Utilize a thermal diffusion process subsequently again, under hot environment with the dopant in the doped polysilicon layer 28, become into (drive in) contiguous substrate 14 surfaces via undoped polycrystalline silicon layer 30 and neck position, upper end 23a, form a shallow junction (shallow junction) 32.In the process that becomes, undoped polycrystalline silicon layer 30 also is doped because of the dopant in the diffusing, doping polysilicon layer 28 simultaneously, and finishes a storage electrode 34 and electric capacity 36.
As shown in the above description, in the step of existing formation deep-channel capacitor, comprise and earlier photoresist liquid is inserted deep trouth 17 in the spin coating mode, return the photoresist of quarter again through the overbaking drying, in deep trouth 17, to form the photoresist layer 22 of desired thickness, as shown in Figure 2.Yet the height that photoresist floor 22 covers can be different with storage array district 12 at periphery circuit region 11, because 12 surfaces, storage array district are formed with the deep trouth 17 of a large amount of arrays, so photoresist liquid can sink after covering baking, to such an extent as to its height can be lower than periphery circuit region 11, especially the photoresist floor 22 on periphery circuit region 11 and 12 adjacent area surfaces, storage array district more can form a gradient because of this difference in height, therefore after time carving technology in just can fully this difference in height be transferred to the photoresist layer 22 that residues in the deep trouth 17, cause being close to that its photoresist floor 22 height can be than photoresist layer 22 height in the deep trouth 17 of storage array district's 12 middle bodies in the deep trouth 17 of periphery circuit region 11, as shown in figure 11, and then influence the uniformity and the acceptance rate of follow-up deep-channel capacitor technology.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of deep trouth that is used to make deep-channel capacitor to insert (deeptrench gap filling) method, to address the above problem.
In a preferred embodiment of the invention, the inventive method forms an embedded electrode in the deep trouth bottom on semi-conductive substrate surface earlier, forms a dielectric layer successively and inserts a photoresist layer at this substrate and this deep trouth surface subsequently.Then carry out an exposure and a developing process, removing this photoresist layer of a desired depth in this substrate surface and this deep trouth, and make rough the trimming in top that residues in this photoresist layer in this deep trouth in this embedded electrode top.Remove this dielectric layer that is not covered at last by this photoresist layer, and carry out successively an oxidation technology and one first and second polysilicon deposition-CMP-polysilicon concavely etch (polysilicon dep.-CMP-polysilicon recess etching) technology, to form a storage electrode.
Because the method for the photoresist layer that the present invention inserts in deep trouth, utilize an exposure and a step of developing, with the hole of deep trouth as natural mask, and control the development degree of depth by the wavelength of exposure light source and the openings of sizes of deep trouth, residual photoresist layer is reached sustained height in the deep trouth so can make, also saved the step of time carving technology simultaneously, to shorten the process time and to save production cost.
According to an aspect of the present invention, provide a kind of manufacture method of deep-channel capacitor, this manufacture method includes the following step:
Provide semi-conductive substrate, and the surface, storage array district of this Semiconductor substrate is formed with at least one deep trouth;
In this Semiconductor substrate of this deep trouth bottom, form an embedded electrode;
Form a dielectric layer in this Semiconductor substrate and this deep trouth surface;
In this semiconductor substrate surface and this deep trouth, insert a photoresist layer;
Carry out an exposure and a developing process, removing this photoresist layer of a desired depth in this semiconductor substrate surface and this deep trouth, and the top that residues in this photoresist layer in this deep trouth is trimmed in this embedded electrode top;
Remove this dielectric layer that is not covered, to expose this Semiconductor substrate that is positioned at this deep trouth first half by this photoresist layer;
Remove this photoresist layer;
Carry out an oxidation technology, form one first oxide-film and a thickness second oxide-film respectively than this first thickness of oxidation film with this semiconductor substrate surface that in this dielectric layer surface and this deep trouth, exposes simultaneously;
Carry out first polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology;
Remove this second oxide-film of part, to expose this Semiconductor substrate of this deep trouth first half part; And
Carry out second polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology, to form a storage electrode.
According to a further aspect of the invention, provide a kind of deep trouth that is used to make deep-channel capacitor to insert the method for photoresist layer, this deep-channel capacitor is made on the semi-conductive substrate, and be formed with at least one deep trouth in the storage array district of this semiconductor substrate surface, and be formed with an embedded electrode in this Semiconductor substrate of this deep trouth bottom, and this Semiconductor substrate and this deep trouth surface are formed with a dielectric layer, and this method includes the following step:
In this semiconductor substrate surface and this deep trouth, insert a photoresist layer; And
Carry out an exposure and a developing process, removing this photoresist layer of a desired depth in this semiconductor substrate surface and this deep trouth, and the top that residues in this photoresist layer in this deep trouth is trimmed in this embedded electrode top.
Description of drawings
Fig. 1 to Figure 11 is the method schematic diagram of existing making one deep-channel capacitor; And
Figure 12 to Figure 18 is the method schematic diagram according to making one deep-channel capacitor of the embodiment of the invention.
Description of reference numerals in the accompanying drawing is as follows:
10 semiconductor chips, 11 periphery circuit regions
12 storage array districts, 14 substrates
16 layings, 17 deep trouths
18 embedded electrodes, 20 silicon nitride layers
22 photoresist layers 23, neck position, 23a upper end
24NO capacitance dielectric layer 26 neck oxide layers
28 doped polysilicon layers, 30 undoped polycrystalline silicon layers
32 shallow junctions, 34 storage electrodes
36 electric capacity, 50 Semiconductor substrate
51 periphery circuit regions, 52 storage array districts
54 layings, 55 deep trouths
56 embedded electrodes, 58 silicon nitride layers
60 photoresist layers 61, neck position, 61a upper end
62NO capacitance dielectric layer 64 neck oxide layers
66 doped polysilicon layers, 68 undoped polycrystalline silicon layers
70 shallow junctions, 72 storage electrodes
74 electric capacity
Embodiment
Please refer to Figure 12 to Figure 18, Figure 12 to Figure 18 makes the method schematic diagram of an E-DRAM deep-channel capacitor on semi-conductive substrate for the present invention.As shown in figure 12, the present invention provides semi-conductive substrate 50 earlier, and Semiconductor substrate 50 surfaces include a periphery circuit region 51 and a storage array district 52.52 surfaces, storage array district are formed with a laying 54, and laying 54 includes the substrate 50 of a plurality of deep trouths 55 sensible its belows, are used for forming follow-up deep-channel capacitor.In this preferred embodiment, laying 54 is piled up by a silicon nitride layer and a pad oxide (not shown) and forms, and substrate 50 can be a silicon substrate, silicon-on-insulator (silicon-on-insulator, SOI) substrate or epitaxial silicon (epitaxy) substrate.
As shown in figure 13, subsequently as above-mentioned prior art, utilize an arsenic silex glass (ASG) to fill up deep trouth 55 as a dopant source (dopant source), and carry out the thermal diffusion process of 800 to 900 ℃ of temperature, make in the arsenic silex glass that residues in the deep trouth 55 the arsenic atom diffusion to substrate 50 that the arsenic silex glass contacts in, to form an embedded electrode (buried diffused plate) 56.After finishing thermal diffusion process, remove the arsenic silex glass that residues in the deep trouth 55 immediately, and on substrate 50, deposit the silicon nitride layer 58 that a thickness is about 100 to 300 dusts, be covered in equably on the surface of laying 54 and deep trouth 55.
In Semiconductor substrate 50 surfaces and deep trouth 55, insert a photoresist layer 60 subsequently.Then carry out a blanket exposure (full exposure) and developing process, with the photoresist layer 60 of desired depths in removal Semiconductor substrate 50 surfaces and the deep trouth 55, and make rough the trimming in photoresist layer 60 top that residues in deep trouth interior 55 in embedded electrode 56 tops.Wherein, this exposure technology utilizes the wavelength of exposure light source and the openings of sizes and the density of deep trouth 55 to control the development degree of depth, for example the present invention promptly is used as exposure light source by long wavelength's light of about 350～400 λ of a wave-length coverage, to reach the purpose of the uniform exposure degree of depth in each deep trouth 55.
Ensuing processing step is identical with above-mentioned prior art, as shown in figure 14, carry out a wet etching, for example utilize hot phosphoric acid solution, remove the silicon nitride layer 58 that is not covered, to expose substrate 50 surfaces at neck position, deep trouth upper end 61 by photoresist layer 60.After having removed photoresist layer 60, then carry out a high temperature oxidation process, for example be heated to about 900 to 1000 ℃ rapid thermal oxidation process (rapid thermal process, RTP) under the environment that contains steam, on silicon nitride layer 58 surfaces, generate one first oxide-film (not shown), and generate one second oxide-film on substrate 50 surfaces that exposed at neck position, upper end 61 simultaneously.Wherein, first oxide-film and silicon nitride layer 58 form mononitride-oxide (NO (nitride-oxide)) capacitance dielectric layer 62 jointly on embedded electrode 56, be used for isolating the storage electrode and the embedded electrode 56 of follow-up formation, and second oxide-film, be called neck oxide layer 64 again, the thickness that generates is about 200 to 300 dusts, in the hope of realizing reducing the purpose of parasitic leakage current (parasitic leakage).
Subsequently as shown in figure 15, at Semiconductor substrate 50 surface depositions one doped polysilicon layer 66, and make it fill up deep trouth 55 fully.Carry out one first polysilicon then and concavely etch technology, with reactive ion etching (reactive ion etching, RIE) the part doped polysilicon layer 66 in the deep trouth 55 is removed on process choice ground, make doped polysilicon layer 66 surfaces be lower than the hundreds of approximately dusts in substrate 50 surfaces, forming a groove, and expose part neck oxide layer 64.
As shown in figure 16, then carry out an etch process, remove the neck oxide layer 64 that exposes, the substrate 50 of deep trouth 55 upper end neck position 61a is exposed.Carry out a CVD technology subsequently at Semiconductor substrate 50 surface depositions one undoped polycrystalline silicon layer 68, make undoped polycrystalline silicon layer 68 fill up groove.Carry out a CMP technology, utilize laying 54, remove part undoped polycrystalline silicon layer 68 so that undoped polycrystalline silicon layer 68 surface and rough the trimming in laying 54 surfaces as stop layer.
At last as shown in figure 17, carry out one second polysilicon and concavely etch technology, return with RIE and carve undoped polycrystalline silicon layer 68, make undoped polycrystalline silicon layer 68 surface be lower than laying 54 surfaces.Then carry out a wet etching process to remove laying 54 fully, utilize a thermal diffusion process subsequently again, under hot environment with the dopant in the doped polysilicon layer 66, become into (drive in) contiguous substrate 50 surfaces via undoped polycrystalline silicon layer 68 and neck position, upper end 61a, form a shallow junction (shallow junction) 70.In the process that becomes, undoped polycrystalline silicon layer 68 also is doped because of the dopant in the diffusing, doping polysilicon layer 66 simultaneously, and finishes a storage electrode 72 and electric capacity 74.
Deep-channel capacitor manufacture method of the present invention is utilized an exposure and a developing process, to insert the photoresist layer 60 of equal altitudes in deep trouth 55.Wherein this exposure technology utilizes long wavelength's light of about 350～400 λ of a wave-length coverage as exposure light source, and control the degree of depth of exposing and developing in each deep trouth by the wavelength of exposure light source and the openings of sizes of deep trouth 55, make each deep trouth 55 interior residual photoresist layers 60 be sustained height simultaneously, as shown in figure 18.
Compare with the manufacture method of existing deep-channel capacitor, deep trouth of the present invention is inserted method makes the interior residual photoresist layer of deep trouth can reach sustained height, and the problem that the photoresist layer height differs in the deep trouth of periphery circuit region and storage array district adjacent area in the prior art can not take place, on the other hand, method of the present invention has been saved the step of time carving technology simultaneously, can shorten the process time and save production cost.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (9)
1. the manufacture method of a deep-channel capacitor, this manufacture method includes the following step:
Provide semi-conductive substrate, and the surface, storage array district of this Semiconductor substrate is formed with at least one deep trouth;
In this Semiconductor substrate of this deep trouth bottom, form an embedded electrode;
Form a dielectric layer in this Semiconductor substrate and this deep trouth surface;
In this semiconductor substrate surface and this deep trouth, insert a photoresist layer;
Carry out an exposure and a developing process, removing this photoresist layer of a desired depth in this semiconductor substrate surface and this deep trouth, and the top that residues in this photoresist layer in this deep trouth is trimmed in this embedded electrode top;
Remove this dielectric layer that is not covered, to expose this Semiconductor substrate that is positioned at this deep trouth first half by this photoresist layer;
Remove this photoresist layer;
Carry out an oxidation technology, form one first oxide-film and a thickness second oxide-film respectively than this first thickness of oxidation film with this semiconductor substrate surface that in this dielectric layer surface and this deep trouth, exposes simultaneously;
Carry out first polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology;
Remove this second oxide-film of part, to expose this Semiconductor substrate of this deep trouth first half part; And
Carry out second polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology, to form a storage electrode.
2. the method for claim 1, wherein to include a periphery circuit region in addition adjacent with this storage array district for this semiconductor substrate surface.
3. the method for claim 1, wherein this exposure and developing process utilize the openings of sizes of an exposure light source wavelength and this deep trouth to control the development degree of depth.
4. the method for claim 1, wherein this exposure technology utilize a long wavelength light as exposure light source, its wave-length coverage is 350～400 λ.
5. a deep trouth that is used to make deep-channel capacitor is inserted the method for photoresist layer, this deep-channel capacitor is made on the semi-conductive substrate, and be formed with at least one deep trouth in the storage array district of this semiconductor substrate surface, and be formed with an embedded electrode in this Semiconductor substrate of this deep trouth bottom, and this Semiconductor substrate and this deep trouth surface are formed with a dielectric layer, and this method includes the following step:
In this semiconductor substrate surface and this deep trouth, insert a photoresist layer; And
Carry out an exposure and a developing process, removing this photoresist layer of a desired depth in this semiconductor substrate surface and this deep trouth, and the top that residues in this photoresist layer in this deep trouth is trimmed in this embedded electrode top.
6. method as claimed in claim 5 is wherein inserted in this deep trouth after this photoresist layer, and the method that forms this deep-channel capacitor includes the following step in addition:
Remove this dielectric layer that is not covered, to expose this Semiconductor substrate that is positioned at this deep trouth first half by this photoresist layer;
Remove this photoresist layer;
Carry out an oxidation technology, form one first oxide-film and a thickness second oxide-film respectively than this first thickness of oxidation film with this semiconductor substrate surface that in this dielectric layer surface and this deep trouth, exposes simultaneously;
Carry out first polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology;
Remove this second oxide-film of part, to expose this Semiconductor substrate of this deep trouth first half part; And
Carry out second polysilicon deposition-chemico-mechanical polishing-polysilicon and concavely etch technology, to form a storage electrode.
7. method as claimed in claim 5, wherein to include a periphery circuit region in addition adjacent with this storage array district for this semiconductor substrate surface.
8. method as claimed in claim 5, wherein this exposure and developing process utilize the openings of sizes of an exposure light source wavelength and this deep trouth to control the development degree of depth.
9. method as claimed in claim 5, wherein this exposure technology utilize a long wavelength light as exposure light source, its wave-length coverage is 350～400 λ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02118539 CN1235280C (en) | 2002-04-27 | 2002-04-27 | Manufacture of deep-channel capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02118539 CN1235280C (en) | 2002-04-27 | 2002-04-27 | Manufacture of deep-channel capacitor |
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| Publication Number | Publication Date |
|---|---|
| CN1453845A CN1453845A (en) | 2003-11-05 |
| CN1235280C true CN1235280C (en) | 2006-01-04 |
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| CN 02118539 Expired - Lifetime CN1235280C (en) | 2002-04-27 | 2002-04-27 | Manufacture of deep-channel capacitor |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568817A (en) * | 2012-03-01 | 2012-07-11 | 中北大学 | MEMS (Micro Electro Mechanical System) capacitor based on three-dimensional silicon micro structure and manufacturing method thereof |
| CN113497006A (en) * | 2020-03-20 | 2021-10-12 | 中芯国际集成电路制造(北京)有限公司 | Capacitor structure and forming method thereof |
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- 2002-04-27 CN CN 02118539 patent/CN1235280C/en not_active Expired - Lifetime
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| CN1453845A (en) | 2003-11-05 |
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