CN1285120C - Bilateral Corner Rounding Process for Partially Vertical Memory Cells - Google Patents
Bilateral Corner Rounding Process for Partially Vertical Memory Cells Download PDFInfo
- Publication number
- CN1285120C CN1285120C CN03156537.9A CN03156537A CN1285120C CN 1285120 C CN1285120 C CN 1285120C CN 03156537 A CN03156537 A CN 03156537A CN 1285120 C CN1285120 C CN 1285120C
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- rounding process
- layer
- memory cells
- vertical memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 230000002146 bilateral effect Effects 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000007800 oxidant agent Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 2
- 229910017604 nitric acid Inorganic materials 0.000 claims 2
- 238000002955 isolation Methods 0.000 abstract description 5
- 238000003491 array Methods 0.000 description 18
- 238000009413 insulation Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 229960002163 hydrogen peroxide Drugs 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides a double-corner rounding process of a partial vertical memory cell, wherein the first rounding process is carried out after a groove of an isolation region is formed in a semiconductor substrate by etching, and the second rounding process is carried out after a shallow groove isolation structure is formed in a supporting region, and the corner of an active region of a memory cell array region is exposed again so as to carry out the second rounding process on the corner of the active region of the memory cell array region.
Description
Technical field
The invention relates to a kind of manufacturing method of semiconductor module, and particularly relevant for a kind of dynamic random access memory (dynamic random access memory that comprises slot type capacitor (deep trench capacitor) and part vertical transistor; DRAM) manufacture method.
Background technology
(how integrated circuit when IC) making the semiconductor subassembly of high integration on the chip, must consideration dwindles size and the power consumption of each memory cell (memory cell), so that its service speed quickening at integrated circuit.In traditional planar transistor design, in order to obtain the memory cell of a minimum dimension, must transistorized gate length be shortened, to reduce the horizontal area of memory cell as far as possible.But this can make gate can't stand excessive leakage current and must reduce the voltage of bit line accordingly, and then makes the stored electric charge of electric capacity reduce.So, at the lateral length that shortens gate simultaneously, also to consider and how make an electric capacity that has than high capacitance, for example: increase the area of electric capacity, the effective dielectric thickness between the minimizing capacitor board or the like.In order to address the above problem, high-density storage (for example: dynamic random access memory at present, DRAM) be to develop two kinds of different capacitor formation technology, a kind of is stacking-type electric capacity, another kind is deep groove capacity (deep trench capacitor), wherein the making of deep groove capacity is to form a deep trench in substrate, and makes the electric capacity storage area in deep trench, so can not take the additional areas of memory cell.In addition, a kind of vertical transistor (vertical transistor) structure in order to make gate length maintain an appropriate value that can obtain low-leakage current, also to develop, is the top that is made in deep groove capacity, not only can not reduce bit line voltage, can not increase the horizontal area of memory cell yet.
Below cooperate Fig. 1 that the structure of traditional deep groove capacity and vertical transistor is described.This semiconductor device comprises a substrate 10, a silicon base for example, and deep trench 18 is formed at wherein, and trench capacitor 14 is arranged at the Lower Half of deep trench 18.The neck ring oxide layer is the sidewall that is arranged at the first half of trench capacitor 14.The compound crystal silicon electric pole plate of capacitor 14 is to be arranged in the deep trench 18.
Imbed the diffusion region that band (buried strap) 12 is meant between slot type capacitor 14 and vertical transistor 16, and electrically contact, in order to drain as vertical transistor 16 with electric pole plate.Imbedding with 12 is the dopant ion in the doping dielectric layer (not illustrating) is driven in substrate 10 and to form via hot processing procedure.
Top silicon oxide layer (TTO) the 24th by being the formed oxide of tetraethyl-metasilicate (TEOS), is arranged on the electric pole plate, in order to as being electrically insulated between slot type capacitor 14 and the vertical transistor 16.
The structure of vertical transistor 16 comprises source electrode 26, drain 12, gate pole oxidation layer 28 and comprises the gate 20 of gate electrode 22.Gate electrode 22 is the first halves that are positioned at deep trench 18, and can partly extend to silicon base 10 surfaces.Yet, the thickness that is positioned at the gate pole oxidation layer 28 of corner 30 can be because of the difference of oxidation rate, and, make the insulating property (properties) variation of the gate pole oxidation layer 28 at 30 places, corner than the thin thickness of deep trench 18 vertical sidewalls and silicon base 10 horizontal surfaces, so can influence the quality of transistor 16.
Summary of the invention
The object of the present invention is to provide a kind of thin excessively method of gate pole oxidation layer that can avoid edge.
The present invention proposes a kind of bilateral angle sphering processing procedure of part vertical memory cell.At first, the semiconductor-based end that comprises memory cell arrays district and supporting area, be provided, has first cover curtain layer on this semiconductor-based end, first cover curtain layer and have first groove and second groove at semiconductor-based the end, first groove is a deep trench, and be arranged in the memory cell arrays district, its Lower Half has capacitor, capacitor top has first insulating barrier, the surface of first insulating barrier and the surface at the semiconductor-based end distance of being separated by, second groove is a shallow trench, in order to define the active region of memory cell arrays district and supporting area.Afterwards, shunk back to the corner that exposes the semiconductor-based end in the edge of first cover curtain layer, and the first sphering processing procedure is carried out in the corner of semiconductor substrate.Then, form lining insulating layer in first cover curtain layer, first insulating barrier and semiconductor-based basal surface, and form insulated plug on lining insulating layer, the surface of the suprabasil lining insulating layer of semiconductor of insulated plug and active region is copline roughly.Then, remove SI semi-insulation connector, part lining insulating layer and part first cover curtain layer in memory cell arrays district, to the corner at the semiconductor-based end that exposes the memory cell arrays district, again the second sphering processing procedure is carried out in the corner at the semiconductor-based end in memory cell arrays district.
The corner of the active region in memory cell arrays district is through twice sphering processing procedure, therefore, the radius of curvature of edge is bigger, utilizes gate insulation layer that oxidation process the generates thickness at edge, roughly the same with other zone, can improve transistorized quality whereby.
Description of drawings
Fig. 1 illustrates the traditional deep groove capacity and the section of structure of vertical transistor;
Fig. 2 A to Fig. 2 I is profile, the bilateral angle sphering processing procedure of a kind of part vertical memory cell of its expression one embodiment of the invention.
Symbol description:
Substrate: 10
Imbed band (drain): 12
Trench capacitor: 14
Vertical transistor: 16
Deep trench: 18
Gate: 20
Gate electrode: 22
Top silicon oxide layer: 24
Source electrode: 26
Gate pole oxidation layer: 28
Corner: 30
Memory cell arrays district: I
Support district: II
The semiconductor-based end: 100
Cover curtain layer: 102
Groove-shaped capacitor: 104
Deep trench: 112
Neck ring insulating barrier: 114
Top electrode: 116
Insulation layer of top end: 122
Cover curtain layer: 124
Photoresist design layer: 126
Groove: 130
Sacrificial oxide layer: 132
Lining insulating layer: 134
Insulated plug: 136
Photoresist design layer: 142
Corner: 150
Gate insulation layer: 152
Gate: 154
Clearance wall: 156
Source/drain: 158
Source electrode: S
Drain: D
Embodiment
At first please refer to Fig. 2 A, semiconductor substrate 100 is provided, its material for example is silicon or germanium.This semiconductor-based end 100, can roughly be divided into memory cell arrays district I and supporting area II.Then form a cover curtain layer 102 on surface, the semiconductor-based ends 100, constituted by the layered structure of pad oxide with the pad nitration case, wherein pad oxide is for example grown up in surface, the semiconductor-based ends 100 by thermal oxidation method, deposits one deck pad silicon nitride layer by chemical vapour deposition technique afterwards on pad oxide.
Then,, and be used cover curtain layer 102 and do protection, in the semiconductor-based end 100, to form deep trench 112 by micro image etching procedure.Afterwards, the Lower Half in deep trench 112 forms groove-shaped capacitor 104, and it comprises flush type bottom electrode (buried plate; BP), capacitance dielectric layer and top electrode 116.Wherein, the flush type bottom electrode is meant and is arranged in the groove 112 Lower Halves doped region at the semiconductor-based end 100 on every side.Capacitance dielectric layer is between the bottom electrode and the top electrode utmost point 116, and material for example is the layered structure of silica or silica-silicon-nitride and silicon oxide (ONO).Top electrode 116 for example is made of the polysilicon that mixes.
Afterwards, the sidewall of the first half of the capacitor 104 in groove 112 forms neck ring insulating barrier 114, for example is the neck ring oxide layer.Continuation forms insulation layer of top end 122 at the top of capacitor 104, for example is top silicon oxide layer (TTO; Trench top oxide), in order to top electrode 116 and the electrical isolation of its top with the vertical transistor structures of formation as capacitor.The formation method of top silicon oxide layer for example is by the formed oxide of tetraethyl-metasilicate (TEOS).
Then please refer to Fig. 2 B; the top of insulation layer of top end 122 forms a cover curtain layer 124 in groove 112; in order in follow-up etching process the protection its below insulation layer of top end 122 and capacitor 104, its material for example is an organic antireflection layer, for example silicon oxynitride (SiON).The surface of cover curtain layer 124 can be depressed in the groove 112, its formation method for example is the anti-reflecting layer that deposition one deck fills up whole groove 112, and cover the surface of whole cover curtain layer 102, then carry out the etch-back processing procedure, until the surface that exposes cover curtain layer 102, and make the surface of the surface of cover curtain layer 124 a little less than cover curtain layer 102.Afterwards, form a photoresist design layer 126 on cover curtain layer 102 and 124, this photoresist design layer 126 covers the assembly active region of memory cell arrays district I and supporting area II.
Then please refer to Fig. 2 C, serves as the cover curtain with this photoresist design layer 126 and cover curtain layer 124, carries out etch process, to form the groove 130 of isolating usefulness as assembly in the semiconductor-based end 100, so as to defining active region (AA).Wherein the bottom of groove 130 is lower than the surface of insulation layer of top end 122 at least.Afterwards, remove photoresist design layer 126 and cover curtain layer 124.
Then carry out primary corners processing procedure, below will cooperate Fig. 2 D to do explanation.
Please refer to Fig. 2 D, contract in the edge with the cover curtain layer 102 on the surface, the semiconductor-based ends 100 of active region AA, with the corner 150 at the semiconductor-based end 100 that exposes active region AA.Make the method that contracts in the edge of cover curtain layer 102 can be the isotropic etching method, for example use hydrofluoric acid/ethylene glycol (hydrogen fluoride/ethylene glycol; HF/EG).
Afterwards, carry out synchronous steam (in-situ steam generation; ISSG) oxidation process, with in the surface, the semiconductor-based ends 100 that exposes, comprise 150 places, corner, form one deck sacrificial oxide layer 132, afterwards sacrificial oxide layer 132 is removed, so as to reaching purpose corner 150 corners at the semiconductor-based end 100 of active region AA.
Then carry out the processing procedure of the assembly isolation structure of supporting area II, below will cooperate Fig. 2 E to do explanation.
Then please refer to Fig. 2 E, form the lining insulating layer 134 of one deck compliance on the whole semiconductor-based end 100, its material for example is a silicon nitride.Afterwards, in groove 130, form insulated plug 136, its formation method for example is to utilize high density plasma enhanced chemical vapor deposition method (HDP-CVD) deposition one deck silica, and utilizes the worn unnecessary silica of chemical mechanical milling method (CMP), till the lining insulating layer 134 that exposes active region AA.
Then carry out the corners processing procedure second time of memory cell arrays district I, below will cooperate Fig. 2 F to Fig. 2 H to do explanation.
Then please refer to Fig. 2 F, form one deck photoresist design layer 142 in lining insulating layer 134 and insulated plug 136 surfaces, it exposes memory cell arrays district I.
Then please refer to Fig. 2 G, remove part lining insulating layer 134, cover curtain layer 102 and the insulated plug 136 of memory cell arrays district I, to the corner 150 at the semiconductor-based end 100 that exposes active region AA.Its method for example is the isotropic etching method, for example uses the wet etching processing procedure of hydrofluoric acid/ethylene glycol (HF/EG).
Afterwards, sphering is carried out in the corner 150 that will expose, and its sphering method for example is to use oxidant, for example hydrogenperoxide steam generator (H
2O
2 (aq)) or salpeter solution (HNO
3 (aq)), to generate oxide, utilize hydrofluoric acid solution (HF again in 150 places, corner that expose
(aq)) remove the oxide of generation, to reach purpose with corner 150 spherings.
Then carry out follow-up transistor processing procedure.
At first, under the protection of photoresist design layer 142, remove the insulated plug 136 of memory cell arrays district I, again photoresist design layer 142 is removed, shown in Fig. 2 H.Afterwards, remove the lining insulating layer 134 and the cover curtain layer 102 that expose, to expose the surface, the semiconductor-based ends 100 of active region AA.Then, form gate insulation layer 152 in surface, the semiconductor-based ends 100, its material for example is to utilize oxidation process in the formed silica of silicon base, and on gate insulation layer 152, form gate 154, and in gate 154 both sides formation clearance wall 156, be beneficial to supporting area II and form source/drain 158, perhaps, can be beneficial to memory cell arrays district I and form the follow-up contact hole connector that can aim at source S automatically with shallow doping drain structure.The drain D of memory cell arrays district I promptly forms in previous processing procedure in graphic, but only indicates in Fig. 2 I, and so this non-pass the present invention seldom does explanation at this.
In sum, the present invention has following advantages at least:
1. the present invention is in finishing slot type capacitor, and forms the ditch of isolated area in semiconductor base Behind the groove, the sphering processing procedure first time is carried out in the corner of active region. And form shallow trench isolation in supporting area After structure, again the sphering processing procedure second time is carried out in the corner of the active region in memory cell arrays district.
2. the corner of the active region in memory cell arrays of the present invention district is to go through twice sphering system Therefore journey can obtain the bigger corner of radius of curvature, to obtain oxidation rate and surface roughly Identical gate insulation layer.
Claims (23)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03156537.9A CN1285120C (en) | 2003-09-03 | 2003-09-03 | Bilateral Corner Rounding Process for Partially Vertical Memory Cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03156537.9A CN1285120C (en) | 2003-09-03 | 2003-09-03 | Bilateral Corner Rounding Process for Partially Vertical Memory Cells |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591834A CN1591834A (en) | 2005-03-09 |
| CN1285120C true CN1285120C (en) | 2006-11-15 |
Family
ID=34598464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03156537.9A Expired - Lifetime CN1285120C (en) | 2003-09-03 | 2003-09-03 | Bilateral Corner Rounding Process for Partially Vertical Memory Cells |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1285120C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521176B (en) * | 2005-09-20 | 2012-11-14 | 联华电子股份有限公司 | Method for manufacturing groove capacitor structure |
| CN101452872B (en) * | 2007-11-30 | 2011-06-01 | 上海华虹Nec电子有限公司 | High-voltage region shallow trench top angle rounding method |
| CN102569202B (en) * | 2010-12-16 | 2014-07-30 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of static random access memory |
| CN107403726B (en) * | 2016-05-20 | 2019-12-27 | 中芯国际集成电路制造（天津）有限公司 | Method for manufacturing semiconductor device |
-
2003
- 2003-09-03 CN CN03156537.9A patent/CN1285120C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1591834A (en) | 2005-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1248065A (en) | Vertical device and method for semiconductor chip | |
| CN1222999C (en) | Channel condenser with epitaxial buried layer | |
| CN1967798A (en) | Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods | |
| CN1252624A (en) | Pot channel type capacitor with epitaxial hidden layer | |
| CN1258933A (en) | Semiconductor integrated circuit and its producing method | |
| CN102339797B (en) | Manufacturing method of capacitor lower electrode of dynamic random access memory | |
| CN101064282A (en) | Trench capacitor dynamic random access memory element and manufacturing method thereof | |
| CN1577823A (en) | Semiconductor device and method of manufacturing the same | |
| CN102315161B (en) | Method for fabricating semiconductor device with side junction | |
| US6319787B1 (en) | Method for forming a high surface area trench capacitor | |
| CN1118874C (en) | Semiconductor device and manufacture thereof | |
| CN1285120C (en) | Bilateral Corner Rounding Process for Partially Vertical Memory Cells | |
| US7009236B2 (en) | Memory device with vertical transistors and deep trench capacitors and method of fabricating the same | |
| US6929998B2 (en) | Method for forming bottle-shaped trench | |
| CN1309050C (en) | Method of manufacturing memory cell with single-sided buried strap | |
| US20090191686A1 (en) | Method for Preparing Doped Polysilicon Conductor and Method for Preparing Trench Capacitor Structure Using the Same | |
| US7638391B2 (en) | Semiconductor memory device and fabrication method thereof | |
| US6929996B2 (en) | Corner rounding process for partial vertical transistor | |
| US20040214391A1 (en) | Method for fabricating bottle-shaped trench capacitor | |
| CN110416218B (en) | Method for manufacturing memory element | |
| CN1264211C (en) | Trench capacitor and method of forming the same | |
| CN1127135C (en) | Method of fabricating horizontal trench capacitor and dynamic random access memory cell array | |
| CN1298048C (en) | Ways to avoid top dimension enlargement of deep trenches | |
| CN1301552C (en) | Method for controlling top size of deep trench | |
| CN1292570A (en) | Integrated circuit with at least a condenser and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20061115 |