CN101521176B - Method for manufacturing groove capacitor structure - Google Patents
Method for manufacturing groove capacitor structure Download PDFInfo
- Publication number
- CN101521176B CN101521176B CN2009100058336A CN200910005833A CN101521176B CN 101521176 B CN101521176 B CN 101521176B CN 2009100058336 A CN2009100058336 A CN 2009100058336A CN 200910005833 A CN200910005833 A CN 200910005833A CN 101521176 B CN101521176 B CN 101521176B
- Authority
- CN
- China
- Prior art keywords
- substrate
- isolating trough
- layer
- screen
- shallow isolating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for manufacturing a groove capacitor structure, which comprises the following steps: providing a substrate of which the surface is defined with a storage array area and a logic area; performing a process of shallow trench isolation to form at least one shallow trench isolation on the substrate in the storage array area and the logic area; forming a patterning shielding layer on the substrate and the surface of the shallow trench isolation; exposing part of the shallow trench isolation and the substrate on the periphery of the shallow trench isolation in the storage array area; and etching the substrate not covered by the shielding layer in the storage array area so as to form a plurality of deep grooves in the substrate.
Description
Present specification is that the name submitted on September 20th, 2005 is called the dividing an application of No. 200510109790.8 application for a patent for invention of " groove capacitor structure and preparation method thereof ".
Technical field
The present invention relates to a kind of manufacture method of groove capacitor structure, particularly relate to a kind of method, and can increase effective capacitance area with making channel capacitor of shallow isolating trough and logic process compatibility.
Background technology
Along with various electronic products towards the miniaturization Development Trend; The DRAM circuit elements design also must meet high integration, highdensity requirement; And channel capacitor DRAM component structure be industry one of the high density DRAM framework that extensively adopts; It etches deep trench and in it, processes channel capacitor in semiconductor substrate, thereby can effectively dwindle the size of memory cell, properly utilizes chip space.
See also Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 is existing generalized section of making the channel capacitor shallow isolating trough.As shown in Figure 1, semiconductor chip 10 is divided into logic region (logic area) 16 and storage array zone (memory array area) 14.A plurality of deep groove capacity structures 18 have been manufactured with in the storage array of semiconductor chip 10 zone 14 among Fig. 1.Generally; The making of deep groove capacity structure 18 etches deep trench opening (figure does not show) through hard shielding (hard mask) 20 earlier in silicon base 12, in opening, form electric capacity top electrode (figure does not show), capacitance dielectric layer 22 and capacitor lower electrode (storage node) 24 then.
Then; As shown in Figure 2; Deposition one bottom anti-reflection layer (BARC) 26 on screen 20; Coating one photoresist layer on bottom anti-reflection layer 26 then with existing gold-tinted technology optical patterning in addition, and toast the back and forms definition and have the shallow isolating trough pattern openings 30 of storage array zone (memory array area) 14 and photoresist that definition has logic region 16 shallow isolating trough pattern openings 32 to shield 28 subsequently and with the photoresist layer.
As shown in Figure 3; Carry out a plasma dry etching process then; Utilize photoresist shielding 28 as etch shield; Via shallow isolating trough pattern openings 30 downward etching bottom anti-reflection layer 26, shield 20 firmly, silicon base 12, a part of capacitor lower electrode 24 and a part of capacitance dielectric layer 22, form insulating channel 34.Simultaneously, via shallow isolating trough pattern openings 30 downward etching bottom anti-reflection layer 26, shield 20 and silicon base 12 firmly,, remove photoresist shielding 28 and bottom anti-reflection layer 26 subsequently in logic region 12, to form insulating channel 36.
At last, as shown in Figure 4, in insulating channel 34 and insulating channel 36, insert trench dielectric material 38, and in addition planarization, promptly accomplish the making of existing channel capacitor shallow isolating trough.
Yet the manufacture method of above-mentioned existing channel capacitor shallow isolating trough still has many shortcomings, because deep groove capacity structure 18 is comparatively complicated, therefore when carrying out the STI etching, the composition of etching plasma is also comparatively complicated and wayward.This is because form insulating channel 34; Need to shield via shallow isolating trough pattern openings 30 downward etching bottom anti-reflection layer 26, firmly 20, silicon base 12, a part of capacitor lower electrode 24 and the capacitance dielectric layer 22 of some; Moreover cause relatively poor critical dimension (critical dimension, CD) the CD deviation between the uniformity and dredging/close (iso/dense) pattern.Therefore, the manufacture method of existing channel capacitor shallow isolating trough when carrying out the STI etching and the compatibility of logic process lower.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of channel capacitor and its manufacture method, with the compatibility and the increase effective capacitance area of logic process, and solves the problem of above-mentioned existing skill in the time of can improving the STI etching.
According to claim of the present invention, disclose a kind of method of making channel capacitor.Said method comprises the following steps:
One substrate is provided, and the definition of the surface of this substrate there are a storage array zone and a logic region;
Carry out a shallow groove isolation, respectively at forming at least one shallow isolating trough in this substrate in this storage array zone and this logic region;
Form the screen of a patterning in the surface of this substrate and this shallow isolating trough, and this screen exposes this shallow isolating trough of part and this peripheral substrate of this shallow isolating trough in this storage array zone; And
This substrate and this shallow isolating trough of part of not covered by this screen in this storage array zone of etching are to form a plurality of deep trench in this substrate.
According to claim of the present invention, also disclose a kind of method of making channel capacitor.Said method comprises the following steps:
One substrate is provided, and the definition of the surface of this substrate there are a storage array zone and a logic region;
Deposit an oxide layer and a silicon nitride layer in regular turn in this substrate;
Carry out a shallow groove isolation, respectively at forming at least one shallow isolating trough in this oxide layer in this storage array zone and this logic region, this silicon nitride layer and this substrate of part;
Form the screen of a patterning in the surface of this silicon nitride layer and this shallow isolating trough, and the screen of this patterning exposes this silicon nitride layer and the periphery of this shallow isolating trough in this storage array zone; And
This silicon nitride layer that is not covered by this screen in this storage array zone of etching and the periphery of this shallow isolating trough; In this substrate, to form a plurality of deep trench; And respectively this deep trench and this shallow isolating trough contact portion have the inwall of a vertical configuration, and it does not then have a circular-arc inwall with this shallow isolating trough contact portion.
According to claim of the present invention, also disclose a kind of channel capacitor, it comprises:
One substrate;
One shallow isolating trough is arranged in this substrate;
A plurality of deep trench; Be positioned at this shallow isolating trough around; And respectively this deep trench and this shallow isolating trough contact portion have the inwall of a vertical configuration, and it does not then have a circular-arc inwall with this shallow isolating trough contact portion, and wherein the inwall of this figure arcuation can increase effective capacitance area; And
A plurality of capacitance structures lay respectively at respectively within this deep trench.
Because the method for making channel capacitor of the present invention; For making shallow isolating trough earlier; Therefore make channel capacitor again, when not only having got rid of prior art and carrying out the shallow isolating trough etching, cause the critical dimension uniformity after the etching because of groove capacitor structure is complicated and dredging/critical dimension variations between close pattern; Simultaneously also can further promote groove capacitor structure and logic process compatibility and effective capacitance area, reduce cost of manufacture to increase productive rate and quality.
In order further to understand characteristic of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Fig. 4 is existing generalized section of making the channel capacitor shallow isolating trough.
Fig. 5 to Fig. 8 makes the method sketch map of channel capacitor for the preferred embodiment of the present invention.
Fig. 9 is the effective capacitance area sketch map of the present invention and prior art.
The simple symbol explanation
12 substrates of 10 semiconductor chips
14 storage arrays zone, 16 logic regions
18 deep groove capacity structures 20 shield firmly
22 capacitance dielectric layers, 24 capacitor lower electrodes
The shielding of 26 bottom anti-reflection layer, 28 photoresists
30 openings, 32 openings
34 insulating channels, 36 insulating channels
38 insulating material, 50 semiconductor chips
52 substrates, 54 logic regions
56 storage arrays zone, 58 oxide layers
60 silicon nitride layers, 62 shallow isolating trough
64 shallow isolating trough, 66 insulating material
68 hard screen 69 bottom reflectors
70 photoresist layers, 72 opening
74 groove capacitor structures, 76 capacitor lower electrodes
77 capacitance dielectric layers, 78 electric capacity top electrodes
A effective capacitance area b effective capacitance area
Embodiment
In order further to understand characteristic of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Please refer to Fig. 5 to Fig. 8, Fig. 5 to Fig. 8 makes the method sketch map of channel capacitor for the present invention.As shown in Figure 5, the present invention provides semiconductor chip 50, defines a logic region 54 and storage array zone 56, and makes a plurality of shallow isolating trough 64 respectively at making in a plurality of shallow isolating trough 62 and the logic region 54 in the storage array zone 56.Wherein, Being made as earlier of shallow isolating trough 62,64 in substrate 52; For example etch a plurality of shallow isolating trough 62,64 through screen (figure does not show) in silicon base, oxide layer 58 and the silicon nitride layer 60; In shallow isolating trough 62,64, insert insulating material 66 then, silica for example, and planarization forms in addition.
Then, as shown in Figure 6, the screen of formation one patterning, for example a photoresist layer 70 on silicon nitride layer 60 and shallow isolating trough 62,64.In addition; The present invention also is formed with a hard screen 68 between photoresist layer 70 and silicon nitride layer 60; And selectivity is used a bottom anti-reflection layer 69 and/or other material layer; Forming the shielding material layer of a plyability, and comprise hard screen 68 and bottom anti-reflection layer 69 at the equal patterning of the shielding material layer of interior plyability, to define a plurality of deep trench position in silicon nitride layer 60 and shallow isolating trough 62 surfaces.Wherein, the material of hard screen 68 can be dielectric material, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, boron-phosphorosilicate glass, Si oxide or carbide.What be worth explanation in addition is, in order to the shielding of definition deep trench and be limited to the above-mentioned practice, and can do suitably change according to effect.
Subsequently, as shown in Figure 7, carry out an etch process, storage array zone 56 interior shallow isolating trough 62 and silicon nitride layer 60, oxide layer 58 and substrate 52 erosions that do not covered by photoresist layer 70 are removed, to form deep trench opening 72.Wherein, residual not etched shallow isolating trough 62 is between two adjacent deep trench openings 72, and the side of not etched shallow isolating trough 62 is close to the vertical side edge of two adjacent deep trench openings 72.What be worth explanation is; Because deep trench opening 72 is just made after shallow isolating trough 62 forms; Therefore when carrying out etch process because the etching selectivity of shallow isolating trough 62, substrate 52 and silicon nitride layer 60 difference to some extent; Therefore each deep trench opening 72 and shallow isolating trough 62 contact portions have the inwall of vertical configuration, and it does not then have circular-arc inwall with the shallow isolating trough contact portion, and the inwall of scheming arcuation by this can increase effective capacitance area.Subsequently, remove photoresist layer 70, bottom anti-reflection layer 69 and hard screen 68.
At last, as shown in Figure 8, in deep trench opening 72, make groove capacitor structure 74.At first; Utilize doping processs such as arsenic silex glass (ASG) diffusion technique, ion injection or angled ion injection; Inwall in deep trench opening 72 and the substrate of bottom 52 form diffusion zone, and as capacitor lower electrode 76, then capacitance dielectric layer 77 is formed on inwall in deep trench opening 72 and bottom; Be to insert in the deep trench opening 72 electric conducting material (figure does not show) at last; Polysilicon for example, and utilize a chemical mechanical milling tech, utilize silicon nitride layer 60 to stop layer and electric conducting material is planarized to silicon nitride layer 60 surfaces to form electric capacity top electrode 78 as grinding.Wherein, in present embodiment, the capacitance dielectric layer 77 of deep groove capacity structure 74 is three layers of composite dielectric layer of oxide/nitride/oxide, but the homogenous material of other Chang Zuowei capacitance dielectric layer or composite material also can be selected for use.
In addition, please refer to Fig. 9, it is the effective capacitance area sketch map of the present invention and prior art.As shown in Figure 9; Because behind the storage array zone 56 and logic region 54 making shallow isolating trough 62,64 of the present invention prior to substrate 52; In the storage array zone, 56 make groove capacitor structures 74 again; Therefore shallow isolating trough 62 can't cover groove capacitor structure 74, has promoted effective capacitance area a of the present invention; Otherwise effective capacitance area b of the prior art because after making groove capacitor structure 18 earlier, make shallow isolating trough 34 again, causes the subregional groove capacitor structure 18 of shallow isolating trough 34 covering part on the contrary, and reduces effective capacitance area b.
Comprehensively above-mentioned, the present invention makes the method for channel capacitor, after making shallow isolating trough prior to the storage array zone of substrate and logic region, carries out the making of groove capacitor structure again, compared to prior art following advantage is arranged:
(1) the present invention makes the method for channel capacitor; Owing to after having made shallow isolating trough earlier, carry out the subsequent technique in storage array zone again, so the shallow isolating trough of logic region; Not influenced by storage array zone subsequent technique, preferred profile arranged to keep the shallow isolating trough in the logic region.
(2) the present invention makes the method for channel capacitor, can avoid described in the prior art, when carrying out the shallow groove isolation of storage array zone and logic region between at the same time; Because of different material layer has different etching ratios; For example therefore macromolecule layer/oxide layer/silicon nitride layer needs different etch to different material layer, causes relatively poor critical dimension uniformity and the critical dimension variations between thin/close pattern on the contrary; Further influence electrically; Reduce the compatibility of groove capacitor structure and logic process, so the present invention solves existing issue, and increase productive rate and quality reduce cost of manufacture.
(3) the present invention makes the method for channel capacitor, because carry out shallow groove isolation earlier, makes groove capacitor structure again, so shallow isolating trough can't cover the groove capacitor structure of part, has therefore promoted about 5%～15% effective capacitance area.
The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (13)
1. method of making channel capacitor, this method comprises:
One substrate is provided, and the definition of the surface of this substrate there are a storage array zone and a logic region;
Carry out a shallow groove isolation,, in said groove, insert insulating material then to form at least one shallow isolating trough respectively at etching at least one groove in this substrate in this storage array zone and this logic region;
Form the screen of a patterning in the surface of this substrate and this shallow isolating trough, and this screen exposes this shallow isolating trough of part and this peripheral substrate of this shallow isolating trough in this storage array zone;
This substrate and this shallow isolating trough of part of not covered by this screen in this storage array zone of etching are to form a plurality of deep trench in this substrate; And
Form an electric capacity top electrode in this deep trench, wherein a top of a top of this electric capacity top electrode and this shallow isolating trough trims.
2. the method for making channel capacitor as claimed in claim 1 also is included in before this shallow isolating trough of formation, prior to the surface formation oxide layer and the silicon nitride layer of this substrate.
3. the method for making channel capacitor as claimed in claim 1, wherein this screen comprises a photoresist layer.
4. the method for making channel capacitor as claimed in claim 1, wherein this screen comprises that a hard screen, a bottom anti-reflection layer are located on this hard screen and a photoresist layer is located on this bottom anti-reflection layer.
5. the method for making channel capacitor as claimed in claim 4, wherein this hard screen is selected from least a in the following material: silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, boron-phosphorosilicate glass, silicon carbide.
6. the method for making channel capacitor as claimed in claim 1 also is included in and forms after this deep trench and before forming this electric capacity top electrode, in this deep trench respectively, forms the step of a capacitor lower electrode and a capacitance dielectric layer.
7. the method for making channel capacitor as claimed in claim 6, wherein this capacitance dielectric layer comprises three layers of composite dielectric layer of monoxide/nitride/oxide.
8. method of making channel capacitor, this method comprises:
One substrate is provided, and the definition of the surface of this substrate there are a storage array zone and a logic region;
Deposit an oxide layer and a silicon nitride layer in regular turn in this substrate;
Carry out a shallow groove isolation, respectively at forming at least one shallow isolating trough in this oxide layer in this storage array zone and this logic region, this silicon nitride layer and this substrate of part;
Form the screen of a patterning in the surface of this silicon nitride layer and this shallow isolating trough, and the screen of this patterning exposes this silicon nitride layer of part and this shallow isolating trough of part in this storage array zone;
This silicon nitride layer and this shallow isolating trough that are not covered in this storage array zone of etching by this screen, in this substrate, forming a plurality of deep trench, and respectively this deep trench and this shallow isolating trough contact portion have the inwall of a vertical configuration; And
Form an electric capacity top electrode in this deep trench, wherein a top of a top of this electric capacity top electrode and this shallow isolating trough trims.
9. the method for making channel capacitor as claimed in claim 8, wherein this screen comprises a photoresist layer.
10. the method for making channel capacitor as claimed in claim 8, wherein this screen comprises that a hard screen, a bottom anti-reflection layer are located on this hard screen and a photoresist layer is located on this bottom anti-reflection layer.
11. the method for making channel capacitor as claimed in claim 10, wherein this hard screen is selected from least a in the following material: silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, boron-phosphorosilicate glass, silicon carbide.
12. the method for making channel capacitor as claimed in claim 8 also is included in and forms after this deep trench and before forming this electric capacity top electrode, in this deep trench respectively, forms the step of a capacitor lower electrode and a capacitance dielectric layer.
13. the method for making channel capacitor as claimed in claim 12, wherein the capacitance dielectric layer of this deep groove capacity structure is three layers of composite dielectric layer of oxide/nitride/oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100058336A CN101521176B (en) | 2005-09-20 | 2005-09-20 | Method for manufacturing groove capacitor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100058336A CN101521176B (en) | 2005-09-20 | 2005-09-20 | Method for manufacturing groove capacitor structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510109790 Division CN1937204A (en) | 2005-09-20 | 2005-09-20 | Trough capacitance structure and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101521176A CN101521176A (en) | 2009-09-02 |
| CN101521176B true CN101521176B (en) | 2012-11-14 |
Family
ID=41081682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100058336A Active CN101521176B (en) | 2005-09-20 | 2005-09-20 | Method for manufacturing groove capacitor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101521176B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6660592B2 (en) * | 2001-11-21 | 2003-12-09 | Mosel Vitelic, Inc. | Fabricating a DMOS transistor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Process for making double corners round of partial vertical storage unit |
-
2005
- 2005-09-20 CN CN2009100058336A patent/CN101521176B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6660592B2 (en) * | 2001-11-21 | 2003-12-09 | Mosel Vitelic, Inc. | Fabricating a DMOS transistor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Process for making double corners round of partial vertical storage unit |
Non-Patent Citations (1)
| Title |
|---|
| JP平870108A 1996.03.12 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101521176A (en) | 2009-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110168724B (en) | Trench structure for three-dimensional memory device | |
| US7344954B2 (en) | Method of manufacturing a capacitor deep trench and of etching a deep trench opening | |
| US7494890B2 (en) | Trench capacitor and method for manufacturing the same | |
| CN1298043C (en) | Semiconducotor device and method for isolating the same | |
| US8242583B2 (en) | Semiconductor device having CMP dummy pattern | |
| US20060081913A1 (en) | Semiconductor memory devices including electrode contact structures having reduced contact resistance and methods of fabricating the same | |
| US8097508B2 (en) | Method and structure for performing a chemical mechanical polishing process | |
| JP2008283168A (en) | Method of forming minute pattern of semiconductor element | |
| KR100570114B1 (en) | Self aligned buried plate | |
| US20080213967A1 (en) | Trench capacitor and method for manufacturing the same | |
| CN101521176B (en) | Method for manufacturing groove capacitor structure | |
| CN1937204A (en) | Trough capacitance structure and its manufacturing method | |
| CN100468702C (en) | Method for manufacturing deep channel capacitor and etching deep channel opening | |
| US7534711B2 (en) | System and method for direct etching | |
| CN111180386B (en) | Semiconductor device mesoporous structure and forming method thereof | |
| CN100590785C (en) | Channel capacitor and memory unit manufacturing method | |
| US6890815B2 (en) | Reduced cap layer erosion for borderless contacts | |
| CN113066795B (en) | Semiconductor device and preparation method thereof | |
| CN1287445C (en) | Method for fabricating shallow trench isolation for channel capacitor | |
| CN116685142A (en) | Method for manufacturing semiconductor element | |
| KR100519375B1 (en) | Capacitor in semiconductor device and method for making the same | |
| CN115084218A (en) | Semiconductor device having STI region | |
| TW201333999A (en) | Manufacturing method of memory capacitor without moat structure | |
| KR20050045175A (en) | Method for forming dummy active pattern | |
| KR20040060218A (en) | Method for fabricating of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |