KR20050045175A - Method for forming dummy active pattern - Google Patents
Method for forming dummy active pattern Download PDFInfo
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- KR20050045175A KR20050045175A KR1020030079141A KR20030079141A KR20050045175A KR 20050045175 A KR20050045175 A KR 20050045175A KR 1020030079141 A KR1020030079141 A KR 1020030079141A KR 20030079141 A KR20030079141 A KR 20030079141A KR 20050045175 A KR20050045175 A KR 20050045175A
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- 238000000034 method Methods 0.000 title abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 더미 액티브패턴의 삽입 방법에 관해 개시한 것으로서, 액티브영역과 필드영역이 정의된 반도체 칩을 제공하는 단계와, 반도체 칩의 액티브영역 내에 메인칩과 테스트 패턴을 배치시키는 단계와, 반도체 칩의 필드영역에 상기 메인칩의 밀도 및 사이즈가 동일한 더미 액티브패턴을 삽입하는 단계를 포함한다.The present invention relates to a method of inserting a dummy active pattern, comprising: providing a semiconductor chip in which an active region and a field region are defined, disposing a main chip and a test pattern in an active region of the semiconductor chip, and And inserting a dummy active pattern having the same density and size of the main chip into a field region of.
따라서, 본 발명은 반도체 칩 내의 필드영역에 삽입될 더미 액티브패턴을 메인칩과 동일한 밀도, 사이즈 및 스페이스와 동일하게 함으로써, 기존의 더미 액티브패턴과 메인 칩간의 폭, 스페이스 차이와 패턴 밀도에 따른 차이를 없앨 수 있다. 이로써, 본 발명은 STI 에서 갭필옥사이드막의 씨엠피 공정 이후 균일도가 향상될 뿐만 아니라, 기존의 더미 액티브 어레이 선택 시 가져올 수 있는 변수를 제거할 수 있는 이점이 있다.Therefore, according to the present invention, the dummy active pattern to be inserted into the field region in the semiconductor chip is the same density, size, and space as the main chip, and thus the difference according to the width, space difference and pattern density between the existing dummy active pattern and the main chip. Can be eliminated. As a result, the present invention not only improves the uniformity after the CMP process of the gap fill oxide layer in the STI, but also has the advantage of eliminating a variable that can be brought about when selecting a conventional dummy active array.
Description
본 발명은 반도체 소자를 제조하는 기법에 관한 것으로, 더욱 상세하게는 반도체 공정 중 STI CMP(Shallow Trench Isolation Chemical Mechnical Polishing) 공정을 위해 액티브영역에 더미 액티브패턴을 삽입하는 방법에 관한 것이다.The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to a method of inserting a dummy active pattern in an active region for a shallow trench isolation chemical mechanical polishing (SMP CMP) process during a semiconductor process.
종래의 기술에서는 메인칩(main chip) 및 테스트 패턴을 각각 배치시킨 다음, 필드영역에 더미 액티브패턴을 삽입하는 방법을 이용하였다. 상기 메인칩은 에스램(SRAM) 칩과 같이 수율을 확인하는 칩을 뜻한다.In the related art, a method of disposing a main chip and a test pattern, and then inserting a dummy active pattern into a field area is used. The main chip refers to a chip that checks the yield, such as an SRAM chip.
그러나, 0.25㎛ 이하의 STI(Shallow Trench Isolation)에서, 갭필(gap fill)에 사용되는 HDP-CVD(High Density Plasma-Chemical Vapor Deposition)의 경우에는 더미 액티브패턴의 밀도 차이 뿐만 아니라 더미 액티브패턴의 폭(width)과 스페이스(space)에 의해서도 두께, 밀도 및 프로파일 등이 변화된다. 따라서, 실제 메인 칩 내에 여러 종류의 패턴을 기존 한가지의 더미 액티브패턴으로 하였을 경우 CMP(Chemical Mechnical Polishing)에서 사용되는 효과적인 패턴의 밀도는 실제 메인 칩과 더미 액티브패턴이 주로 들어가는 필드영역 또는 테스트패턴 사이에서 차이가 발생되는 문제점이 있었다.However, in shallow trench isolation (STI) of 0.25 μm or less, in the case of high density plasma-chemical vapor deposition (HDP-CVD) used for gap fill, not only the difference in density of the dummy active pattern but also the width of the dummy active pattern The thickness, density, and profile also vary with width and space. Therefore, when several kinds of patterns are used as one dummy active pattern in the actual main chip, the effective pattern density used in CMP (Chemical Mechnical Polishing) is determined between the field area or the test pattern where the actual main chip and the dummy active pattern mainly enter. There was a problem that the difference occurs.
그러나, 0.25㎛ 이하의 STI(Shallow Trench Isolation)에서, HDP-CVD(High Density Plasma-Chemical Vapor Deposition)방식으로 갭필옥사이드막을 형성하고 나서, 상기 갭필옥사이드막을 씨엠피(Chemical Mechnical Polishing)하는 경우, 더미 액티브패턴의 밀도 차이 뿐만 아니라 더미 액티브패턴의 폭(width)과 스페이스(space)에 의해서도 두께, 밀도 및 프로파일 등이 변화된다. 따라서, 실제 메인 칩 내에 여러 종류의 패턴을 기존 한가지의 더미 액티브패턴으로 하였을 경우 CMP(Chemical Mechnical Polishing)에서 사용되는 효과적인 패턴의 밀도는 실제 메인 칩과 더미 액티브패턴이 주로 들어가는 필드영역 또는 테스트패턴 사이에서 차이가 발생된다.However, when a gap fill oxide film is formed by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method at a shallow trench isolation (STI) of 0.25 μm or less, the gap fill oxide film is subjected to chemical mechanical polishing (CMP). In addition to the difference in density of the active pattern, the thickness, density, profile, and the like are changed by the width and space of the dummy active pattern. Therefore, when several kinds of patterns are used as one dummy active pattern in the actual main chip, the effective pattern density used in CMP (Chemical Mechnical Polishing) is determined between the field area or the test pattern where the actual main chip and the dummy active pattern mainly enter. The difference occurs at.
일반적으로 메인-칩의 경우에는 폭(width)이 디자인룰(design rule)대로 그려져 있어 작은 패턴들의 모임이고, 테스트패턴 등은 좁은 패턴과 넓은 패턴으로 산재해 있다. 그런데, HDP-CVD막의 경우 증착프로파일은 패턴밀도 뿐만 아니라 패턴 사이즈 즉, 폭 및 스페이스에도 영향을 받는 문제점이 있다.In general, in the case of the main chip, the width is drawn according to the design rule, which is a collection of small patterns, and the test patterns are scattered in a narrow pattern and a wide pattern. However, in the case of the HDP-CVD film, the deposition profile has a problem that not only the pattern density but also the pattern size, that is, the width and the space.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 필드영역에 메인챕의 밀도와 사이즈가 같은 더미 액티브패턴을 삽입함으로써, 기존의 더미패턴과 메인 칩 간의 액티브영역의 폭, 스페이스 차이와 패턴밀도에 따른 차이를 없애 STI CMP후의 균일도를 향상시킬 수 있는 더미 액티브패턴의 삽입 방법을 제공하려는 것이다.Accordingly, to solve the above problem, an object of the present invention is to insert a dummy active pattern having the same density and size of a main chapter into a field region, thereby reducing the width, space difference and pattern density of the active region between the existing dummy pattern and the main chip. The purpose of the present invention is to provide a method of inserting a dummy active pattern that can improve the uniformity after STI CMP by eliminating the difference.
상기 목적을 달성하고자, 본 발명의 더미 액티브패턴의 삽입 방법은 액티브영역과 필드영역이 정의된 반도체 칩을 제공하는 단계와, 반도체 칩의 액티브영역 내에 메인칩과 테스트 패턴을 배치시키는 단계와, 반도체 칩의 필드영역에 상기 메인칩의 밀도 및 사이즈가 동일한 더미 액티브패턴을 삽입하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method of inserting a dummy active pattern of the present invention comprises the steps of providing a semiconductor chip having an active region and a field region defined, disposing a main chip and a test pattern in the active region of the semiconductor chip, And inserting a dummy active pattern having the same density and size of the main chip into the field region of the chip.
(실시예)(Example)
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 더미 액티브패턴의 삽입방법을 설명하면 다음과 같다.Hereinafter, a method of inserting a dummy active pattern according to the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 3은 본 발명에 따른 더미 액티브패턴 삽입방법을 설명하기 위한 멀티칩(multi chip) 배치도이다.1 to 3 are diagrams illustrating a multi chip arrangement for explaining a method of inserting a dummy active pattern according to the present invention.
도 1은 메인 칩의 반복되는 최소크기의 칩으로 반도체 칩에 배치하는 단계를 보인 멀티칩 배치도이고, 도 2는 테스트 패턴을 배치하는 단계를 보인 멀티칩 배치도이다.FIG. 1 is a multichip layout view showing a step of arranging a semiconductor chip as a repeating minimum size chip of a main chip, and FIG. 2 is a multichip layout view showing a step of arranging a test pattern.
또한, 도 3은 더미 액티브패턴을 삽입하는 단계를 보인 멀티칩 배치도이다.3 is a multi-chip layout view showing a step of inserting a dummy active pattern.
본 발명에 따른 더미 액티브패턴의 삽입방법은, 도 1에 도시된 바와 같이, 먼저 액티브영역과 필드영역이 정의된 반도체 칩을 제공한다. 이어, 상기 반도체칩에 메인 칩의 반복되는 최소크기의 칩으로 배치한다. According to the present invention, a method of inserting a dummy active pattern, as shown in FIG. 1, first provides a semiconductor chip in which an active region and a field region are defined. Subsequently, the semiconductor chip is arranged as a repeating minimum size chip of the main chip.
그런 다음, 도 2에 도시된 바와 같이, 테스트패턴을 순차적으로 배치한다.Then, as shown in Figure 2, the test pattern is arranged sequentially.
이후, 도 3에 도시된 바와 같이, 반도체 칩의 필드영역(b)에 메인칩과 같은 패턴 밀도(density), 사이즈(size) 및 스페이스(space)가 동일한 더미 액티브패턴(a)을 삽입한다.3, a dummy active pattern a having the same pattern density, size, and space as the main chip is inserted into the field region b of the semiconductor chip.
본 발명에서는 필드영역에 메인 칩과 동일한 패턴 밀도, 사이즈 및 스페이서를 갖는 더미 액티브패턴을 형성함으로써, 이후의 STI CMP 공정 이 후에 균일성 향상을 가져오며, 기존의 더미 액티브패턴 어레이 선택 시 가져올 수 있는 변수를 제거할 수 있다.In the present invention, by forming a dummy active pattern having the same pattern density, size, and spacer as the main chip in the field region, the uniformity is improved after the subsequent STI CMP process, and can be obtained when the existing dummy active pattern array is selected. You can remove the variable.
즉, 0.25㎛ 이하의 STI에서, HDP-CVD방식으로 갭필옥사이드막을 형성하고 나서, 상기 갭필옥사이드막을 씨엠피하는 경우, 액티브패턴이 더미 메인 칩과 동일하게 패터닝됨에 따라, 액티브패턴의 밀도 뿐만 아니라 더미 액티브패턴의 폭과 스페이스에 변화가 발생되지 않는다.That is, when the gap fill oxide film is formed by HDP-CVD in an STI of 0.25 μm or less, and then the gap fill oxide film is CMP, as the active pattern is patterned the same as the dummy main chip, not only the density of the active pattern but also the dummy active There is no change in the width and space of the pattern.
본 발명에 따르면, 반도체 칩 내의 더미 액티브패턴이 삽입될 필드영역에 메인 칩과 동일한 밀도, 크기 및 스페이서를 가진 패턴을 삽입시킴으로써, 기존의 더미 액티브패턴과 메인 칩 간의 차이를 없앨 수 있으며, 이로써 STI CMP 공정 이 후 균일도를 향상시킬 수 있다.According to the present invention, by inserting a pattern having the same density, size, and spacer as the main chip in the field region into which the dummy active pattern is inserted in the semiconductor chip, the difference between the existing dummy active pattern and the main chip can be eliminated. Uniformity can be improved after the CMP process.
이상에서와 같이, 본 발명은 반도체 칩 내의 필드영역에 삽입될 더미 액티브패턴을 메인칩과 동일한 밀도, 사이즈 및 스페이스와 동일하게 함으로써, 기존의 더미 액티브패턴과 메인 칩간의 폭, 스페이스 차이와 패턴 밀도에 따른 차이를 없앨 수 있다. As described above, the present invention makes the dummy active pattern to be inserted into the field region in the semiconductor chip the same density, size, and space as that of the main chip, thereby providing a width, space difference, and pattern density between the existing dummy active pattern and the main chip. You can eliminate the difference.
따라서, 본 발명은 STI 에서 갭필옥사이드막의 씨엠피 공정 이후 균일도가 향상될 뿐만 아니라, 기존의 더미 액티브 어레이 선택 시 가져올 수 있는 변수를 제거할 수 있다.Therefore, the present invention not only improves the uniformity after the CMP process of the gap fill oxide film in the STI, but also eliminates a variable that can be brought about when selecting a conventional dummy active array.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1 내지 도 3은 본 발명에 따른 더미 액티브패턴 형성방법을 설명하기 위한 멀티칩 배치도.1 to 3 is a multi-chip layout for explaining a method of forming a dummy active pattern according to the present invention.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050104959A (en) * | 2004-04-30 | 2005-11-03 | 매그나칩 반도체 유한회사 | Method for chemical mechanical polishing using cross-shaped dummy pattern |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050104959A (en) * | 2004-04-30 | 2005-11-03 | 매그나칩 반도체 유한회사 | Method for chemical mechanical polishing using cross-shaped dummy pattern |
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