CN1314106C - Flush type trench capacitor and method for making same - Google Patents
Flush type trench capacitor and method for making same Download PDFInfo
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- CN1314106C CN1314106C CNB2003101223600A CN200310122360A CN1314106C CN 1314106 C CN1314106 C CN 1314106C CN B2003101223600 A CNB2003101223600 A CN B2003101223600A CN 200310122360 A CN200310122360 A CN 200310122360A CN 1314106 C CN1314106 C CN 1314106C
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- 239000003990 capacitor Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 236
- 239000000463 material Substances 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 230000002950 deficient Effects 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 150000004756 silanes Chemical class 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 150000003376 silicon Chemical class 0.000 claims 2
- 230000003647 oxidation Effects 0.000 abstract description 11
- 238000007254 oxidation reaction Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 6
- 238000000231 atomic layer deposition Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000005039 memory span Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
The present invention relates to an embedded type slot capacitor and a manufacturing method thereof. The method has the steps that an embedded electrode region is formed in a substrate on the lower part of a slot, and then, a first mask layer is formed on the surface on which the embedded electrode region is exposed; after that the self-pinch atomic layer deposition of fabrication process is carried out so as to form a second mask layer on the surface of the slot outside the first mask layer; subsequently, the fabrication process of heat oxidation is carried out so as to enable the region exposed on the surface of the slot to form a collar oxide layer the first, the second mask layers are removed, and then, a capacitance dielectric layer is formed on the surface of the slot; finally, a first conducting layer is formed in the slot which is below the top of the collar oxide layer, and the capacitance dielectric layer which is exposed is removed. Because the present invention firstly manufactures the collar oxidizing layer, and then the collar oxidizing layer is filled in the conducting layer, fabrication process can be simplified.
Description
Technical field
The present invention relates to the manufacture method of a kind of memory element (memory device), particularly a kind of flush type trench capacitor (buried trench capacitor) and manufacture method thereof that is used for dynamic random access memory.
Background technology
When semiconductor entered the manufacture craft of deep-sub-micrometer (Deep Sub-Micron), size of component was dwindled gradually, for DRAM structure in the past, just represented as the space of capacitor more and more little.On the other hand, because computer application software is huge gradually, therefore required memory span is also just more and more big, for this size decreases and memory span needs the situation that increases, the manufacture method of the capacitor of original dynamic random access memory must change to some extent, and is required to meet trend.
Generally speaking, the method for increase capacitor stores electric charge ability has a variety of, for example by increasing the area of capacitor, the whole amount of charge that is stored in the capacitor is increased.And seek new storage capacitor structures and manufacture method thereof, so that under the situation of dwindling on the shared plane of holding capacitor, still keeping required capacitance will be one of following target of desiring to reach of constantly increase situation of present assembly integrated level.
Have a kind of capacitor that has high store charge ability and be called " trench capacitor " to be widely used in the memory element at present, its manufacture craft is shown in Figure 1A to Fig. 1 G.
Figure 1A to Fig. 1 G is the manufacturing process generalized section of known a kind of trench capacitor.Please earlier with reference to Figure 1A, known production method is that substrate 100 is provided earlier, and forms one deck pad oxide 101 and one deck silicon nitride layer 103 in this substrate 100.Then, use pad oxide 101 and silicon nitride layer 103 as etching mask (mask), and in substrate 100, form groove 110.Then, form embedded electrode district 102 in the substrate 100 around deep trench 110 Lower Halves after, again at deep trench 110 surface coverage one deck capacitance dielectric layers (capacitor dielectric) 104.
Then, please refer to Figure 1B, form the first conductive layer 106a in deep trench 110, this first conductive layer 106a is present in the Lower Half of deep trench 110.Then, remove the capacitance dielectric layer 104 that is not covered by the first conductive layer 106a.
Subsequently, please refer to Fig. 1 C, utilize time aumospheric pressure cvd manufacture craft (sub-atmosphericchemical vapor deposition, SACVD) form layer of oxide layer 108 in the groove 110 on the first conductive layer 106a after, the manufacture craft of annealing (anneal process) makes its densification.
Then, please refer to Fig. 1 D, etch-back oxide layer 108, utilize the anisotropic etching manufacture craft, remove the oxide layer 108 on silicon nitride layer 103 surface and the first conductive layer 106a, exposing the first conductive layer 106a surface, thereby form neck oxide layer (collar oxide) 108a in the capacitor.
Afterwards, please refer to Fig. 1 E, in groove 110, form one deck second conductive layer 106b, and the first conductive layer 106a and the second conductive layer 106b are electrically connected.Then, remove the part second conductive layer 106b, make its end face be lower than substrate 100 end faces.
Subsequently, please refer to Fig. 1 F, remove the above neck oxide layer 108a that is exposed of the second conductive layer 106b, in groove 110 tops, form a flush type band (buried strap, BS) 112 again.
Then, please refer to Fig. 1 G, in groove 110, fill up one the 3rd conductive layer 106c, remove part the 3rd conductive layer 106c again, make its end face be lower than substrate 100 end faces.
By aforementioned manufacture craft as can be known, desire to finish trench capacitor and need pass through the multiple tracks step, particularly more need to carry out repeatedly deposition, the planarization of conductive layer and step back manufacture crafts such as (recession) by the top electrode that the multilayer conductive layer constituted.Therefore, structure and manufacture craft how to simplify this trench capacitor will be one of emphasis of future development.In addition, because the neck oxide layer has the function that prevents to go up in vertical parasitic element (vertical parasitic device) electric leakage,, thereby hinder assembly toward the more development of miniaturization so its thickness and length can't be dwindled with assembly.Moreover, because the neck oxide layer is to utilize time aumospheric pressure cvd manufacture craft to form,, make the follow-up problem that is difficult for inserting that has when inserting conductive layer so it can occupy the space of groove.
Summary of the invention
Purpose of the present invention is exactly the manufacture method in the neck oxide layer that a kind of flush type trench capacitor is provided, and can reduce the space that the neck oxide layer occupies groove, in order to the manufacture craft of inserting of subsequent conductive layer.
A further object of the present invention is exactly in the manufacture method that a kind of flush type trench capacitor is provided, and can simplify manufacture craft and can make assembly toward more miniaturization development.
Another object of the present invention provides a kind of flush type trench capacitor, can reduce the space that the neck oxide layer occupies groove, is beneficial to inserting of conductive layer, and is beneficial to the miniaturization development of assembly.
The present invention proposes a kind of manufacture method of neck oxide layer of flush type trench capacitor, comprises forming a groove earlier in a substrate, forms one deck first mask layer on the surface of groove bottom again.Then, carry out together as from deficient ald (self starved atomic layer deposition, ALD) manufacture craft, so that the part flute surfaces beyond first mask layer forms one deck second mask layer, wherein second mask layer and first mask layer at a distance of a segment distance, and expose the part substrate of trenched side-wall at trenched side-wall.Subsequently, carry out that (local oxidation of silicon, thermal-oxidative production process LOCOS) is so that form one deck neck oxide layer in the substrate of trenched side-wall exposed portions as the silicon selective oxidation.
According to the described manufacture method of the preferred embodiments of the present invention, the above-mentioned flute surfaces that exposes about the embedded electrode district forms the step of first mask layer, for example form a material layers earlier in flute surfaces, in groove, form a photoresist layer again, remove part photoresist layer again, to expose the part material layers more than the embedded electrode district, then to remove the part material layers that exposes.In addition, first mask layer and second mask layer can be removed after the silicon selective oxidation manufacture craft.
The present invention reintroduces a kind of manufacture method of flush type trench capacitor, comprises forming a groove earlier in a substrate, forms an embedded electrode district again in the substrate of groove bottom, exposes the surface again in the embedded electrode district and forms one first mask layer.Then, carry out together as manufacture craft from deficient ald, so that the part flute surfaces beyond first mask layer forms one second mask layer, wherein second mask layer and first mask layer be at a trenched side-wall segment distance apart, and expose the part substrate of trenched side-wall.Subsequently, carry out thermal-oxidative production process,, remove first mask layer and second mask layer again so that form a neck oxide layer in the substrate of trenched side-wall exposed portions as the silicon selective oxidation.Then, form a capacitance dielectric layer in flute surfaces, form one first conductive layer again in groove, make the end face of first conductive layer be lower than the top of leading oxide layer, wherein first conductive layer is the top electrode as capacitor, removes the capacitance dielectric layer that exposes afterwards.
According to the described manufacture method of the preferred embodiments of the present invention, the above-mentioned flute surfaces that exposes in the embedded electrode district forms the step of first mask layer, for example form a material layers earlier in flute surfaces, in groove, form a photoresist layer again, remove part photoresist layer again, to expose the part material layers more than the embedded electrode district, then to remove the part material layers that exposes.In addition, manufacture method of the present invention also can form a flush type band in the substrate around the groove on the neck oxide layer after removing the capacitance dielectric layer that exposes, fill up one second conductive layer again in groove.
The present invention proposes a kind of flush type trench capacitor in addition, comprises a substrate, a neck oxide layer, an embedded electrode district, one first conductive layer and a capacitance dielectric layer, wherein has a groove in the substrate.The neck oxide layer is to be arranged in the part flute surfaces and to be partially embedded in substrate, and the embedded electrode district is the substrate around the groove that is arranged under the neck oxide layer, and wherein the embedded electrode district is the bottom electrode as capacitor.First conductive layer then is the following groove of end face that is positioned at the neck oxide layer, and wherein first conductive layer is the top electrode as capacitor, and capacitance dielectric layer is between first conductive layer and embedded electrode district and neck oxide layer.
According to the described flush type trench capacitor of the preferred embodiments of the present invention, above-mentioned structure more comprises a flush type band and one second conductive layer, wherein the flush type band is the substrate around the groove that is arranged on the neck oxide layer, and second conductive layer is to be arranged on first conductive layer of groove.
The present invention utilizes silicon selective oxidation manufacture craft to form the neck oxide layer because utilize mask layer that the part flute surfaces is covered earlier again, therefore can directly form the conductive layer as top electrode after oxide layer forms, and then simplify manufacture craft in groove.Simultaneously, because the neck oxide layer is formed with silicon selective oxidation manufacture craft, is to be embedded in the substrate so have part neck oxide layer, thereby can enlarges the sectional area of conductive layer between the neck oxide layer.Moreover, because the shared space of the neck oxide layer that the space that the neck oxide layer occupies groove makes than known technology is little, therefore help inserting of subsequent conductive layer.
For foregoing of the present invention and other purpose, feature and advantage can be become apparent, hereinafter in conjunction with specific embodiments, and conjunction with figs., be described in detail below.
Description of drawings
Figure 1A to Fig. 1 G is the manufacturing process generalized section of known a kind of trench capacitor.
Fig. 2 A to Fig. 2 J is the manufacturing process generalized section according to the flush type trench capacitor of a preferred embodiment of the present invention.
The drawing reference numeral explanation
100,200: substrate
101,201: pad oxide
102,202: the embedded electrode district
103,203: silicon nitride layer
104,214,214a: capacitance dielectric layer
106a, 106b, 106c, 216,220: conductor layer
108: oxide layer
108a, 212: the neck oxide layer
110,210: groove
112,218: the flush type band
204,204a, 208: mask layer
205: the zone
206: the photoresist layer
Embodiment
Fig. 2 A to Fig. 2 J is the manufacturing process generalized section according to the flush type trench capacitor of the preferred embodiment among the present invention.
Please refer to Fig. 2 A, present embodiment is to form a groove 210 earlier in substrate 200, and its manufacture craft for example is to form one deck pad oxide 201 and one deck silicon nitride layer 203 in substrate 200 in regular turn.Behind patterning pad oxide 201 and the silicon nitride layer 203, use pad oxide 201 and silicon nitride layer 203, in substrate 200, form groove 210 as etching mask (mask).Etching the method for groove 210 in substrate 200, for example is the dry-etching method.Afterwards, form an embedded electrode district 202 in the substrate 200 of groove 210 bottoms, it is the bottom electrode as capacitor.And the step that forms embedded electrode district 202 for example forms conformal doping insulating barrier (not drawing) earlier in groove 210, its material for example be the arsenic silex glass (arsenic silicate glass, ASG).Then, remove part doping insulating barrier, carry out an annealing manufacture craft (anneal process) again, the dopant diffusion in this doping insulating barrier is entered in the substrate 200 near groove 210 tops, to form embedded electrode district 202, remove remaining doping insulating barrier at last.
Then, please refer to Fig. 2 B～Fig. 2 D, groove 210 surfaces that expose in embedded electrode district 202 form one first mask layer 204a, its detailed step for example is to form one deck material layers 204 (also being mask layer) with groove 210 surfaces earlier in substrate 200, one of its formation method for example is low-pressure chemical vapor deposition manufacture craft (low pressure CVD, LPCVD), and this material layers 204 be nitration case for example.Then, in Fig. 2 C, demonstrate and in groove 210, form one deck photoresist layer 206, remove part photoresist layer 206 again, to expose part first mask layer 204 of embedded electrode district more than 202.Shown in Fig. 2 D, be mask afterwards, remove part first mask layer 204 that exposes, cover groove 210 Lower Halves, remove residual photoresist layer 206 then fully to stay the first mask layer 204a with photoresist layer 206.
Afterwards, please refer to Fig. 2 E, carry out together as from deficient ald (self starved atomiclayer deposition, ALD) manufacture craft, so that 210 surfaces of the part groove beyond the first mask layer 204a form one deck second mask layer 208, wherein second mask layer 208 and the first mask layer 204a at groove 210 sidewalls at a distance of a distance, and expose the part substrate 200 (i.e. zone 205) of groove 210 sidewalls, for example be to feed earlier to comprise the gas of a silanes wherein to groove 210 surfaces from deficient ald manufacture craft, to form a silicon single-layer (not drawing) on groove 210 surfaces, feeding comprises the surface of the gas of a nitrogen to silicon single-layer again, is second mask layer 208 of silicon nitride to form material.Because the characteristics from deficient ald are that sedimentary deposit only can form near big groove 210 tops of depth-width ratio (aspect ratio), and can not be deposited on whole groove 210 surfaces.Therefore, have the knack of this operator and should understand the present invention can control second mask layer 208 by control from the parameter of deficient ald manufacture craft formation position.
Subsequently, please refer to Fig. 2 F, carry out that (local oxidation of silicon, thermal-oxidative production process LOCOS) form neck oxide layers 212 with the zone 205 on groove 210 surfaces that expose as the silicon selective oxidation.Can then finish the making of capacitor afterwards.
Then, please refer to Fig. 2 G, remove the first mask layer 204a and second mask layer 208 (asking for an interview Fig. 2 F), forming a capacitance dielectric layer (capacitor dielectric) 214 on groove 210 surfaces again, for example is silicon oxide/silicon nitride/silicon oxide stack layer (ONO) or nitrogenize silicon/oxidative silicon stack layer (NO).
Then, please refer to Fig. 2 H, in groove 210, form one deck first conductive layer 216, make the end face of first conductive layer 216 be lower than the top of leading oxide layer 212, the wherein material of first conductive layer 216 such as doped polycrystalline silicon, and this first conductive layer 216 is the top electrodes as capacitor.And the making of aforementioned first conductive layer 216 can be to form a conductive layer earlier to fill up groove 210 in substrate 200, utilize as the cmp manufacture craft conductive layer beyond the groove 210 is worn again, then utilize etching process to remove the partially conductive layer, so that the end face of first conductive layer 216 is lower than the top of neck oxide layer 212.
Afterwards, please refer to Fig. 2 I, remove the capacitance dielectric layer 214 that exposes, to keep the capacitance dielectric layer 214a between first conductive layer 216 and embedded electrode district 202 and neck oxide layer 212.Then, also optionally form a flush type band (buried strap, BS) 218 in the groove on neck oxide layer 212 210 substrate 200 on every side.
Then, please refer to Fig. 2 J, fill up one deck second conductive layer 220 in groove 210, remove part second conductive layer 220 again, wherein the material of second conductive layer 220 for example is a doped polycrystalline silicon.
Flush type trench capacitor proposed by the invention then can wherein comprise substrate 200, neck oxide layer 212, embedded electrode district 202, first conductive layer 216 and capacitance dielectric layer 214a with reference to Fig. 2 J equally at least, wherein has groove 210 in the substrate 200.Neck oxide layer 212 is to be arranged in part groove 210 surfaces and to be partially embedded in substrate 200, and embedded electrode district 202 is the substrates 200 around the groove 210 that is arranged under the neck oxide layer 212, and wherein embedded electrode district 202 is the bottom electrodes as capacitor.216 of first conductive layers are the following grooves 210 of end face that is positioned at neck oxide layer 212, wherein first conductive layer 216 is the top electrodes as capacitor, and capacitance dielectric layer 214a is between first conductive layer 216 and embedded electrode district 202 and neck oxide layer 212.In addition, the flush type trench capacitor among this figure can comprise that also a flush type band 218 is arranged in groove 210 substrate 200 on every side on the neck oxide layer 212, and the first conductive layer 214a that also has one deck second conductive layer to be arranged in groove 210 goes up and is electrical connected with it.
In sum, characteristics of the present invention comprise:
Utilize mask layer that the part flute surfaces is covered earlier, utilize silicon selective oxidation manufacture craft to form the neck oxide layer again, therefore can form the direct conductive layer that in groove, forms as top electrode in back, thereby simplify manufacture craft in oxide layer.
Simultaneously, because having part with the formed neck oxide layer of silicon selective oxidation manufacture craft is to be embedded in the substrate, so can reduce the space that the neck oxide layer occupies groove, make it not influence the neck oxide layer and go up the function of electric leakage, so capacitor of the present invention can be toward more miniaturization development in vertical parasitic element (vertical parasitic device).
Moreover, because the shared space of the neck oxide layer that the space that the neck oxide layer occupies groove makes than known technology is little, therefore help inserting of subsequent conductive layer.
Though the present invention discloses preferred embodiment as above; but it is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be as the criterion with the scope that claim defines.
Claims (22)
1. the manufacture method of the neck oxide layer of a flush type trench capacitor comprises:
One substrate is provided, in this substrate, is formed with a groove;
Form one first mask layer on the surface of this groove bottom;
Carry out one from deficient ald manufacture craft, so that this flute surfaces of part beyond this first mask layer forms one second mask layer, this second mask layer and this first mask layer at a distance of a segment distance, and expose this substrate of part of this trenched side-wall at this trenched side-wall;
Carry out a thermal-oxidative production process, so that form a neck oxide layer in this substrate of this trenched side-wall exposed portions.
2. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 1 is wherein carried out also comprising after this thermal-oxidative production process and is removed this first mask layer and this second mask layer.
3. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 1 wherein should comprise from deficient ald manufacture craft:
Feeding comprises that the gas of a silanes is to this flute surfaces, to form a silicon single-layer in this flute surfaces; And
Feeding comprises the surface of the gas of a nitrogen to this silicon single-layer.
4. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 3, wherein the material of this second mask layer comprises silicon nitride.
5. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 1, the step that wherein forms this first mask layer on the surface of this groove bottom comprises:
Form a material layers in this flute surfaces;
In this groove, form a photoresist layer;
Remove this photoresist layer of part, to expose this residual this material layers of part more than photoresist layer; And
Remove this material layers of part that exposes.
6. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 5 wherein also comprises after the step that removes this material layers of part that exposes and removes this residual photoresist layer fully.
7. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 5 wherein comprises the low-pressure chemical vapor deposition manufacture craft in the method that this flute surfaces forms this material layers.
8. the manufacture method of the neck oxide layer of flush type trench capacitor as claimed in claim 1, wherein this first mask layer comprises nitration case.
9. the manufacture method of a flush type trench capacitor comprises:
In a substrate, form a groove;
Form an embedded electrode district in this substrate of this groove bottom, this embedded electrode district is as a bottom electrode;
This flute surfaces that exposes in this embedded electrode district forms one first mask layer;
Carry out one from deficient ald manufacture craft, so that this flute surfaces of part beyond this first mask layer forms one second mask layer, this second mask layer and this first mask layer at a distance of a segment distance, and expose this substrate of part of this trenched side-wall at this trenched side-wall;
Carry out a thermal-oxidative production process, so that form a neck oxide layer in this substrate of this trenched side-wall exposed portions;
Remove this first mask layer and this second mask layer;
Form a capacitance dielectric layer in this flute surfaces;
Form one first conductive layer in this groove, make the end face of this first conductive layer be lower than the top of this neck oxide layer, this first conductive layer is as a top electrode; And
This capacitance dielectric layer that removal exposes.
10. the manufacture method of flush type trench capacitor as claimed in claim 9 wherein should comprise from deficient ald manufacture craft:
Feeding comprises the gas of a silanes to this flute surfaces, to form a silicon single-layer in this flute surfaces; And
Feeding comprises the surface of the gas of a nitrogen to this silicon single-layer.
11. the manufacture method of flush type trench capacitor as claimed in claim 10, wherein the material of this second mask layer comprises silicon nitride.
12. the manufacture method of flush type trench capacitor as claimed in claim 9, wherein this flute surfaces that exposes in this embedded electrode district step of forming this first mask layer comprises:
Form a material layers in this flute surfaces;
In this groove, form a photoresist layer;
Remove this photoresist layer of part, to expose this this material layers of part more than embedded electrode district; And
Remove this material layers of part that exposes.
13. the manufacture method of flush type trench capacitor as claimed in claim 12 wherein also comprises after the step that removes this material layers of part that exposes and removes this residual photoresist layer fully.
14. the manufacture method of flush type trench capacitor as claimed in claim 12 wherein comprises the low-pressure chemical vapor deposition manufacture craft in the method that this flute surfaces forms this material layers.
15. the manufacture method of flush type trench capacitor as claimed in claim 9, wherein this first mask layer comprises nitration case.
16. the manufacture method of flush type trench capacitor as claimed in claim 9, wherein the material of this first conductive layer comprises doped polycrystalline silicon.
17. the manufacture method of flush type trench capacitor as claimed in claim 9, wherein this capacitance dielectric layer comprises silicon oxide/silicon nitride/silicon oxide stack layer or nitrogenize silicon/oxidative silicon stack layer.
18. the manufacture method of flush type trench capacitor as claimed in claim 9, the step that wherein forms this embedded electrode district comprises:
In this groove, form a conformal doping insulating barrier;
Removing should the doping insulating barrier near the part on this groove top; And
Carry out an annealing manufacture craft, the dopant diffusion in this doping insulating barrier is entered in this substrate, to form this embedded electrode district.
19. the manufacture method of flush type trench capacitor as claimed in claim 18, wherein carry out also comprising after this annealing manufacture craft remove remaining should the doping insulating barrier.
20. the manufacture method of flush type trench capacitor as claimed in claim 18, material that wherein should the doping insulating barrier comprises the arsenic silex glass.
21. the manufacture method of flush type trench capacitor as claimed in claim 9 also comprises after wherein removing the step of this capacitance dielectric layer that exposes:
Form a flush type band in this substrate around this groove on this neck oxide layer;
In this groove, fill up one second conductive layer; And
Remove this second conductive layer of part.
22. the manufacture method of flush type trench capacitor as claimed in claim 21, wherein the material of this second conductive layer comprises doped polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101223600A CN1314106C (en) | 2003-12-19 | 2003-12-19 | Flush type trench capacitor and method for making same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101223600A CN1314106C (en) | 2003-12-19 | 2003-12-19 | Flush type trench capacitor and method for making same |
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| Publication Number | Publication Date |
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| CN1630064A CN1630064A (en) | 2005-06-22 |
| CN1314106C true CN1314106C (en) | 2007-05-02 |
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| CNB2003101223600A Expired - Fee Related CN1314106C (en) | 2003-12-19 | 2003-12-19 | Flush type trench capacitor and method for making same |
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| US11309214B2 (en) * | 2020-08-11 | 2022-04-19 | Nanya Technology Corporation | Semiconductor device with graphene-based element and method for fabricating the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281259A (en) * | 1999-07-14 | 2001-01-24 | 国际商业机器公司 | Integration scheme for raising deep groove capacity in semiconductor integrated circuit device |
| US6281069B1 (en) * | 2000-09-29 | 2001-08-28 | United Microelectronics Corp. | Method for forming deep trench capacitor under a shallow trench isolation structure |
| US6326261B1 (en) * | 2001-01-05 | 2001-12-04 | United Microelectronics Corp. | Method of fabricating a deep trench capacitor |
| US6605838B1 (en) * | 2002-09-30 | 2003-08-12 | International Business Machines Corporation | Process flow for thick isolation collar with reduced length |
-
2003
- 2003-12-19 CN CNB2003101223600A patent/CN1314106C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281259A (en) * | 1999-07-14 | 2001-01-24 | 国际商业机器公司 | Integration scheme for raising deep groove capacity in semiconductor integrated circuit device |
| US6281069B1 (en) * | 2000-09-29 | 2001-08-28 | United Microelectronics Corp. | Method for forming deep trench capacitor under a shallow trench isolation structure |
| US6326261B1 (en) * | 2001-01-05 | 2001-12-04 | United Microelectronics Corp. | Method of fabricating a deep trench capacitor |
| US6605838B1 (en) * | 2002-09-30 | 2003-08-12 | International Business Machines Corporation | Process flow for thick isolation collar with reduced length |
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| CN1630064A (en) | 2005-06-22 |
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