CN1767199A - Dynamic random access memory unit, array thereof, and method for manufacturing the array - Google Patents

Abstract

The present invention relates to a dynamic random access memory cell and its array, and a method for manufacturing the array. The dynamic random access memory cell comprises a semiconductor column on a substrate, a capacitor at the lower part of the side wall of the semiconductor column, and a vertical transistor at the upper part of the side wall of the semiconductor column. The capacitor comprises a first plate at the lower part of the side wall of the semiconductor column, a second plate around the first plate and serving as an upper electrode, a third plate around the second plate, and a dielectric layer separating the second plate from the first and third plates. The third plate is electrically connected to the first plate to form a lower electrode. In addition, based on the dynamic random access memory cell, the present invention further proposes a dynamic random access memory array and a method for manufacturing the array.

Description

Dynamic random access memory unit, array thereof, and method for manufacturing the array

technical field

The present invention relates to a semiconductor device, and in particular to a storage unit and an array structure of a DRAM, and a manufacturing process of the DRAM array. DRAM cells feature capacitors with high capacitance.

Background technique

In the semiconductor industry, DRAM is one of the most important integrated circuits, so it stimulates continuous research and development. Increasing the storage capacity, improving the writing and reading speed, and reducing the device area size of the DRAM cell are the goals of continuous efforts. In general, a DRAM cell includes a transistor and a capacitor operated by the transistor. Traditionally, the design of DRAM cells can be divided into three types, namely planar, stacked capacitor and trench. In a planar design, the transistors and capacitors of the memory cell are fabricated with planar components. In a stacked capacitor design, the capacitor of the memory cell is placed above the transistor. In a trench design, the transistors are placed on the surface of the substrate, and the capacitors are placed in trenches formed in the substrate.

However, in the process of forming the trench, the operation of the mask requires very precise alignment. For deep sub-micron semiconductor devices, deep trenches may have an aspect ratio of 40:1 in length to diameter. Capacitors are typically formed by first depositing a dielectric layer on the sidewalls of a deep and narrow trench, and then filling the trench with a doped polysilicon layer. As the aspect ratio becomes larger, for example greater than 20:1, it becomes more difficult to fill the trench.

Contents of the invention

In view of this, the object of the present invention is to provide a dynamic random access memory unit, which has a capacitor formed on the sidewall of the semiconductor pillar, to solve the existing problem of filling the trench, and to increase the surface area of the capacitor .

Another object of the present invention is to provide a DRAM array based on the DRAM cell structure of the present invention. Since the vertical transistors are formed as memory cells, the DRAM array can have a higher degree of integration.

Another object of the present invention is to provide a method for fabricating a DRAM array, so as to solve the existing problem of filling trenches, increase the capacitance of capacitors, and increase the integration of DRAM elements.

The dynamic random access memory unit of the present invention includes a semiconductor pillar formed on a substrate, a capacitor formed on the lower part of the sidewall of the semiconductor pillar, and a vertical transistor formed on the upper part of the sidewall of the semiconductor pillar. The capacitor includes a first plate, a second plate, a third plate and a dielectric layer. Wherein, the first flat plate is arranged on the lower part of the sidewall of the semiconductor column, and the second flat plate is arranged around the first flat plate and serves as an upper electrode. The third plate is arranged around the second plate, and is electrically connected with the first plate to form a lower electrode together. The dielectric layer separates the second plate from the first plate and the third plate. The vertical transistor is electrically coupled to the capacitor.

According to a preferred embodiment of the present invention, the first plate and the third plate are electrically connected to each other by design, wherein the first plate further extends into the substrate next to the semiconductor pillar, and the third plate is in contact with the substrate next to the semiconductor pillar. However, the first plate and the third plate can also be electrically connected through other connection designs.

The DRAM array of the present invention includes the columns and rows of memory cells mentioned above in the present invention, and a plurality of bit lines and word lines. These memory cells are arranged on a semiconductor substrate and have the same structure as described above. Each bit line is electrically coupled to the vertical transistors of a column of memory cells, and each word line is electrically coupled to the vertical transistors of a row of memory cells. Furthermore, the first plates of all capacitors are connected to each other by the doped surface layer of the base between the semiconductor pillars, so that the first and third plates of all memory cells constitute a common lower electrode.

The following is a description of the manufacturing method of the DRAM unit of the present invention. Patterning the semiconductor substrate to form semiconductor pillars arranged in rows and columns thereon, and then forming capacitors on the lower portion of the sidewall of each semiconductor pillar, includes the following steps. Firstly, a first plate serving as a doped region is formed in the lower portion of the sidewall of each semiconductor pillar. Then, a first dielectric layer is formed around each first flat plate, and a second flat plate is formed around each first dielectric layer as an upper electrode. Then, a second dielectric layer is formed around each second plate, and a third plate is formed around each second dielectric layer, and the corresponding first plate is electrically connected to form a lower electrode. After that, a vertical transistor is formed on the upper portion of the sidewall of each semiconductor pillar, and is electrically coupled with the corresponding capacitor. Then, a plurality of bit lines and word lines are formed, wherein each bit line is electrically coupled to the transistors of a row of memory cells, and each word line is electrically coupled to the transistors of a row of memory cells.

Since the capacitors in the DRAM of the present invention are formed around the semiconductor pillars rather than within the deep trench, the problem of filling the trench due to the aspect ratio of the deep trench in the prior art is thus solved. . At the same time, the surface area and capacitance of the capacitor become quite large, because the capacitor can be formed on all sidewalls of the semiconductor pillar, and the second plate as the upper electrode is embedded between the first plate and the third plate, making the capacitor more stable. multiplied.

In addition, because the transistors of the DRAM cell of the present invention are formed in a vertical structure, the lateral area occupied by the memory cell can be greatly reduced to significantly increase the integration of the DRAM array. In other words, the DRAM array can have a higher degree of integration.

Furthermore, because in the DRAM array manufacturing method of the present invention, the capacitors are formed around the semiconductor pillars, the existing problem of filling the trenches is eliminated. Therefore, the quality of the access capacitor can be improved.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail together with accompanying drawings.

Description of drawings

1 to 18 are schematic diagrams illustrating the manufacturing process of a DRAM array according to a preferred embodiment of the present invention. 1 to 7 illustrate a method for manufacturing a capacitor, FIGS. 8 to 14 illustrate a method for manufacturing a vertical transistor, and FIGS. 15 to 18 illustrate subsequent steps, including bit lines and How character lines are made.

17 and 18 illustrate the structures of DRAM cells and arrays according to preferred embodiments of the present invention.

Explanation of reference signs

100: Semiconductor substrate 102: Pad oxide layer

104, 136: Patterned mask layer 110: Semiconductor pillars

112, 142, 144: Doped region 114: Conformal dielectric layer

116, 120, 122, 1264, 132: conductor layer

118, 124, 1262, 134, 1462: spacers

118a, 128, 130, 138, 148: insulating layer

126: Upper electrode 1266: Lower electrode

127: Capacitor 132a: Gate

1361: pattern 140: ion implantation

145: Transistor 146: Bit line

1461: Cap layer 150: Character line

152: contact window

Detailed ways

Fig. 1 clearly shows a perspective view of a DRAM array, and Fig. 2 to Fig. 11, Fig. 13 to Fig. 15 and Fig. 18(a) are schematic cross-sectional views along line II' in Fig. 1, And FIG. 18( b ) is another schematic cross-sectional view, and FIG. 12 , FIG. 16 and FIG. 17 are all top views.

More particularly, FIG. 1 to FIG. 7 are schematic diagrams showing the manufacturing process of capacitors forming DRAM arrays, and FIG. 8 to FIG. 14 are schematic diagrams showing the manufacturing process of transistors forming DRAM arrays. , and FIG. 15 to FIG. 18 illustrate subsequent steps, including manufacturing methods of bit lines and word lines.

<Manufacturing method of capacitor>

First, referring to FIG. 1 , a semiconductor substrate 100 is provided, which is made of lightly doped P-type single crystal silicon, and a pad oxide layer 102 and a patterned mask layer 104 are formed on the substrate 100 . Wherein, the patterned mask layer 104 includes rectangular or square blocks arranged in rows and columns, which are formed by, for example, coating a photoresist material on it and performing an etching process, and the patterned mask layer 104 material An example is silicon nitride (SiN). Then, using the patterned mask layer 104 as a mask, the substrate 100 is etched to form semiconductor pillars 110 arranged in rows and columns. It should be noted that, in the top view, the shape of each block of the patterned mask layer 104 can be a circle, an ellipse or other polygons, even if the patterned mask layer 104 in the top view is a rectangle or a square . Of course, in another embodiment, the shape of the semiconductor pillar 110 can be shaped as a cylindrical, elliptical cylindrical or corresponding polygonal semiconductor pillar.

Furthermore, it should be noted that, for convenience, in the following description, the semiconductor pillar 110 and the part of the patterned mask layer 104 thereon are sometimes collectively referred to as the semiconductor pillar 110 .

Referring to FIG. 1 again, the doped region 112 serving as a part of the common lower electrode of the storage capacitor formed later is formed in the lower portion of the sidewall of each semiconductor pillar 110 and the surface layer of the substrate 100 . In addition, a part of the doped region 112 located in each semiconductor pillar 110 is mentioned as the first plate of the capacitor in the summary of the present invention. Meanwhile, the part of the doped region 112 between the semiconductor pillars 110 and inside the substrate 100 is the doped surface layer of the substrate 100 between the semiconductor pillars 110 mentioned in the summary of the invention.

The method of doping includes, for example, the following steps. First, an arsenic-doped silicon oxide layer (not shown) with a predetermined thickness is formed between the semiconductor pillars 110 . Among them, there are two methods for forming the arsenic-doped silicon oxide layer, for example, using an in-situ (in-situ) method to deposit silicon oxide on the substrate 100 while doping arsenic to fill the space between the semiconductor pillars 110. gap, and then etch back the arsenic-doped silicon oxide layer to a preset depth. Alternatively, an arsenic-doped oxide layer is formed to cover the lower portion of the sidewall of the pillar, and a predetermined depth is defined by a photoresist covering and etching back process. After covering the undoped oxide layer on the arsenic-doped oxide layer, a thermal process is performed to heat the arsenic atoms in the arsenic-containing oxide layer into the contact surface layer of the semiconductor pillar 110 and the surface layer of the substrate 100 . Afterwards, the arsenic-doped oxide layer and the undoped oxide layer are removed.

Subsequent steps describe the manufacturing method of the capacitor completely in FIGS. 2 to 7, wherein FIGS. 2 to 7 are schematic cross-sectional views along line I-I' of FIG. 1.

First, referring to FIG. 2 , a conformal dielectric layer 114 is formed between the substrate 100 and the semiconductor pillar 110 . Wherein, the conformal dielectric layer 114 is preferably made of silicon oxide-silicon nitride-silicon oxide (ONO) or silicon nitride-silicon oxide (NO) combination layer, and is used as a capacitor dielectric layer. Then, a conductive layer 116 is formed between the semiconductor pillars 110 , and has a depth almost the same as that of the doped region 112 , or a depth lower than that of the doped region 112 . Wherein, the material of the conductor layer 116 is a conductive material, such as heavily doped N-type polysilicon, and the method of forming it is, for example, using an in-situ method, first depositing a polysilicon layer on the substrate 100 and simultaneously doping to fill the semiconductor pillars 110 gap, and then etch back the polysilicon layer to a preset thickness.

Afterwards, referring to FIG. 3 , the exposed part of the conformal dielectric layer 114 is removed, which can be performed by a wet etching process. When the material of the conformal dielectric layer 114 is, for example, an ONO combination layer including a top oxide layer, a silicon nitride layer, and a bottom oxide layer, the exposed layers can be removed by dilute hydrofluoric acid, phosphoric acid, and dilute hydrofluoric acid, respectively. The top oxide layer, silicon nitride layer and bottom oxide layer.

Then, referring to FIG. 4 , insulating spacers 118 are formed on the sidewalls of each semiconductor pillar 110 on the conductive layer 116 . The material of the insulating spacer 118 includes a dielectric material such as silicon oxide, and the method of forming it is, for example, performing a chemical vapor deposition process (Chemical Vapor Deposition, CVD) and then performing an anisotropic etching process. In addition, it should be noted that although the cross-sectional view shows that the insulating spacers 118 are formed on both sides of the corresponding semiconductor pillars 110 , in fact the insulating spacers 118 are formed around the semiconductor pillars 110 . Afterwards, another conductive layer 120 is formed between the semiconductor pillars 110 on the conductive layer 116 and covers the lower portion of the insulating spacer 118 . Wherein, the material of the conductor layer 120 includes a conductive material, such as heavily doped N-type polysilicon, and the method of forming it is, for example, using an in-situ method to deposit a polysilicon layer on the substrate 100 and dope it at the same time, and then etch back the polysilicon. Layer up to a preset depth.

Next, referring to FIG. 5 , the exposed portion of the insulating spacer 118 on each semiconductor pillar 110 is removed to form a collar insulating layer 118 a surrounding the semiconductor pillar 110 . Next, another conductive layer 122 is formed between the collar insulating layer 118 a and the semiconductor pillars 110 on the conductive layer 120 . Wherein, the material of the conductive layer 122 includes conductive material such as heavily doped N-type polysilicon, and its formation method is the same as the above-mentioned deposition method and etching back method. Afterwards, a mask spacer 124 is formed on the sidewall of each semiconductor pillar 110 on the conductive layer 122, and its thickness is greater than that of the collar insulation 118a. In addition, the mask spacer 124 is used to define the upper electrode of the capacitor, which is described in detail below.

Afterwards, please refer to FIG. 5 and FIG. 6 at the same time, use the mask spacer 124 as a mask, and successively etch the above-mentioned three layers of conductor layers 122, 120, 116 to form an upper sidewall on the lower sidewall of each semiconductor pillar 110. Electrode 126. It is to be noted that the remaining conductive layer 122 , that is, the upper portion of the upper electrode 126 , is in direct contact with the sidewall of the semiconductor pillar 110 . Afterwards, a dielectric spacer 1262 is formed on the sidewalls of the mask spacer 124 and the conductive layers 122 , 120 , 116 . Wherein, the dielectric spacer 1262 may be a combined spacer of silicon nitride and silicon oxide (NO), and its formation method is to sequentially form a silicon nitride layer and a silicon oxide layer, and then perform anisotropic etching to remove Part of the silicon nitride layer and the silicon oxide layer are removed.

Then, referring to FIG. 7 , the exposed dielectric layer 114 is removed, and then a conductive layer 1264 is formed to partially fill the gap in the pillar and contact with part of the doped region 112 of the substrate 100 in the pillar. Therefore, the entire doped region 112 and the conductive layer 1264 together form a common lower electrode 1266 . Meanwhile, it is described in the Summary of the Invention that the part of the doped region 112 corresponding to the semiconductor pillar 110 and the part of the conductor layer 1264 are respectively regarded as the first plate and the third plate.

Wherein, the formation method of the conductive layer 1264 is, for example, to firstly form a conductive material (not shown) to fill the gaps in the columns, and then etch back the conductive material to a preset depth, and the material may be doped polysilicon. In addition, the upper electrode 126 , the two dielectric layers 114 , 1262 and the common lower electrode 1266 together form a capacitor 127 . Since the capacitor 127 is formed on all sidewalls of the semiconductor pillar 110, and the upper electrode 126 is embedded between two parts of the lower electrode 1266, wherein the two parts are the doped region 112 and the conductive layer 1264, therefore, the capacitance of the capacitor 127 quite big.

In addition, in the above-mentioned method of forming a capacitor surrounding each semiconductor pillar, for example, some slight modifications or changes in the materials, the manufacturing method of each layer, and the manufacturing sequence of these layers may also be included in the scope of the present invention. within range.

<Manufacturing method of transistor>

Next, referring to FIG. 8 , the mask spacer 124 and the upper portion of the dielectric layer 1262 are removed, and then the insulating layer 128 is filled in the semiconductor pillar 110 to cover all the capacitors 127 . Wherein, the material of the insulating layer 128 includes a dielectric material, such as silicon oxide, and its formation method is, for example, depositing silicon oxide on the substrate 100 first, and then performing etching back to a predetermined depth. After that, referring to FIG. 9 , a gate insulating layer 130 is formed on the exposed sidewall of each semiconductor pillar 110 . Wherein, the gate insulating layer 130 is, for example, a thin silicon oxide layer or a thin silicon oxide/silicon nitride layer, and its formation method may be a thermal oxidation process or a thermal oxynitride process.

Next, a conductive layer 132 is formed between the semiconductor pillars 110 on the insulating layer 128 and covers the lower portion of the gate insulating layer 130 . Wherein, the material of the conductor layer 132 includes a conductive material, such as heavily doped N-type polysilicon, and the method of forming it is, for example, using an in-situ method, adding an N-type dopant while depositing a polysilicon layer on the substrate 100, and then returning to the substrate 100. This polysilicon layer is etched to a predetermined depth.

After that, referring to FIG. 10 , a mask spacer 134 is formed on the sidewall of each semiconductor pillar 110 on the conductor layer 132 . Wherein, the mask spacer 134 is used to define the gate later, and it is formed of an insulating material, wherein the insulating material is, for example, silicon oxide.

Then, please refer to FIG. 11 and FIG. 12 at the same time, wherein FIG. 12 is a top view of the structure after the following steps are completed, and FIG. 11 is a schematic cross-sectional view along line XI-XI' of FIG. 12 . A patterned mask layer 136 , such as a patterned photoresist layer, is formed on the substrate 100 . And the patterned mask layer 136 includes some parallel and linear patterns 1361 , wherein each linear pattern 1361 covers the semiconductor pillars 110 in the same row and part of the conductive layer 132 between the semiconductor pillars 110 in the same row. Afterwards, the conductive layer 132 is etched using the patterned mask layer 136 and the mask spacer 134 as a mask to form a gate 132 a on the sidewall of each semiconductor pillar 110 . Even if the patterned mask layer 136 is misaligned, the mask spacer 134 enables the corresponding gate 132 a to surround its corresponding semiconductor pillar 110 .

The remaining conductor layer 132 in the same row of semiconductor pillars is connected to the gates 132a on the sidewalls of the same row of semiconductor pillars 110 to form gate lines 132a (dotted areas in the figure), which can be directly referred to as characters Wire. However, another low-resistance conductor line may be formed on the gate line 132a and electrically connected to the gate line 132a to reduce the resistance, which is described below.

In addition, in the above-mentioned formation method of the gate surrounding each semiconductor pillar, for example, some modifications or changes in the materials, the manufacturing method of each layer and the manufacturing sequence of these layers may also be included in the present invention. In the range.

<Manufacturing method of source/drain>

First, referring to FIG. 13 , the gaps between the semiconductor pillars 110 are filled with an insulating layer 138, and the material of the insulating layer 138 is an insulating material, such as silicon oxide, and its formation method is, for example, plasma-enhanced chemical vapor deposition. Plasma Enhanced CVD (PECVD), followed by chemical mechanical polishing (CMP).

After that, referring to FIG. 14 , the patterned mask layer 104 , the pad oxide layer 102 , part of the mask spacer 134 and part of the insulating layer 138 are removed. Wherein, the method of removing the above four parts is, for example, performing chemical mechanical polishing, so that the upper surfaces of the mask spacers 134 and the insulating layer 138 are substantially coplanar with those semiconductor pillars 110 . Next, ion implantation 140 is performed to form a doped region 142 on the upper portion of each semiconductor pillar 110 as a source/drain region. Wherein, the doped region 142 may be an N-type heavily doped region with phosphorous ions or arsenic ions as dopants.

Then, a high temperature tempering process is performed to repair the crystal lattice damaged by the ion implantation 140 to the semiconductor pillars 110, and some dopants of the lower electrode 126 tend to enter the sidewalls of each semiconductor pillar 110 to form doped regions. 144. The two doped regions 142 and 144 , the gate 132 a and the gate insulating layer 130 together form a vertical transistor 145 . It should be noted that although the doped region 144 is not shown in the previous figures, in fact it will be more or less during each thermal process after the upper portion 122 of the lower electrode 126 is formed (as shown in FIG. 5 ). Doped regions 144 are present. However, in a preferred embodiment, the doped region 144 is primarily present during the high temperature tempering process after the doped region 142 is formed.

<Manufacturing method of bit line and word line>

15 and 16 illustrate the steps of forming the bit lines of the memory array, wherein FIG. 16 is a top view of the structure after the following steps are completed, and FIG. 15 is a cross-section along line XV-XV' of FIG. 16 schematic diagram. After the vertical transistor 145 is constructed, a plurality of bit lines 146 are formed on the substrate 100 . Each bit line 146 is in direct contact with the doped regions 142 of the upper portions of the semiconductor pillars 110 in the same column. Wherein, the bit line 146 is made of conductive material, such as heavily doped N-type polysilicon, and is formed by using a deposition-patterning method or a damascene method.

In addition, the capping layer 1461 is disposed on each bit line 146, and assuming that the bit line 146 and the capping layer 1461 are formed by deposition and patterning, the protection spacer 1462 will be formed on each pair of bit lines. line and the side walls of the top cover. Among them, the material for forming the top cover layer 1461 and the protective spacer 1462 is preferably silicon nitride, and its purpose is to prevent the bit line 146 from being exposed in the subsequent etching process of the contact window, so that the contact window can automatically The method of alignment is formed. Afterwards, an insulating layer 148 is formed on the substrate 100 to cover the bit lines 146 and fill the gap between every two bit lines 146 to isolate the bit lines 146 from the word lines formed in the next step.

17 and 18(a) and (b) illustrate the steps of forming additional word lines of the memory array to electrically connect previously formed gate lines. Figure 17 is a top view of the structure after the following steps are completed, and Figure 18(a) and Figure 18(b) are schematic cross-sectional views along the A-A' line and the B-B' line of Figure 17 respectively. After the insulating layer 148 is formed, a plurality of word lines 150 are formed on the substrate 100 . Each word line 150 is electrically connected to a row of gate lines on the sidewalls of the semiconductor pillars 110 through at least one contact window 152 between two semiconductor pillars 110 . In addition, the contact window 152 is in direct contact with the conductive layer 132, and the conductive layer 132 is connected to two gates 132a on the sidewalls of two adjacent semiconductor pillars 110 in the same row.

The method for forming the contact window 152 and the word line 150 is, for example, to first form a contact window opening in the insulating layer 148 to expose a part of the conductive layer 132, and then deposit another conductive layer to cover the insulating layer 148 to fill up the contact window. openings, followed by patterning the conductor layer. Alternatively, a damascene process is used to form the contact holes 152 and the word lines 150 .

In addition, Fig. 17 and Fig. 18(a) and (b) also illustrate the structure of the DRAM unit and the array according to the preferred embodiment of the present invention. Therefore, the structure of the DRAM cell and the array can be understood from the above detailed description of the preferred embodiments.

Please refer to Fig. 17 and Fig. 18 (a) and (b), because the capacitor 127 in the dynamic random access memory unit of the present invention is formed to surround the semiconductor column 110, rather than being formed in the deep trench, so in the prior art The problem of filling the trench due to the aspect ratio of the deep trench therefore does not exist. Simultaneously, the surface area and capacitance of the capacitor 127 become quite large, because the capacitor 127 can be formed on all sidewalls of the semiconductor pillar 110, and the upper electrode 126 is embedded between the two parts 112 and 1164 of the lower electrode 1266, making the capacitance Multiplied even more.

In addition, since the transistor 145 of the DRAM cell of the present invention is formed in a vertical structure, the size of each memory cell can be greatly reduced to significantly increase the integration of the memory array.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.

Claims (40)

1. A dynamic random access storage unit, comprising: a semiconductor pillar located on a substrate; A capacitor, located on a lower portion of a sidewall of the semiconductor pillar, comprising: a first plate located in the lower portion of the sidewall of the semiconductor pillar; a second flat plate located around the first flat plate as an upper electrode; a third plate, located around the second plate, and electrically connected with the first plate to serve as a lower electrode; and a dielectric layer separating the second plate from the first plate and the third plate; and A vertical transistor is located on the upper portion of the sidewall of the semiconductor pillar and is electrically coupled to the capacitor. 2. The dynamic random access memory unit of claim 1, wherein: The first plate and the third plate are electrically connected by a design, wherein the first plate further extends to the base next to the semiconductor pillar, and the third plate contacts the base next to the semiconductor pillar; and The dielectric layer is also disposed on a portion of the first plate in the substrate next to the semiconductor pillar to separate a bottom layer of the second plate from the first plate. 3. The DRAM unit as claimed in claim 2, wherein the dielectric layer comprises: a first dielectric layer between the semiconductor pillar and the second plate, and between the substrate and the second plate; and A second dielectric layer is located between the second plate and the third plate and connected to the first dielectric layer. 4. The DRAM cell of claim 1, wherein the second plate has an upper portion directly contacting a source/drain region of the vertical transistor in the semiconductor pillar. 5. The DRAM cell of claim 1, wherein the first plate, the second plate, the third plate and the dielectric layer surround the semiconductor pillar. 6. The DRAM cell of claim 5, wherein the capacitor further comprises an insulating layer surrounding the semiconductor pillar and covered by an upper portion of the second plate. 7. The DRAM unit of claim 6, wherein the second panel comprises: a first conductor layer surrounding the insulating layer; a second conductor layer located below the first conductor layer and the collar insulating layer; and A third conductive layer is located on the first conductive layer and the insulating layer, and is electrically coupled to the vertical transistor. 8. The DRAM cell of claim 1, wherein the vertical transistor comprises: a first doped region located in the sidewall of the semiconductor pillar and electrically connected to the upper electrode of the capacitor; a second doped region located in the upper portion of the semiconductor pillar; a gate located on the sidewall of the semiconductor pillar between the first doped region and the second doped region; and A gate insulating layer is located between the sidewall of the semiconductor column and the gate. 9. The DRAM cell of claim 8, wherein the gate is isolated from an insulating layer on an upper portion of the upper electrode. 10. The DRAM cell of claim 8, wherein the first doped region, the gate and the gate insulating layer surround the semiconductor pillar. 11. A dynamic random access memory array comprising: A plurality of memory cells arranged in rows and columns are disposed on a substrate, and each of the memory cells includes: a semiconductor pillar located on the substrate; a capacitor located at the lower portion of the side wall of the semiconductor pillar, comprising a first plate located in the lower portion of the side wall of the semiconductor pillar, a second plate located around the first plate as an upper electrode, A third plate is located around the second plate and is electrically connected to the first plate to serve as a lower electrode and a dielectric layer to separate the second plate from the first plate and the third plate; a vertical transistor located on the upper portion of the sidewall of the semiconductor pillar and electrically coupled to the capacitor; a plurality of bit lines, each of the bit lines coupled to the vertical transistors in a column; and A plurality of word lines, each of the word lines is coupled to the vertical transistors in a row. 12. The dynamic random access memory array of claim 11, wherein: The first plates are electrically connected to each other through a doped surface layer of the substrate between the semiconductor pillars; The third plates together form a conductive layer, and the conductive layer partially fills the gap between the semiconductor pillars and contacts the doped surface layer of the substrate; and The first plates, the doped surface layer and the conductor layer together serve as a common lower electrode. 13. The dynamic random access memory array as claimed in claim 12, wherein in each of the memory cells, the dielectric layer comprises: a first dielectric layer between the second slab and the semiconductor pillar, and between the second slab and the doped surface layer of the substrate; and A second dielectric layer is located between the second plate and the third plate and connected to the first dielectric layer. 14. The DRAM array of claim 11, wherein each of the second plates has an upper portion directly contacting a source/drain region of a corresponding vertical transistor. 15. The DRAM array of claim 11, wherein in each of the capacitors, the first plate, the second plate, the dielectric layer and the third plate surround the semiconductor pillar. 16. The DRAM array of claim 15, wherein each of the capacitors further comprises an insulating layer surrounding the corresponding semiconductor pillar and covered by an upper portion of the second plate. 17. The DRAM array of claim 16, wherein the second panel comprises: a first conductor layer surrounding the insulating layer; a second conductor layer located below the first conductor layer and the collar insulating layer; and A third conductor layer is located on the first conductor layer and the collar insulating layer, and is electrically coupled to a corresponding vertical transistor. 18. The DRAM array of claim 11, wherein each of the vertical transistors comprises: a first doped region located in a sidewall of a corresponding semiconductor pillar and electrically connected to an upper electrode of a corresponding capacitor; a second doped region located in the upper portion of the semiconductor pillar; a gate located on the sidewall of the semiconductor pillar between the first doped region and the second doped region; and A gate insulating layer is located between the sidewall of the semiconductor column and the gate. 19. The DRAM array of claim 18, wherein each of the bit lines is in direct contact with the second doped regions of the vertical transistors of the memory cells in the same column. 20. The DRAM array of claim 18, wherein the gates of the memory cells in the same row are connected to each other to form a gate line. 21. The DRAM array of claim 20, wherein the gate line directly serves as a word line of the vertical transistors in the row. 22. The dynamic random access memory array of claim 20, wherein a word line is electrically connected to the gate line through a contact window located at least between two of the semiconductor pillars. 23. A method of manufacturing a dynamic random access memory array, comprising: patterning a semiconductor substrate to form a plurality of semiconductor pillars arranged in rows and columns on the semiconductor substrate; forming a capacitor on a lower portion of a sidewall of each of the semiconductor pillars, comprising: forming a first plate in the lower portion of the sidewall of each of the semiconductor pillars; forming a first dielectric layer around each of the first plates; forming a second plate around each of the first dielectric layers as an upper electrode; forming a second dielectric layer around each of the second plates; and forming a third plate around each of the second dielectric layers, wherein the third plate is electrically connected to a corresponding first plate to form a lower electrode; forming a vertical transistor on an upper portion of a sidewall of each of the semiconductor pillars, and coupling the vertical transistor to a corresponding capacitor; and A plurality of bit lines are formed on the semiconductor substrate, wherein each of the bit lines is coupled to a row of the vertical transistors. 24. The manufacturing method of a dynamic random access memory array as claimed in claim 23, wherein the first plates are formed together with a doped surface layer of the substrate between the semiconductor pillars, so that all the first plates A plate is electrically connected to each other. 25. The manufacturing method of a dynamic random access memory array as claimed in claim 24, wherein the step of forming the first dielectric layer comprises forming a conformal dielectric layer on the doped surface layer of the substrate and each of the on the sidewall of the semiconductor pillar. 26. The method for manufacturing a dynamic random access memory array as claimed in claim 25, wherein the step of forming the third plates comprises: removing the first dielectric layer exposed by the second plate and the second dielectric layer to expose a portion of the doped surface layer between the semiconductor pillars; and A conductive layer is formed to partially fill the gaps between the semiconductor pillars to serve as the third plates of all capacitors. 27. The method for manufacturing a dynamic random access memory array as claimed in claim 25, wherein the step of forming the second plate comprises: forming at least one conductive layer to partially fill the gap between the semiconductor pillars; forming a spacer on the sidewall of each of the semiconductor pillars; and The conductor layer in the second plates is etched by using the spacers as a mask. 28. The method of manufacturing a dynamic random access memory array as claimed in claim 27, wherein the step of forming the second dielectric layers and the third plates comprises: forming a dielectric spacer on the sidewall of each of the spacers and the corresponding second plate, wherein the lower part of the dielectric spacer serves as the second dielectric layer; using the spacer and the dielectric spacer as an etching mask to remove the exposed first dielectric layer; forming a second conductive layer to partially fill the gaps between the semiconductor pillars to serve as the third plates for all capacitors; and The upper portion of each of the spacers and each of the dielectric spacers is removed. 29. The method for manufacturing a dynamic random access memory array as claimed in claim 27, wherein the step of forming at least one conductor layer comprises: forming a first conductive layer to partially fill the gap between the semiconductor pillars; removing the exposed portion of the conformal dielectric layer from the first conductor layer; forming an insulating spacer on the sidewalls of the semiconductor pillars on the first conductor layer; forming a second conductor layer between the semiconductor pillars to cover the lower portions of the insulating spacers; removing a portion of each of the insulating spacers exposed by the second conductive layer to form an insulating layer on each of the semiconductor pillars; and A third conductor layer is formed between the semiconductor pillars and on the collar insulating layer and the second conductor layer. 30. The method of manufacturing a DRAM array as claimed in claim 23, wherein in each of the memory cells, an upper portion of the second plate directly contacts the semiconductor pillar. 31. The method of manufacturing a dynamic random access memory array as claimed in claim 23, wherein the step of forming the vertical transistors comprises: partially filling the gaps between the semiconductor pillars with a first insulating material layer to cover the capacitors; A gate structure of a vertical transistor is formed on the sidewalls of each of the semiconductor pillars on the first insulating layer, and the gate structure includes a gate electrode and a gate electrode between the semiconductor pillar and the gate electrode a gate insulating layer; forming a first doped region of a vertical transistor in the sidewall of each of the semiconductor pillars, the first doped region coupled to the capacitor on the same sidewall of the semiconductor pillar; and A second doped region of a vertical transistor is formed on the upper portion of each of the semiconductor pillars. 32. The method of manufacturing a dynamic random access memory array as claimed in claim 31, wherein the step of forming the gate structure comprises: forming a gate insulating layer on the sidewalls of each of the semiconductor pillars above the first insulating material layer; forming a conductor layer between the semiconductor pillars and on the first insulating material layer, the first conductor layer having an upper surface lower than the upper surface of the semiconductor pillars; forming a mask spacer on the sidewalls of each of the semiconductor pillars above the conductor layer; forming a mask layer comprising a plurality of linear patterns on the semiconductor substrate, wherein each of the linear patterns straddles the semiconductor pillars in the same row; and Using the mask spacer and the mask layer as a mask, etching the conductor layer to form a gate on the sidewall of each of the semiconductor columns, wherein the semiconductor columns on the same row The gates are connected by the conductor layer between semiconductor pillars in the same row to form a gate line. 33. The manufacturing method of the dynamic random access memory array as claimed in claim 32, further comprising forming a plurality of word lines on the substrate after forming the bit lines, wherein each of the word lines is formed alternately Above the bit lines and electrically connected to a corresponding gate line through at least one contact window, the contact window is located between the semiconductor pillars in the corresponding row. 34. The manufacturing method of a dynamic random access memory array as claimed in claim 33, wherein the step of forming the word lines comprises: forming a dielectric layer on the substrate and covering the bit lines; and forming at least one contact window through the dielectric layer and a word line on the dielectric layer, the word line is electrically connected to the gate line, wherein the contact window is connected to the two semiconductor pillars in the same row The conductor layers are in direct contact. 35. The method of manufacturing a dynamic random access memory array as claimed in claim 34, wherein: each of the bit lines has a capping layer formed thereon; and The method also includes: Before the dielectric layer is formed, a protective spacer is formed on each pair of bit lines and the sidewall of the cap layer. 36. The method of manufacturing a dynamic random access memory array as claimed in claim 34, wherein the contacts and the word lines are formed by a damascene process. 37. The manufacturing method of a dynamic random access memory array as claimed in claim 31, wherein on each of the memory cells, the first doped region of the sidewall of the semiconductor pillar is obtained from the second plate An upper portion is doped and diffused, wherein the upper portion of the second plate directly contacts the semiconductor pillar. 38. The method of manufacturing a dynamic random access memory array as claimed in claim 31, wherein each of the bit lines forms the second doped regions directly contacting the transistors in the same column. 39. The manufacturing method of a dynamic random access memory array as claimed in claim 38, wherein before each of the bit lines is formed, the gap between the semiconductor pillars is filled with a second insulating material layer, and covers the transistors. 40. The manufacturing method of a dynamic random access memory array as claimed in claim 23 , further comprising forming a plurality of word lines above the substrate after forming the bit lines, wherein each of the word lines is connected to The vertical transistors in the same row are coupled.

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