CN1767199A - Dynamic random access memory unit and its array, and Method of making the same - Google Patents
Dynamic random access memory unit and its array, and Method of making the same Download PDFInfo
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- CN1767199A CN1767199A CN200410089997.9A CN200410089997A CN1767199A CN 1767199 A CN1767199 A CN 1767199A CN 200410089997 A CN200410089997 A CN 200410089997A CN 1767199 A CN1767199 A CN 1767199A
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- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 238000000034 method Methods 0.000 claims abstract description 74
- 239000003990 capacitor Substances 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 177
- 239000004065 semiconductor Substances 0.000 claims description 143
- 239000004020 conductor Substances 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 40
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000002344 surface layer Substances 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000013461 design Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 2
- 239000012774 insulation material Substances 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 235000015250 liver sausages Nutrition 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000003973 irrigation Methods 0.000 description 9
- 230000002262 irrigation Effects 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000013517 stratification Methods 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910000413 arsenic oxide Inorganic materials 0.000 description 1
- 229960002594 arsenic trioxide Drugs 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- KTTMEOWBIWLMSE-UHFFFAOYSA-N diarsenic trioxide Chemical compound O1[As](O2)O[As]3O[As]1O[As]2O3 KTTMEOWBIWLMSE-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention relates to a dynamic random access memory unit and its array and the method for making the array. The dynamic random access memory unit comprises a semi-conducting column on the base, a capacitor on the side lower part of the semi-conducting column and a vertical crystal pipe on the side upper part of the semi-conducting column. The capacitor comprises: a first plate on the side lower part of the semi-conducting column, a second plate around the first pate as upper electrode, a third plate around the second pate and a dielectric layer which divides the second plate and the first and third plates. The third plate is connected with the first plate to form lower electrode. The invention also provides the method for making the dynamic random access memory unit and its array.
Description
Technical field
The present invention is relevant for a kind of semiconductor element, and particularly relevant for a kind of memory cell and array structure of dynamic random access memory, and the manufacture process of dynamic random access memory array.DRAM cell is a characteristic with the capacitor with high capacitance.
Background technology
In semi-conductor industry, dynamic random access memory is one of very important integrated circuit, so it has excited the research and development that continues.Increase storage volume, improve the speed that writes and read, and the element area size of minimizing DRAM cell is the target of present ongoing effort.In general, DRAM cell comprises transistor and the capacitor of being operated by transistor.Traditionally, the design of DRAM cell can be divided into three kinds of kenels, i.e. plane formula, stacked capacitor formula and ditching type.In the design of plane formula, the transistor of memory cell and capacitor form with the member manufacturing on plane.In the design of stacked capacitor formula, the capacitor of memory cell is placed in transistorized top.And in the design of ditching type, transistor is placed in the surface of substrate, and capacitor is seated in the irrigation canals and ditches that are formed in the substrate.
Yet, in the technology that forms irrigation canals and ditches, the very accurate aligning of the action need of mask.For the semiconductor element of deep-sub-micrometer, the ratio that deep trenches may have length and a diameter is 40: 1 a depth-width ratio.And the method that typically forms capacitor be earlier by dielectric layer in dark and narrow trench sidewall, fill up this irrigation canals and ditches with doped polysilicon layer again.Along with depth-width ratio becomes greatly gradually,, fill up irrigation canals and ditches and also become difficult more for example greater than 20: 1.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of DRAM cell exactly, and it has the capacitor on the sidewall of the semiconductor column of being formed at, solving existing problem of filling up irrigation canals and ditches, and the surface area that increases capacitor.
A further object of the present invention provides a kind of dynamic random access memory array based on DRAM cell structure of the present invention.Because form vertical transistor as memory cell, make dynamic random access memory array can have higher integrated level.
Another purpose of the present invention provides a kind of manufacture method of dynamic random access memory array, solving existing problem of filling up irrigation canals and ditches, and the electric capacity that increases capacitor, and increases the integration of dynamic random access memory.
DRAM cell of the present invention comprises that the lower sidewall of the semiconductor column that forms in the substrate, semiconductor column divides the capacitor that forms and the side wall upper part of semiconductor column to divide the vertical transistor that forms.Capacitor comprises first flat board, second flat board, the 3rd flat board and dielectric layer.Wherein, first flat panel configurations is in the lower part of the sidewall of semiconductor column, and second flat panel configurations and is used as top electrode around first flat board.The 3rd flat panel configurations and becomes bottom electrode with first dull and stereotyped the electrical connection around second flat board.Dielectric layer with second plate isolation in first dull and stereotyped and the 3rd flat board.Vertical transistor system arrives capacitor with electric property coupling.
According to a preferred embodiment of the invention, first flat board is electrically connected to each other by design with the 3rd flat board, and wherein first flat board more extends in the other substrate of semiconductor column, and the 3rd dull and stereotyped substrate with the semiconductor column side contacts.Yet first flat board also can be selected to be electrically connected by other the design that is connected with the 3rd flat board.
Dynamic random access memory array of the present invention comprises the row and the row of the memory cell that front of the present invention is mentioned, and many bit lines and character line.These memory cell arrangements and have above-mentioned identical structure on the semiconductor-based end.The vertical transistor electric property coupling of each a bar bit line and an array storage unit, and the vertical transistor electric property coupling of each a bar character line and a line storage unit.In addition, first flat board of all capacitors is connected to each other by the doped surface layer of the substrate between semiconductor column, so that first flat board and the 3rd flat board of all memory cell have constituted shared bottom electrode.
It below is the description of the manufacture method of DRAM cell of the present invention.The patterned semiconductor substrate is the semiconductor column that ranks are arranged to form thereon, follows the lower part formation capacitor at the sidewall of each semiconductor column, and it may further comprise the steps.At first, formation is used as first flat board of doped region in the lower part of the sidewall of each semiconductor column.Then, form first dielectric layer around each first flat board, and form second flat board around each first dielectric layer, and be used as top electrode.Then, form second dielectric layer around each second flat board, and form the 3rd flat board around each second dielectric layer, and be electrically connected corresponding first flat board to form bottom electrode.Afterwards, form vertical transistor, and electrically couple with corresponding capacitor in the top of the sidewall of each semiconductor column.Continue it, form many bit lines and character line, the transistor electric property coupling of each a bar bit line and an array storage unit wherein, and the transistor electric property coupling of each a bar character line and a line storage unit.
Because the formation of the capacitor in the dynamic random access memory of the present invention is around semiconductor column, rather than is formed in the deep trenches, so therefore the problem of filling up irrigation canals and ditches of deriving owing to the depth-width ratio of deep trenches solves in the prior art.Simultaneously, it is quite big that the surface area of capacitor and electric capacity become, because capacitor can form on all sidewalls of semiconductor column, and second flat board of being used as top electrode is bumped between first dull and stereotyped and the 3rd flat board, makes more doubly increase of electric capacity.
In addition, because the transistor of DRAM cell of the present invention forms with vertical stratification, therefore can reduce the shared side direction area of memory cell widely to increase the integrated level of dynamic random access memory array significantly.In other words, dynamic random access memory array can have higher integrated level.
Moreover because in the manufacture method of dynamic random access memory array of the present invention, the formation of capacitor is around semiconductor column, and therefore existing problem of filling up irrigation canals and ditches promptly is excluded.Therefore, the quality of access capacitor can be enhanced.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is to the manufacturing process schematic diagram of Figure 18 illustrate according to the dynamic random access memory array of the preferred embodiments of the present invention.Wherein, Fig. 1 is to the manufacture method of Fig. 7 illustrate into capacitor, and Fig. 8 is to the manufacture method of Figure 14 illustrate into vertical transistor, and Figure 15 is follow-up step to Figure 18 illustrate, comprises the manufacture method of bit line and character line.
Figure 17 and Figure 18 illustrate are according to the DRAM cell of the preferred embodiments of the present invention and the structure of array.
Description of reference numerals
100: the semiconductor-based end 102: pad oxide
104,136: patterned mask layer 110: semiconductor column
112,142,144: doped region 114: conformal dielectric layer
116,120,122,1264,132: conductor layer
118,124,1262,134,1462: clearance wall
118a, 128,130,138,148: insulating barrier
126: top electrode 1266: bottom electrode
127: capacitor 132a: grid
1361: pattern 140: ion is implanted
145: transistor 146: the bit line
1461: cap layer 150: the character line
152: contact hole
Embodiment
Fig. 1 clearly shows the perspective view of dynamic random access memory array, Fig. 2 to Figure 11, Figure 13 to Figure 15 and Figure 18 (a) then be the generalized section of the I-I ' line in Fig. 1, and Figure 18 (b) is another generalized section, and Figure 12, Figure 16 and Figure 17 are all top view.
More particularly, Fig. 1 is to the manufacturing process schematic diagram of Fig. 7 illustrate into the capacitor of formation dynamic random access memory array, Fig. 8 is to the transistorized manufacturing process schematic diagram of Figure 14 illustrate into the formation dynamic random access memory array, and Figure 15 is follow-up step to Figure 18 illustrate, comprises the manufacture method of bit line and character line.
The manufacture method of＜capacitor 〉
At first, please refer to Fig. 1, the semiconductor-based end 100 is provided, its material for example is a doped with P type monocrystalline silicon, and forms pad oxide 102 and patterned mask layer 104 in substrate 100.Wherein, this patterned mask layer 104 comprises rectangle or the square block that ranks are arranged, and the method for its formation for example is to apply a photo anti-corrosion agent material thereon to carry out etch process, and these patterned mask layer 104 materials for example are silicon nitride (SiN).Then, be mask with patterned mask layer 104, etching substrate 100 is to form the semiconductor column 110 that ranks are arranged.Be noted that in top view the shape of each block of patterned mask layer 104 can be for circular, oval and other polygons, even the patterned mask layer in top view 104 is rectangle or square.Certainly, in another embodiment, the shape of semiconductor column 110 can be modelled as cylindric, oval column or corresponding polygonal semiconductor column.
Moreover, be noted that especially for convenience's sake in the description of following specification, semiconductor column 110 and on partially patterned mask layer 104 be collectively referred to as semiconductor column 110 sometimes.
Referring again to Fig. 1, as the doped region 112 of the partial common bottom electrode of the holding capacitor that formed afterwards be the lower sidewall that is formed at each semiconductor column 110 divide and the superficial layer of substrate 100 in.In addition, the position the part doped region 112 of each semiconductor column 110 be in summary of the invention of the present invention mention as first flat board of capacitor.Simultaneously, between between the semiconductor column 110 and the doped region 112 of the part in substrate 100 be exactly in summary of the invention mention between the doped surface layer of the substrate 100 of 110 of semiconductor column.
The method of mixing for example comprises the following steps.At first, in 110 silicon oxide layers that contain arsenic doping (not illustrating) that form preset thickness of semiconductor column.Wherein, the method that formation contains the silicon oxide layer of arsenic doping for example has two, is respectively the mode of utilizing original position (in-situ), in substrate 100 in the cvd silicon oxide, arsenic doped is to fill up the gap of 110 of semiconductor column, and then this silicon oxide layer that contains arsenic doping of etch-back is up to the default degree of depth.Or form the lower part that the oxide layer contain arsenic doping covers the post sidewall, and by photoresist cover and etch back process to define the default degree of depth.Contain on the oxide layer of arsenic doping cover unadulterated oxide layer after, carry out the arsenic atomic heat that thermal process will contain in the arsenic oxide layer and become, and the superficial layer of substrate 100 into the contact surface layer of semiconductor column 110.Afterwards, remove oxide layer and the unadulterated oxide layer that contains arsenic doping.
Follow-up step is in the manufacture method of Fig. 2 complete narration capacitor in Fig. 7, and wherein Fig. 2 is a generalized section along the I-I ' line of Fig. 1 to Fig. 7.
At first, please refer to Fig. 2, form conformal dielectric layer 114 in substrate 100 and 110 of semiconductor column.Wherein, the material of this conformal dielectric layer 114 is silica-silicon-nitride and silicon oxide (ONO) or silicon-nitride and silicon oxide (NO) combination layer preferably, and is used as capacitor dielectric.Then, form conductor layer 116, and it has almost the degree of depth the same with doped region 112, or be lower than the degree of depth of doped region 112 110 of semiconductor column.Wherein, the material of conductor layer 116 is an electric conducting material, and as heavy doping N type polysilicon, and the method for its formation is as utilizing the mode of original position, also do simultaneously to mix to fill up the gap of 110 of semiconductor column prior to deposit spathic silicon layer in the substrate 100, then this polysilicon layer of etch-back is up to default thickness.
Afterwards, please refer to Fig. 3, remove the part conformal dielectric layer 114 that exposes, it can utilize wet etching process.And when the material of conformal dielectric layer 114 for example be when comprising the ONO combination layer of top oxide layer, silicon nitride layer and bottom oxide, can remove top oxide layer, silicon nitride layer and the bottom oxide that exposes respectively with diluted hydrofluoric acid, phosphoric acid and diluted hydrofluoric acid in regular turn.
Then, please refer to Fig. 4, the sidewall of each semiconductor column 110 on conductor layer 116 forms insulating gap wall 118.Wherein the material of insulating gap wall 118 comprises dielectric material such as silica, and the method for its formation for example is to carry out chemical vapor deposition method (Chemical Vapor Deposition CVD), and carries out anisotropic etching process subsequently.In addition, though be noted that demonstration insulating gap wall 118 is formed on the both sides of corresponding semiconductor column 110 in profile, in fact insulating gap wall 118 is to form around semiconductor column 110.Afterwards, 110 of semiconductor column on conductor layer 116 form another conductor layer 120 and cover the bottom of insulating gap wall 118.Wherein, the material of conductor layer 120 comprises electric conducting material, and as heavy doping N type polysilicon, and the method for its formation for example is to utilize the mode of original position, and prior to deposit spathic silicon layer in the substrate 100 and mix simultaneously, then this polysilicon layer of etch-back is up to the default degree of depth.
Then, please refer to Fig. 5, remove the SI semi-insulation clearance wall 118 that on each semiconductor column 110, is exposed, with formation neck insulating barrier 118a and around semiconductor column 110.Then, 110 of the semiconductor column on neck insulating barrier 118a and conductor layer 120 form another conductor layer 122.Wherein, the material of conductor layer 122 comprises electric conducting material such as heavy doping N type polysilicon, and the method for its formation is to use above-mentioned sedimentation and the etch-back method of being same as.Afterwards, the sidewall of each semiconductor column 110 on conductor layer 122 forms mask clearance wall 124, and its thickness is greater than neck insulation 118a.In addition, mask clearance wall 124 is the top electrodes that are used for defining capacitor, and it is described in detail as follows.
Afterwards, please be used as mask with mask clearance wall 124 simultaneously with reference to Fig. 5 and Fig. 6, above-mentioned three layers of conductor layer 122,120,116 of etching in succession are to form top electrode 126 on the lower wall of each semiconductor column 110.Be noted that remaining conductor layer 122, promptly the top of top electrode 126 directly contacts with the sidewall of semiconductor column 110.Afterwards, on the sidewall of mask clearance wall 124 and conductor layer 122,120,116, form dielectric gap wall 1262.Wherein, this dielectric gap wall 1262 may be the combinational gap wall of silicon nitride and silica (NO), and the method for its formation is to form silicon nitride layer and silicon oxide layer in regular turn, carries out anisotropic etching then to remove part silicon nitride layer and silicon oxide layer.
Then, please refer to Fig. 7, remove the dielectric layer 114 that exposes, then form conductor layer 1264 and be filled in gap in the post, and contact with the part doped region 112 of substrate 100 in post with part.Therefore, whole doped region 112 and conductor layer 1264 together constitute shared bottom electrode 1266.Simultaneously, description is arranged in summary of the invention, be used as first dull and stereotyped and the 3rd flat board respectively with the doped region 112 of semiconductor column 110 corresponding parts and the conductor layer 1264 of part.
Wherein, the formation method of conductor layer 1264 for example is to form conductor material (not illustrating) earlier to fill up the gap in the post, electric conducting material is eat-back up to the default degree of depth, and its material may be doped polycrystalline silicon.In addition, top electrode 126, two layers of dielectric layer 114,1262 and shared bottom electrode 1266 together constitute capacitor 127.Because capacitor 127 is formed on all sidewalls of semiconductor column 110, and top electrode 126 embeds between two parts of bottom electrodes 1266, and wherein these two parts are doped region 112 and conductor layer 1264, therefore, and suitable big of the electric capacity of capacitor 127.
In addition, in the formation method of above-mentioned capacitor around each semiconductor column, for example on the manufacturing sequence of the manufacture method of material, each layer and these layers, a little retouching or change are arranged, also all may be within the scope of the present invention.
＜transistorized manufacture method 〉
Next please refer to Fig. 8, remove the top of mask clearance wall 124 and dielectric layer 1262, then in semiconductor column 110, insert insulating barrier 128 to cover all capacitors 127.Wherein, the material of insulating barrier 128 comprises dielectric material, and as silica, and the method for its formation for example is first cvd silicon oxide in substrate 100, carries out etch-back then equally up to the default degree of depth.Afterwards, please refer to Fig. 9, on the sidewall that each semiconductor column 110 is exposed, form gate insulation layer 130.Wherein, this gate insulation layer 130 for example is one deck thin silicon oxide layer or the thin silicon oxide/nitride layer of one deck, and the method for its formation may be to utilize thermal oxidation technology or thermal oxidation nitriding process.
Then, 110 of the semiconductor column on insulating barrier 128 form conductor layer 132, and the lower part of covering gate insulating barrier 130.Wherein, the material of conductor layer 132 comprises electric conducting material, and as heavy doping N type polysilicon, and the method for its formation for example is to utilize the mode of original position, add N type dopant in substrate 100 in the deposit spathic silicon layer, this polysilicon layer of etch-back is up to the default degree of depth afterwards.
Afterwards, please refer to Figure 10, on the sidewall of each semiconductor column 110 on the conductor layer 132, form mask clearance wall 134.Wherein, this mask clearance wall 134 was as defining grid usefulness afterwards, and it is formed by insulating material, and wherein this insulating material for example is a silica.
Then, please be simultaneously with reference to Figure 11 and Figure 12, wherein, Figure 12 is the top view of the structure after following step is finished, and Figure 11 is the generalized section along the XI-XI ' line of Figure 12.Forming patterned mask layer 136 in substrate 100, for example is patterning photoresist layer.And this patterned mask layer 136 comprises some parallel and linear patterns 1361, and wherein, each linear pattern 1361 covers with the semiconductor column 110 of delegation and at the segment conductor layer 132 with 110 of the semiconductor column of delegation.Afterwards, be mask etching conductor layer 132 with patterned mask layer 136 with mask clearance wall 134, form grid 132a with sidewall in each semiconductor column 110.Even the problem of aligning takes place not have patterned mask layer 136, mask clearance wall 134 also can make corresponding grid 132a around its corresponding semiconductor column 110.
By conductor layer remaining in the semiconductor column with delegation 132, be connected grid 132a on the sidewall of colleague's semiconductor column 110 to form gate line 132a (dotted region among the figure), it can directly be referred to as the character line.Yet, can on gate line 132a, form another low-resistance conductor lines again, and be electrically connected to reduce resistance with gate line 132a, it is described as follows.
In addition, in the formation method of above-mentioned grid around each semiconductor column, for example on the manufacturing sequence of the manufacture method of material, each layer and these layers, a little retouching or change are arranged, also all may be within the scope of the present invention.
The manufacture method of＜source/drain 〉
At first, please refer to Figure 13, fill up the space of 110 of semiconductor column with insulating barrier 138, and the material of this insulating barrier 138 is an insulating material, as silica, and the method for its formation for example be carry out the plasma enhanced chemical vapor deposition method (Plasma Enhanced CVD, PECVD), and then carry out chemical mechanical milling method (chemical mechanical polishing, CMP).
Afterwards, please refer to Figure 14, remove patterned mask layer 104, pad oxide 102, part mask clearance wall 134 and partial insulative layer 138.Wherein, the method that removes four above-mentioned parts for example is to carry out chemical mechanical milling method, makes the upper surface of mask clearance wall 134 and insulating barrier 138 and those semiconductor column 110 copline substantially.Then, carry out ion and implant 140 and form doped region 142, with as source/drain regions with top in each semiconductor column 110.Wherein, doped region 142 may be to be the N type heavily doped region of dopant with phosphonium ion or arsenic ion.
Then, carry out high-temperature tempering process and implant 140 pairs of lattices that semiconductor column 110 is damaged, and some dopants of bottom electrode 126 are become into the sidewall of each semiconductor column 110, to form doped region 144 to repair by ion.Two doped regions 142 and 144, grid 132a and gate insulation layer 130 together constitute vertical transistor 145.Though be noted that in doped region 144 diagram formerly not illustrate, in fact during the top 122 of bottom electrode 126 forms each thermal process of back (as shown in Figure 5), more or less all doped region 144 can occur.Yet in a preferred embodiment, doped region 144 mainly appears at during the high-temperature tempering process after doped region 142 forms.
The manufacture method of＜bit line and character line 〉
Figure 15 and Figure 16 illustrate the step of the bit line that forms memory array, and wherein, Figure 16 is the top view of the structure after following step is finished, and Figure 15 is the generalized section along the XV-XV ' line of Figure 16.After the structure of vertical transistor 145 is finished, in substrate 100, form many bit lines 146.Each bar bit line 146 directly contacts with these doped regions 142 on the top of the semiconductor column 110 of same row.Wherein, the material of bit line 146 is an electric conducting material, and as heavy doping N type polysilicon, and its formation method is to use deposit patterned method (deposition-patterning) or mosaic technology (damascene method).
In addition, cap layer 1461 is configured on each bar bit line 146, and supposes that bit line 146 and cap layer 1461 are formed with the deposit patterned method, then protects clearance wall 1462 will be formed on each sidewall to bit line and cap layer.Wherein, the material of formation cap layer 1461 and protection clearance wall 1462 is silicon nitride preferably, and its purposes is in case stop bit unit line 146 is exposed out in the etch process of follow-up contact hole, so that contact hole forms with the method for aiming at voluntarily.Afterwards, in substrate 100, form insulating barrier 148, and fill up the gap between per two bit lines 146, bit line 146 and the character line that forms in next procedure are isolated with covering bit line 146.
Figure 17 and Figure 18 (a) and (b) illustrate the step of the extra character line that forms memory array are to be electrically connected previous formed gate line.Figure 17 is the top view of the structure after following step is finished, and Figure 18 (a) and Figure 18 (b) are respectively the generalized sections along A-A ' line and the B-B ' line of Figure 17.After insulating barrier 148 forms, in substrate 100, form many character lines 150.Each bar character line 150 is electrically connected with gate line in the delegation on the sidewall of semiconductor column 110, and it is to see through at least one contact hole 152 between two semiconductor column 110.In addition, contact hole 152 directly contacts with conductor layer 132, and this conductor layer 132 is connected with two grid 132a on the sidewall of two adjacent semiconductor column 110 of delegation.
Contact hole 152 for example is to form contact window earlier in insulating barrier 148 with the formation method of character line 150, to expose segment conductor layer 132, deposits another conductor layer then covering insulating barrier 148, and fills up this and connect the window opening, then this conductor layer of patterning.Or utilize mosaic technology to form contact hole 152 and character line 150.
In addition, according to the preferred embodiments of the present invention, Figure 17 and Figure 18 (a) and the structure of DRAM cell and array (b) also is described.Therefore, the structure of DRAM cell and array can be understood according to the detailed description of above-mentioned preferred embodiment.
Please refer to Figure 17 and Figure 18 (a) and (b), because the capacitor 127 in DRAM cell of the present invention is to form around semiconductor column 110, rather than be formed in the deep trenches, so therefore the problem of filling up irrigation canals and ditches of deriving because of the depth-width ratio of deep trenches does not exist in the prior art.Simultaneously, it is quite big that the surface area of capacitor 127 and electric capacity become, because capacitor 127 can form on all sidewalls of semiconductor column 110, and top electrode 126 is to embed between two parts 112 and 1164 of bottom electrode 1266, makes more doubly increase of electric capacity.
In addition, because the transistor of DRAM cell of the present invention 145 forms with vertical stratification, therefore can reduce the size of each memory cell widely, to improve the integrated level of memory array significantly.
Though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be with being as the criterion that claims were defined.
Claims (40)
1. DRAM cell comprises:
The semiconductor post is positioned in the substrate;
One capacitor is positioned at the lower part of a sidewall of this semiconductor column, comprising:
One first flat board is arranged in the lower part of this sidewall of this semiconductor column;
One second flat board, be positioned at this first dull and stereotyped around with as a top electrode;
One the 3rd flat board is positioned at around this second flat board, and with this first dull and stereotyped electrical connection with together as a bottom electrode; And
One dielectric layer makes this second dull and stereotyped and this first dull and stereotyped and the 3rd plate isolation; And
One vertical transistor is positioned at the top of this sidewall of this semiconductor column and this capacitor of electric property coupling.
2. DRAM cell as claimed in claim 1, wherein:
This first dull and stereotyped design by one with the 3rd flat board is electrically connected, and wherein this first flat board more extends to this other substrate of this semiconductor column, and the 3rd dull and stereotyped this substrate with this semiconductor column side contacts; And
This dielectric layer also is disposed on this first flat board of part in this other substrate of this semiconductor column, so that a bottom of this second flat board and this first plate isolation.
3. DRAM cell as claimed in claim 2, wherein this dielectric layer comprises:
One first dielectric layer, between this semiconductor column and this second flat board, and between this substrate and this second flat board; And
One second dielectric layer between this second flat board and the 3rd flat board, and connects this first dielectric layer.
4. DRAM cell as claimed in claim 1, wherein this second flat board has the source that a top directly contacts this vertical transistor in this semiconductor column.
5. DRAM cell as claimed in claim 1, wherein this first flat board, this second flat board, the 3rd flat board and this dielectric layer are around this semiconductor column.
6. DRAM cell as claimed in claim 5, wherein this capacitor also comprises a neck insulating barrier around this semiconductor column, and covers by the top of this second flat board.
7. DRAM cell as claimed in claim 6, wherein this second flat board comprises:
One first conductor layer is around this neck insulating barrier;
One second conductor layer is positioned at this first conductor layer and this neck insulating barrier below; And
One the 3rd conductor layer is positioned on this first conductor layer and this neck insulating barrier, and this vertical transistor of electric property coupling.
8. DRAM cell as claimed in claim 1, wherein this vertical transistor comprises:
One first doped region is arranged in the sidewall of this semiconductor column, and is electrically connected the top electrode of this capacitor;
One second doped region is arranged in the top of this semiconductor column;
One grid is on the sidewall of this semiconductor column between this first doped region and this second doped region; And
One gate insulation layer is between the sidewall and this grid of this semiconductor column.
9. DRAM cell as claimed in claim 8, wherein an insulating barrier on the top of this grid and this top electrode is isolated.
10. DRAM cell as claimed in claim 8, wherein this first doped region, this grid and this gate insulation layer are around this semiconductor column.
11. a dynamic random access memory array comprises:
A plurality of memory cell arrangements that line up rows and columns are in a substrate, and each those memory cell comprises:
The semiconductor post is positioned in this substrate;
One capacitor, be positioned at the lower part of a sidewall of this semiconductor column, comprise that one first flat board is arranged in the lower part of this sidewall of this semiconductor column, one second flat board is electrically connected together to make this second flat board and this first flat board and the 3rd flat plate separation as a bottom electrode and a dielectric layer to be positioned at this second flat board as a top electrode, one the 3rd flat board around being positioned at this first flat board on every side and with this first flat board;
One vertical transistor is positioned at the top of this sidewall of this semiconductor column and this capacitor of electric property coupling;
Many bit lines, each those bit line couple those vertical transistors in the row; And
Many character lines, each those character line couples those vertical transistors in the delegation.
12. dynamic random access memory array as claimed in claim 11, wherein:
Those first flat boards are electrically connected to each other by a doped surface layer of this substrate between those semiconductor column;
Those the 3rd flat boards together constitute a conductor layer, and the gap that this conductor layer is partly inserted between those semiconductor column contacts with this doped surface layer of this substrate; And
Those first flat boards, this doped surface layer with this conductor layer as a shared bottom electrode.
13. dynamic random access memory array as claimed in claim 12, wherein in each those memory cell, this dielectric layer comprises:
One first dielectric layer, between this second flat board and this semiconductor column, and between this doped surface layer of this second flat board and this substrate; And
One second dielectric layer between this second flat board and the 3rd flat board, and connects this first dielectric layer.
14. dynamic random access memory array as claimed in claim 11, wherein each those second flat board has the directly source of contact one corresponding vertical transistor of a top.
15. dynamic random access memory array as claimed in claim 11, wherein in each those capacitor, this first flat board, this second flat board, this dielectric layer and the 3rd flat board are around this semiconductor column.
16. dynamic random access memory array as claimed in claim 15, wherein each those capacitor also comprises a neck insulating barrier around this corresponding semiconductor column, and covers by the top of this second flat board.
17. dynamic random access memory array as claimed in claim 16, wherein this second flat board comprises:
One first conductor layer is around this neck insulating barrier;
One second conductor layer is positioned at this first conductor layer and this neck insulating barrier below; And
One the 3rd conductor layer is positioned on this first conductor layer and this neck insulating barrier, and electric property coupling one corresponding vertical transistor.
18. dynamic random access memory array as claimed in claim 11, wherein each those vertical transistor comprises:
One first doped region is arranged in the sidewall of a corresponding semiconductor column, and is electrically connected the top electrode of a corresponding capacitor;
One second doped region is arranged in the top of this semiconductor column;
One grid is on the sidewall of this semiconductor column between this first doped region and this second doped region; And
One gate insulation layer is between the sidewall and this grid of this semiconductor column.
19. dynamic random access memory array as claimed in claim 18, wherein each those bit line directly contacts with those second doped regions at those vertical transistors of those memory cell of same row.
20. dynamic random access memory array as claimed in claim 18 wherein is connected to each other to form a gate line at those grids with those memory cell of delegation.
21. dynamic random access memory array as claimed in claim 20, wherein this gate line is directly as a character line of those vertical transistors of this row.
22. dynamic random access memory array as claimed in claim 20, wherein a character line is electrically connected with this gate line by the contact hole between two those semiconductor column at least.
23. the manufacture method of a dynamic random access memory array comprises:
The substrate of patterning semiconductor is to be formed with a plurality of semiconductor column that line up rows and columns on this semiconductor-based end;
Form a capacitor on the lower part of a sidewall of each those semiconductor column, comprising:
Form one first flat board in the lower part of this sidewall of each those semiconductor column;
Form one first dielectric layer in each around those first flat boards;
Form one second flat board in each around those first dielectric layers, to be used as a top electrode;
Form one second dielectric layer in each around those second flat boards; And
Form one the 3rd flat board in each around those second dielectric layers, wherein the 3rd dull and stereotyped corresponding first flat board that is electrically connected is to form a bottom electrode;
Form the top of a vertical transistor, and this vertical transistor and a corresponding capacitor couple in a sidewall of each those semiconductor column; And
Form many bit lines on this semiconductor-based end, wherein each those bit line couples those vertical transistors of row.
24. the manufacture method of dynamic random access memory array as claimed in claim 23, wherein a doped surface layer of those this substrates of first flat board between those semiconductor column forms, so that all those first flat boards are electrically connected to each other.
25. comprising, the manufacture method of dynamic random access memory array as claimed in claim 24, the step that wherein forms this first dielectric layer form a conformal dielectric layer on the sidewall of this doped surface layer of this substrate and each those semiconductor column.
26. the manufacture method of dynamic random access memory array as claimed in claim 25, the step that wherein forms those the 3rd flat boards comprises:
Remove this second dull and stereotyped this first dielectric layer that is exposed with this second dielectric layer, to expose this doped surface layer of part between those semiconductor column; And
Form a conductor layer and partly insert gap between those semiconductor column, to be used as those the 3rd flat boards of all capacitors.
27. the manufacture method of dynamic random access memory array as claimed in claim 25, the step that wherein forms this second flat board comprises:
Form at least one conductor layer and partly insert gap between those semiconductor column;
Form a clearance wall on the sidewall of each those semiconductor column; And
With those clearance walls is mask, those second dull and stereotyped these interior conductor layers of etching.
28. the manufacture method of dynamic random access memory array as claimed in claim 27, the step that wherein forms those second dielectric layers and those the 3rd flat boards comprises:
Form a dielectric gap wall on the sidewall and corresponding this second flat board of each those clearance wall, wherein the lower part of this dielectric gap wall is as this second dielectric layer;
With this clearance wall and this dielectric gap wall is etching mask, to remove this first dielectric layer that exposes;
Form one second conductor layer and partly insert gap between those semiconductor column, to be used as those the 3rd flat boards of all capacitors; And
Remove the top of each this clearance wall and each this dielectric gap wall.
29. the manufacture method of dynamic random access memory array as claimed in claim 27, the step that wherein forms at least one conductor layer comprises:
Form one first conductor layer and partly insert gap between those semiconductor column;
Remove this conformal dielectric layer of part that this first conductor layer is exposed;
Form the sidewall of those semiconductor column of an insulating gap wall on first conductor layer;
Form one second conductor layer between those semiconductor column to cover the lower part of those insulating gap walls;
Remove the part of each this insulating gap wall that this second conductor layer exposed, to form a neck insulating barrier on each those semiconductor column; And
Form one the 3rd conductor layer between those semiconductor column and on this neck insulating barrier and this second conductor layer.
30. the manufacture method of dynamic random access memory array as claimed in claim 23, wherein in each those memory cell, a top of this second flat board directly contacts this semiconductor column.
31. the manufacture method of dynamic random access memory array as claimed in claim 23, the step that wherein forms those vertical transistors comprises:
Insert gap between those semiconductor column with one first insulating material layer segment, to cover those capacitors;
Form the sidewall of each those semiconductor column of a grid structure on this first insulating barrier of a vertical transistor, and this grid structure comprises a gate electrode and the gate insulation layer between this semiconductor column and this gate electrode;
One first doped region that forms a vertical transistor is in the sidewall of each those semiconductor column, and this first doped region couples this capacitor on the sidewall of this identical semiconductor column; And
One second doped region that forms a vertical transistor is in the top of each those semiconductor column.
32. the manufacture method of dynamic random access memory array as claimed in claim 31, the step that wherein forms this grid structure comprises:
Form the sidewall of a gate insulator in each those semiconductor column of this first insulation material layer top;
Form a conductor layer between those semiconductor column with this first insulation material layer on, this first conductor layer has the upper surface that a upper surface is lower than those semiconductor column;
Form the sidewall of a mask clearance wall in each those semiconductor column of this conductor layer top;
Form a mask layer, this mask layer is included in the suprabasil a plurality of linearity patterns of this semiconductor, and wherein each those linearity pattern strides across in those semiconductor column with delegation; And
With this mask clearance wall and this mask layer as a mask, this conductor layer of etching, to form a grid on the sidewall of each those semiconductor column, wherein connecting to form a gate line by this conductor layer between the semiconductor column of going together mutually with those grids on those semiconductor column of delegation.
33. the manufacture method of dynamic random access memory array as claimed in claim 32, also be included in and form after those bit lines, form many character lines in the substrate top, wherein each those character line is staggered to form in those bit line tops, and being electrically connected a corresponding gate line by at least one contact hole, this contact hole is positioned between those semiconductor column of this corresponding row.
34. the manufacture method of dynamic random access memory array as claimed in claim 33, the step that wherein forms those character lines comprises:
Form a dielectric layer in this substrate, and cover those bit lines; And
Form the contact hole at least always wear this dielectric layer and a character line that is positioned on this dielectric layer, this character line is electrically connected this gate line, and wherein this contact hole directly contacts with this conductor layer in two those semiconductor column of going together mutually.
35. the manufacture method of dynamic random access memory array as claimed in claim 34, wherein:
Each those bit line has a cap layer formed thereon; And
This method also comprises:
Before this dielectric layer forms, form a protection clearance wall in each to bit line and this cap layer sidewall.
36. the manufacture method of dynamic random access memory array as claimed in claim 34, wherein this contact hole and this character line utilize a mosaic technology to form.
37. the manufacture method of dynamic random access memory array as claimed in claim 31, wherein on each those memory cell, this first doped region of the sidewall of this semiconductor column forms by the diffusion of mixing from a top of this second flat board, and wherein this top of this second flat board directly contacts this semiconductor column.
38. the manufacture method of dynamic random access memory array as claimed in claim 31, wherein each those bit line forms those transistorized those second doped regions that are in direct contact with same row.
39. the manufacture method of dynamic random access memory array as claimed in claim 38, wherein before each those bit line formed, the gap between those semiconductor column was filled up with one second insulation material layer, and covers those transistors.
40. the manufacture method of dynamic random access memory array as claimed in claim 23 also is included in and forms after those bit lines, forms many character lines in this substrate top, wherein each those character line and couple with those vertical transistors of delegation.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100899979A CN100373623C (en) | 2004-10-28 | 2004-10-28 | Dynamic random access memory unit and its array, and method of making the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100899979A CN100373623C (en) | 2004-10-28 | 2004-10-28 | Dynamic random access memory unit and its array, and method of making the same |
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| CN1767199A true CN1767199A (en) | 2006-05-03 |
| CN100373623C CN100373623C (en) | 2008-03-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992175A (en) * | 2017-03-29 | 2017-07-28 | 合肥智聚集成电路有限公司 | Semiconductor storage unit and preparation method thereof |
| CN107025938A (en) * | 2016-02-01 | 2017-08-08 | 株式会社东芝 | Storage arrangement |
| WO2023245804A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, and memory |
| WO2023245711A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, and memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0917203A3 (en) * | 1997-11-14 | 2003-02-05 | Infineon Technologies AG | Gain cell DRAM structure and method of producing the same |
| DE19944012B4 (en) * | 1999-09-14 | 2007-07-19 | Infineon Technologies Ag | Trench capacitor with capacitor electrodes and corresponding manufacturing process |
| US7026209B2 (en) * | 2002-08-02 | 2006-04-11 | Promos Technologies Inc. | Dynamic random access memory cell and fabrication thereof |
-
2004
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107025938A (en) * | 2016-02-01 | 2017-08-08 | 株式会社东芝 | Storage arrangement |
| CN106992175A (en) * | 2017-03-29 | 2017-07-28 | 合肥智聚集成电路有限公司 | Semiconductor storage unit and preparation method thereof |
| WO2023245804A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, and memory |
| WO2023245711A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, and memory |
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| CN100373623C (en) | 2008-03-05 |
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