CN113497006A - Capacitor structure and forming method thereof - Google Patents

Capacitor structure and forming method thereof Download PDF

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Publication number
CN113497006A
CN113497006A CN202010202321.5A CN202010202321A CN113497006A CN 113497006 A CN113497006 A CN 113497006A CN 202010202321 A CN202010202321 A CN 202010202321A CN 113497006 A CN113497006 A CN 113497006A
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layer
semiconductor substrate
electrode layer
dielectric
forming
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王锦喆
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application provides a capacitor structure and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor substrate; forming a groove in the semiconductor substrate, wherein the groove is provided with a plurality of discrete columnar structures formed by partial semiconductor substrate, and the columnar structures are distributed in an array manner; forming a first electrode layer on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and the sidewall surface and the top surface of the columnar structure; forming a dielectric layer on the surface of the first electrode layer; and forming a second electrode layer on the surface of the dielectric layer, wherein the second electrode layer fills the groove around the columnar structure. The method improves the electrostatic capacity and breakdown voltage resistance of the capacitor structure, and realizes the manufacture of the high-density silicon capacitor.

Description

Capacitor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a capacitor structure and a method for forming the same.
Background
The temperature coefficient of the positive capacitance of the common capacitor in the integrated circuit is small, and the common capacitor can be used as a bypass or a DC blocking in a high-stability oscillation loop. And on the occasion of higher requirements on stability and loss, the capacitance of a common capacitor is smaller, the small-size machining performance is poorer, and the common capacitor is easy to be broken down by pulse voltage when being used in a high-pulse circuit. Therefore, the silicon-based capacitor is developed, a more general semiconductor processing technology can be adopted, a smaller size and a larger electrode structure surface area can be manufactured, and higher capacitance density and charging and discharging speed can be obtained.
At present, in order to obtain larger electrode structure surface area and capacitance density, a trench structure is generally used for depositing a silicon inner electrode, a dielectric layer and a metal layer serving as an outer electrode in the trench, but when the trench is expanded to a deeper direction, the process cannot etch a silicon-based profile with an ideal structure and enough space to form a good trench in a deposition layer so as to obtain accurate and stable capacitance performance; in addition, the two electrodes in the trench occupy more space of the dielectric layer, so that more charge storage capacity cannot be obtained; if the width of the trench is widened, the density of the unit trench is reduced, and a better deep trench process expansion effect cannot be obtained.
Therefore, it is necessary to develop a new capacitor structure and a method for forming the same to increase the surface area of the capacitor and to improve the capacitance per unit area of the substrate, the breakdown voltage resistance, and the like.
Disclosure of Invention
The application provides a capacitor structure and a forming method thereof, which are used for improving the performance of the capacitor structure.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a groove in the semiconductor substrate, wherein the groove is provided with a plurality of discrete columnar structures formed by partial semiconductor substrate, and the columnar structures are distributed in an array manner; forming a first electrode layer on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and the sidewall surface and the top surface of the columnar structure; forming a dielectric layer on the surface of the first electrode layer; and forming a second electrode layer on the surface of the dielectric layer, wherein the second electrode layer fills the groove around the columnar structure.
Optionally, the shape of the columnar structure comprises a cylinder.
Optionally, in the plurality of columnar structures distributed in an array, two adjacent rows of columnar structures are staggered.
Optionally, the first electrode layer is located on the top surface of the semiconductor substrate, in the partial semiconductor substrate at the side wall and the bottom of the trench, and in the side wall region and the top region in the columnar structure, or the first electrode layer is located on the top surface of the semiconductor substrate, in the partial semiconductor substrate at the side wall and the bottom of the trench, and in the entire region in the columnar structure.
Optionally, the first electrode layer is formed by a solid source diffusion process.
Optionally, the method for forming the first electrode layer by using a solid-state source diffusion process includes forming a doping source layer on the surface of the semiconductor substrate, the surface of the trench, and the surfaces of the plurality of columnar structures, where the doping source layer has diffusion ions; forming a covering layer on the surface of the doping source layer; after the covering layer is formed, carrying out thermal driving treatment, and enabling diffused ions in the doping source layer to be diffused into the top surface of the semiconductor substrate, the partial semiconductor substrate on the side wall and the bottom of the groove and the columnar structure to form a first electrode layer; and removing the covering layer and the doping source layer after the thermal driving treatment is carried out.
Optionally, the material of the doping source layer comprises silicon oxide doped with phosphorus, and the diffusing ions comprise phosphorus.
Optionally, the thickness of the doping source layer is 60 nm to 100 nm; the dopant source layer has a concentration of diffusing ions in the range of 15% to 25% prior to the thermal drive process.
Optionally, the material of the cover layer comprises silicon oxide; the thickness of the covering layer is 150 nm to 250 nm.
Optionally, the method for forming the first electrode layer includes: performing ion implantation on the top surface of the semiconductor substrate, partial semiconductor substrate at the side wall and the bottom of the groove and the side wall area and the top area in the columnar structure; after the ion implantation, annealing treatment is performed.
Optionally, the process of forming the first electrode layer includes a deposition process; the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.
Optionally, the method for forming the dielectric layer on the surface of the first electrode includes an atomic layer deposition process.
Optionally, the dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multilayer stack structure; the dielectric layer comprises a first dielectric sublayer and a second dielectric sublayer located on the first dielectric sublayer; the material of the first dielectric sublayer comprises silicon oxide, and the material of the second dielectric sublayer comprises silicon nitride.
The present invention also provides a capacitor structure comprising: the semiconductor substrate is provided with a groove, the groove is provided with a plurality of discrete columnar structures formed by partial semiconductor substrates, and the columnar structures are distributed in an array manner; a first electrode layer on a top surface of the semiconductor substrate, sidewall surfaces and a bottom surface of the trench, and sidewall surfaces and a top surface of the columnar structure; the dielectric layer is positioned on the surface of the first electrode layer; and the second electrode layer is positioned on the surface of the dielectric layer, and the groove around the columnar structure is filled with the second electrode layer.
Optionally, the plurality of columnar structures are cylinders.
Optionally, the diameter of each of the pillar structures is 0.2 to 0.8 micrometers, and the height of the pillar structure is 20 to 50 micrometers.
Optionally, in the plurality of columnar structures distributed in an array, two adjacent rows of columnar structures are staggered.
Optionally, the first electrode layer is located on the top surface of the semiconductor substrate, in the partial semiconductor substrate at the side wall and the bottom of the trench, and in the side wall region and the top region in the columnar structure, or the first electrode layer is located on the top surface of the semiconductor substrate, in the partial semiconductor substrate at the side wall and the bottom of the trench, and in the entire region in the columnar structure.
Optionally, the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.
Optionally, the dielectric layer is a single-layer structure, and the material of the dielectric layer includes silicon oxide or silicon nitride; or, the dielectric layer is a multilayer stack structure; the dielectric layer comprises a first dielectric sublayer and a second dielectric sublayer located on the first dielectric sublayer; the material of the first dielectric sublayer comprises silicon oxide, and the material of the second dielectric sublayer comprises silicon nitride.
Advantageous effects
In the method for forming the capacitor structure provided by the technical method, the groove is formed in the semiconductor substrate, the groove is internally provided with a plurality of discrete columnar structures formed by partial semiconductor substrates, and the columnar structures are distributed in an array form, so that the opening rate of the groove is higher, and secondly, the opening rate of the groove is higher, so that a deeper groove is favorably formed, and the larger side wall area and the larger bottom area of the groove are extended. And the first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and also along the sidewall surface and the top surface of the columnar structure, thereby increasing the effective area of the first electrode layer. And forming a dielectric layer on the surface of the first electrode layer, wherein the dielectric layer is formed along the surface of the first electrode layer, so that the effective area of the first electrode layer is increased. Accordingly, the area of the side of the second electrode layer opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer form a capacitor structure. Therefore, the effective area of the second electrode layer, the dielectric layer and the first electrode layer in the unit area of the substrate is increased, so that the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are improved, and the high-density silicon capacitor is manufactured. In conclusion, the performance of the capacitor structure is improved.
Further, the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the sidewall region and the top region in the columnar structure, or the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the entire region in the columnar structure. That is, the first electrode layer does not occupy the space of the trench, so that the dielectric layer and the second electrode layer have more filling space, which is beneficial to increasing the thickness of the dielectric layer. This results in an improved breakdown voltage resistance of the capacitor structure. And secondly, the first electrode layer does not occupy the space of the groove, and is positioned in the partial semiconductor substrate at the side wall and the bottom of the groove and in the columnar structure, so that the contact effective area of the first electrode layer and the dielectric layer is further improved, and the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are further improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 8 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Referring to fig. 1, wherein fig. 1(a) is a top view of the semiconductor substrate; fig. 1(b) is a cross-sectional view of the semiconductor substrate. Providing a semiconductor substrate 100; a trench 110 is formed in the semiconductor substrate 100, and a plurality of discrete pillar structures 120 formed by a part of the semiconductor substrate 100 are formed in the trench 110, and the plurality of pillar structures 120 are distributed in an array.
The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.
In some embodiments of the present application, the semiconductor substrate 100 is a P-type substrate, and the surface of the P-type substrate may be doped with impurity ions by an N-type ion diffusion process in a subsequent process to form a first electrode layer. In other embodiments of the present application, the semiconductor substrate 100 is an N-type substrate, and the first electrode layer may be formed by doping impurity ions on the surface of the N-type substrate through a P-type ion diffusion process in a subsequent process.
In some embodiments of the present application, a method of forming the trench 110 includes: forming a patterned mask layer on the semiconductor substrate 100, the patterned mask layer being used to define the position of the trench 110; etching the semiconductor substrate 100 by using the patterned mask layer as a mask and adopting an anisotropic dry etching process to form the trench 110; after the semiconductor substrate 100 is etched by using an anisotropic dry etching process, the patterned mask layer is removed.
After the semiconductor substrate 100 is etched by using the anisotropic dry etching process and before the patterned mask layer is removed, the inner wall of the trench 110 and the surface of the columnar structure 120 may be heat-treated by using nitrogen gas to repair etching damage. In the process of performing the heat treatment on the inner wall of the trench 110 and the surface of the columnar structure 120, the temperature of the heat treatment is 800 to 1200 degrees celsius, such as 900 degrees celsius, 1000 degrees celsius, or 1100 degrees celsius, and the time of the heat treatment is 25 to 40 minutes, such as 25 minutes, 30 minutes, 35 minutes, or 40 minutes.
In some embodiments of the present application, the patterned mask layer is removed by a wet etching process, and the surface of the trench and the surface of the columnar structure are cleaned during the removal of the patterned mask layer.
In some embodiments of the present application, the number of columnar structures 120 are cylinders. Referring to fig. 1(a), in the case that the number of the pillar structures 120 is the same, the use of the pillar structures can maximize the distance between the adjacent pillar structures 120, accommodate more dielectric layers, and increase the capacitance.
In some embodiments of the present application, the diameter of the plurality of pillar structures 120 is 0.2 microns to 0.8 microns, such as 0.2 microns, 0.4 microns, 0.6 microns, or 0.8 microns, and the like. The smaller the diameter of the columnar structure 120 is, the larger the number of the columnar structures 120 that can be formed in the semiconductor substrate 110 is, the larger the surface area of the capacitor is, the higher the capacitance is, but on the one hand, the too small diameter causes the volume of the first electrode in the columnar structure 120 to be too small, which affects the performance of the capacitor; on the other hand, the ratio of the height to the diameter of the columnar structure 120 is too large, and the structure is unstable and easily damaged.
In some embodiments of the present application, the height of the plurality of pillar structures 120 is 20 microns to 50 microns, such as 20 microns, 30 microns, 40 microns, or 50 microns. The higher the height of the pillar structure 120, the larger the surface area of the capacitor, and the higher the capacitance, but the requirements for the etching process and the deposition process are higher.
In some embodiments of the present application, two adjacent rows of the plurality of pillar structures 120 are staggered. Referring to fig. 1(a), two adjacent rows of the pillar structures 120 in the array are staggered and not aligned, which can form a greater number of pillar structures 120 on the same area of the semiconductor substrate. It should be noted that only a plurality of the column structures 120 are drawn in the drawings to illustrate the arrangement of the column structures 120, and the number of the column structures 120 is not limited.
Referring to fig. 2 to 5, a first electrode layer 150 is formed on the top surface of the semiconductor substrate 100, the sidewall surface and the bottom surface of the trench 110, and the sidewall surface and the top surface of the pillar structure 120 using a solid source diffusion process. The first electrode layer 150 does not occupy the space of the dielectric layer formed in the trench 110, and the charge storage capacity can be increased. By controlling the process parameters of the solid state source diffusion process, the solid state source diffusion process can form the first electrode layer 150 with good uniformity and controllable size and resistivity.
Referring to fig. 2, the method of forming the first electrode layer 150 using a solid source diffusion process includes: forming a doping source layer 130 on the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of columnar structures 120, wherein the doping source layer 130 has diffusion ions, and the diffusion ions comprise phosphorus. For example, the material of the dopant source layer 130 is PSG, and the PSG is silicon oxide doped with phosphorus. In a subsequent process, the phosphorus in the doping source layer 130 may be diffused to the surface of the semiconductor substrate 100, the trench 110, and the plurality of pillar structures 120 to form a first electrode layer 150.
In some embodiments of the present application, the method of forming the dopant source layer 130 is TEOS and TEPO deposition. The thickness of the doping source layer 130 is 60 nm to 100 nm, such as 60 nm, 80 nm, or 100 nm; the doping source layer 130 is doped with phosphorus at a concentration of 15% to 25%, for example, 15%, 20%, 25%, or the like.
In some embodiments of the present application, the dopant ions in the dopant source layer 130 may also be other types of dopant ions besides phosphorus, and the function of the dopant source layer 130 is to provide dopant ions for diffusing the dopant ions to form the first electrode layer 150 on the top surface of the semiconductor substrate 100, the sidewall surface and the bottom surface of the trench 110, and the sidewall surface and the top surface of the columnar structure 120, as long as the dopant ions in the dopant source layer 130 can be used to form the first electrode layer.
Referring to fig. 3, the method for forming the first electrode layer 150 by using the solid state source diffusion process further includes: and forming a covering layer 140 on the surface of the doping source layer 130. In the subsequent process, it is required to diffuse the phosphorus in the dopant source layer 130 to the surface of the semiconductor substrate 100, the surface of the trench 110, and the surfaces of the several pillar structures 120 to form the first electrode 150. Since the material diffuses in a direction with a lower concentration according to the diffusion principle, the covering layer 140 is required to enable the phosphorus in the dopant source layer 130 to diffuse to the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of pillar structures 120 to form the first electrode 150, rather than being collected on the side of the dopant source layer 130 away from the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of pillar structures 120.
In some embodiments of the present application, the method of forming the capping layer 140 includes TEOS deposition. The thickness of the capping layer 140 is 150 nm to 250 nm, such as 150 nm, 200 nm, or 250 nm.
In some embodiments of the present application, the material of the cap layer 140 includes silicon oxide, silicon nitride, silicon carbide, or the like.
Referring to fig. 4, the method for forming the first electrode layer 150 by using the solid state source diffusion process further includes: and performing thermal driving treatment to diffuse the diffused ions in the doping source layer 130 into the top surface of the semiconductor substrate 100, the part of the semiconductor substrate 100 at the side wall and the bottom of the trench 110, and the columnar structure 120, thereby forming a first electrode layer 150. The first electrode layer 150 does not occupy the space of the dielectric layer formed in the trench 110, and the charge storage capacity can be increased.
In some embodiments of the present application, the plurality of pillar structures 120 are completely doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, on the sidewall and bottom of the trench 110 in a portion of the semiconductor substrate 100, and on the entire area of the pillar structures 120. In other embodiments of the present application, the plurality of pillar structures 120 are only partially doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, on a portion of the semiconductor substrate 100 at the sidewalls and bottom of the trench 110, and on the sidewall regions and the top regions of the pillar structures 120.
In some embodiments of the present application, the thermally-driven process is a thermally-driven process of the semiconductor substrate using nitrogen gas. The temperature of the thermal drive treatment is 800 to 1200 degrees celsius, such as 900, 1000, or 1100 degrees celsius, or the like; the time of the heat driving treatment is 100 minutes to 150 minutes, such as 100 minutes, 120 minutes, 150 minutes, or the like. By controlling the process parameters of the thermal driving process, the size, resistivity, uniformity, etc. of the first electrode layer 150 may be adjusted.
Referring to fig. 5, the method for forming the first electrode layer 150 by using the solid state source diffusion process further includes: the dopant source layer 130 and the capping layer 140 are removed. The doping source layer and the capping layer 140 function to form the first electrode layer 150, and after the first electrode layer 150 is formed, the doping source layer 130 and the capping layer 140 need to be removed.
In some embodiments of the present application, the method of removing the dopant source layer 130 and the capping layer 140 includes wet etching.
In other embodiments of the present application, a method of forming the first electrode layer 150 includes: performing ion implantation on the top surface of the semiconductor substrate 100, part of the semiconductor substrate 100 at the side wall and the bottom of the trench 110, and the side wall region and the top region in the columnar structure 120; after the ion implantation, annealing treatment is performed.
In still other embodiments of the present application, the process of forming the first electrode layer 150 includes a deposition process; the first electrode layer 150 is located outside the semiconductor substrate 100 and outside the pillar structure 120.
Referring to fig. 6, a dielectric layer 160 is formed on the surface of the first electrode layer 150.
In some embodiments of the present application, the method of forming the dielectric layer 160 on the surface of the first electrode layer 150 includes an atomic layer deposition method. The atomic layer deposition method can form a film layer with good uniformity and high step coverage.
In some embodiments of the present application, the dielectric layer 160 has a single-layer structure, and the material of the dielectric layer 160 includes silicon oxide or silicon nitride.
In other embodiments of the present application, the dielectric layer 160 is a multi-layer stack structure; the dielectric layer 160 includes a first dielectric sublayer 161 and a second dielectric sublayer 162 on the first dielectric sublayer 161; the material of the first dielectric sublayer 161 includes silicon oxide, and the material of the second dielectric sublayer 162 includes silicon nitride.
The method of forming the first dielectric sublayer 161 comprises: using H2、O2And HCD growing the first dielectric sublayer 161 at a high temperature of 500 to 800 degrees celsius, such as 500, 600, 700, or 800 degrees celsius, the first dielectric sublayer 161 having a thickness of 60 to 100 nanometers, such as 60, 80, or 100 nanometers.
In some embodiments of the present application, after the first dielectric sublayer 161 is grown, the semiconductor substrate may be further heat-treated with nitrogen gas under high temperature conditions. The high temperature is 700 to 800 degrees celsius, such as 700, 750, or 800 degrees celsius, and the heat treatment time is 100 to 150 minutes, such as 100, 120, or 150 minutes.
The method of forming the second dielectric sublayer 162 comprises: using SiH2Cl2The second dielectric sublayer 162 is grown at a high temperature of 550 to 650 degrees celsius, such as 550, 580, 600, or 650 degrees celsius, and the second dielectric sublayer 162 has a thickness of 100 to 150 nanometers, such as 100, 120, or 150 nanometers.
In other embodiments of the present application, the dielectric layer 160 may further include more dielectric sublayers, such as a first dielectric sublayer, a second dielectric sublayer, a third dielectric sublayer, a fourth dielectric sublayer, and the like.
Referring to fig. 7, a second electrode layer 170 is formed on the surface of the dielectric layer 160, and the second electrode layer 170 fills the trench 110 around the pillar structure 120.
In some embodiments of the present application, a method of forming the second electrode layer 170 includes: using SiH4And pH3The second electrode layer 170 is grown under high temperature conditions. The high temperature is 600 to 700 degrees centigrade, such as 600, 6 degrees centigrade20 degrees celsius, 650 degrees celsius, 700 degrees celsius, or the like. The thickness of the second electrode layer 170 is 250 nm to 350 nm, such as 250 nm, 300 nm, or 350 nm.
In some embodiments of the present application, the second electrode layer 170 is polysilicon doped with N-type dopant concentration of 2E20cm-3。
In some embodiments of the present application, the second electrode layer 170 has a resistivity of 1.5 to 2m Ω · cm, for example 1.5, 1.8, or 2m Ω · cm, and the like.
Referring to fig. 8, the method for forming the semiconductor structure further includes: an interlayer dielectric layer 180 is formed on the semiconductor substrate 100, and a plurality of contact structures 190 penetrating the interlayer dielectric layer 180 and electrically connected to the first electrode layer 150 and the second electrode layer 170, respectively, are formed in the interlayer dielectric layer 180. It should be noted that each contact structure 190 can only be electrically connected to the first electrode layer 150 or the second electrode layer 170 individually, but cannot be electrically connected to the first electrode layer 150 and the second electrode layer 170 simultaneously, so that before the interlayer dielectric layer 180 is formed, a portion of the second electrode layer 170 on the semiconductor substrate 100 is etched, so that the second electrode layer 170 does not completely shield the first electrode layer 150.
In some embodiments of the present disclosure, a passivation layer may be further formed on the contact surface of the contact structure 190 and the first and second electrode layers 150 and 170, respectively, and the passivation layer may reduce the resistance of the first and second electrode layers 150 and 170 and increase the conductivity.
In some embodiments of the present application, the material of the passivation layer comprises salicide.
In some embodiments of the present application, the method of forming the semiconductor structure further comprises forming an aluminum pad on the surface of the contact structure.
In the method for forming the capacitor structure provided by the technical method, the groove is formed in the semiconductor substrate, the groove is internally provided with a plurality of discrete columnar structures formed by partial semiconductor substrates, and the columnar structures are distributed in an array form, so that the opening rate of the groove is higher, and secondly, the opening rate of the groove is higher, so that a deeper groove is favorably formed, and the larger side wall area and the larger bottom area of the groove are extended. And the first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and also along the sidewall surface and the top surface of the columnar structure, thereby increasing the effective area of the first electrode layer. And forming a dielectric layer on the surface of the first electrode layer, wherein the dielectric layer is formed along the surface of the first electrode layer, so that the effective area of the first electrode layer is increased. Accordingly, the area of the side of the second electrode layer opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer form a capacitor structure. Therefore, the effective area of the second electrode layer, the dielectric layer and the first electrode layer in the unit area of the substrate is increased, so that the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are improved, and the high-density silicon capacitor is manufactured. In conclusion, the performance of the capacitor structure is improved.
Further, the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the sidewall region and the top region in the columnar structure, or the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the entire region in the columnar structure. That is, the first electrode layer does not occupy the space of the trench, so that the dielectric layer and the second electrode layer have more filling space, which is beneficial to increasing the thickness of the dielectric layer. This results in an improved breakdown voltage resistance of the capacitor structure. And secondly, the first electrode layer does not occupy the space of the groove, and is positioned in the partial semiconductor substrate at the side wall and the bottom of the groove and in the columnar structure, so that the contact effective area of the first electrode layer and the dielectric layer is further improved, and the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are further improved.
Embodiments of the present application also provide a semiconductor structure, referring to fig. 1 and 8, including: the semiconductor device comprises a semiconductor substrate 100, wherein a groove 110 is formed in the semiconductor substrate 100, a plurality of discrete columnar structures 120 formed by partial semiconductor substrate 100 are arranged in the groove 110, and the plurality of columnar structures 120 are distributed in an array; a first electrode layer 150 on the top surface of the semiconductor substrate 100, the sidewall surface and the bottom surface of the trench 110, and the sidewall surface and the top surface of the pillar structure 120; a dielectric layer 160 on the surface of the first electrode layer 150; and a second electrode layer 170 on the surface of the dielectric layer 160, wherein the second electrode layer 170 fills the trench 110 around the pillar structure 120.
Referring to fig. 8, the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.
In some embodiments of the present application, the semiconductor substrate 100 is a P-type substrate, and the first electrode 150 may be formed by doping impurity ions on the surface of the P-type substrate through an N-type diffusion process in a subsequent process. In other embodiments of the present application, the semiconductor substrate 100 is an N-type substrate, and the first electrode 150 may be formed by doping impurity ions on the surface of the N-type substrate through a P-type diffusion process in a subsequent process.
Referring to fig. 1 and 8, the semiconductor substrate 100 has a trench 110 therein, and the trench 110 has a plurality of discrete pillar structures 120 formed by a portion of the semiconductor substrate 100 therein, wherein the plurality of pillar structures 120 are distributed in an array. The plurality of columnar structures 120 arranged in an array form the first electrode layer 150 in a subsequent process, and the array form the first electrode layer can increase the surface area of the capacitor, thereby increasing the capacitance.
In some embodiments of the present application, the number of columnar structures 120 are cylinders. Referring to fig. 1(a), in the case that the number of the pillar structures 120 is the same, the use of the pillar structures can maximize the distance between the adjacent pillar structures 120, accommodate more dielectric layers, and increase the capacitance.
In some embodiments of the present application, the diameter of the plurality of pillar structures 120 is 0.2 microns to 0.8 microns, such as 0.2 microns, 0.4 microns, 0.6 microns, or 0.8 microns, and the like. The smaller the diameter of the columnar structure 120 is, the larger the number of the columnar structures 120 that can be formed in the semiconductor substrate 110 is, the larger the surface area of the capacitor is, the higher the capacitance is, but on the one hand, the too small diameter causes the volume of the first electrode in the columnar structure 120 to be too small, which affects the performance of the capacitor; on the other hand, the ratio of the height to the diameter of the columnar structure 120 is too large, and the structure is unstable and easily damaged.
In some embodiments of the present application, the height of the plurality of pillar structures 120 is 20 microns to 50 microns, such as 20 microns, 30 microns, 40 microns, or 50 microns. The higher the height of the pillar structure 120, the larger the surface area of the capacitor, and the higher the capacitance, but the requirements for the etching process and the deposition process are higher.
In some embodiments of the present application, two adjacent rows of the plurality of pillar structures 120 are staggered. Referring to fig. 1(a), two adjacent rows of the pillar structures 120 in the array are staggered and not aligned, which can form a greater number of pillar structures 120 on the same area of the semiconductor substrate. It should be noted that only a plurality of the column structures 120 are drawn in the drawings to illustrate the arrangement of the column structures 120, and the number of the column structures 120 is not limited.
Referring to fig. 2, the method of forming the first electrode layer 150 includes: forming a doping source layer 130 on the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of columnar structures 120, wherein the doping source layer 130 has diffusion ions, and the diffusion ions comprise phosphorus. For example, the material of the dopant source layer 130 is PSG, and the PSG is silicon oxide doped with phosphorus. In a subsequent process, the phosphorus in the doping source layer 130 may be diffused to the surface of the semiconductor substrate 100, the trench 110, and the plurality of pillar structures 120 to form a first electrode layer 150. .
In some embodiments of the present application, the thickness of the dopant source layer 130 is 60 nm to 100 nm, such as 60 nm, 80 nm, or 100 nm; the doping source layer 130 is doped with phosphorus at a concentration of 15% to 25%, for example, 15%, 20%, 25%, or the like.
Referring to fig. 3, the method of forming the first electrode layer 150 further includes: and forming a covering layer 140 on the surface of the doping source layer 130. In the subsequent process, it is required to diffuse the phosphorus in the dopant source layer 130 to the surface of the semiconductor substrate 100, the surface of the trench 110, and the surfaces of the several pillar structures 120 to form the first electrode 150. Since the material diffuses in a direction with a lower concentration according to the diffusion principle, the covering layer 140 is required to enable the phosphorus in the dopant source layer 130 to diffuse to the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of pillar structures 120 to form the first electrode 150, rather than being collected on the side of the dopant source layer 130 away from the surface of the semiconductor substrate 100, the surface of the trench 110 and the surfaces of the plurality of pillar structures 120. In some embodiments of the present application, the thickness of the capping layer 140 is 150 nm to 250 nm, such as 150 nm, 200 nm, or 250 nm.
In some embodiments of the present application, the material of the cap layer 140 includes silicon oxide, silicon nitride, silicon carbide, or the like.
Referring to fig. 4, the method for forming the first electrode layer 150 further includes: and performing thermal driving treatment to diffuse the diffused ions in the doping source layer 130 into the top surface of the semiconductor substrate 100, the part of the semiconductor substrate 100 at the side wall and the bottom of the trench 110, and the columnar structure 120, thereby forming a first electrode layer 150. The first electrode layer 150 does not occupy the space of the dielectric layer formed in the trench 110, and the charge storage capacity can be increased.
In some embodiments of the present application, the plurality of pillar structures 120 are completely doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, on the sidewall and bottom of the trench 110 in a portion of the semiconductor substrate 100, and on the entire area of the pillar structures 120. In other embodiments of the present application, the plurality of pillar structures 120 are only partially doped, and the first electrode layer 150 is located on the top surface of the semiconductor substrate 100, on a portion of the semiconductor substrate 100 at the sidewalls and bottom of the trench 110, and on the sidewall regions and the top regions of the pillar structures 120.
In some embodiments of the present application, the thermally-driven process is thermally-driven processing of the semiconductor substrate using nitrogen gas. The temperature of the thermal drive treatment is 800 to 1200 degrees celsius, such as 900, 1000, or 1100 degrees celsius, or the like; the time of the heat driving treatment is 100 minutes to 150 minutes, such as 100 minutes, 120 minutes, 150 minutes, or the like. By controlling the process parameters of the thermal driving process, the size, resistivity, uniformity, etc. of the first electrode 150 may be adjusted.
Referring to fig. 5, the method for forming the first electrode layer 150 further includes: the dopant source layer 130 and the capping layer 140 are removed. The doping source layer and the capping layer 140 function to form the first electrode layer 150, and after the first electrode layer 150 is formed, the doping source layer 130 and the capping layer 140 need to be removed.
In other embodiments of the present application, a method of forming the first electrode layer 150 includes: performing ion implantation on the top surface of the semiconductor substrate 100, part of the semiconductor substrate 100 at the side wall and the bottom of the trench 110, and the side wall region and the top region in the columnar structure 120; after the ion implantation, annealing treatment is performed.
In still other embodiments of the present application, the process of forming the first electrode layer 150 includes a deposition process; the first electrode layer 150 is located outside the semiconductor substrate 100 and outside the pillar structure 120.
With continued reference to fig. 8, a dielectric layer 160 is formed on the surface of the first electrode layer 150.
In some embodiments of the present application, the dielectric layer 160 has a single-layer structure, and the material of the dielectric layer 160 includes silicon oxide or silicon nitride.
In other embodiments of the present application, the dielectric layer 160 is a multi-layer stack structure; the dielectric layer 160 includes a first dielectric sublayer 161 and a second dielectric sublayer 162 on the first dielectric sublayer 161; the material of the first dielectric sublayer 161 includes silicon oxide, and the material of the second dielectric sublayer 162 includes silicon nitride.
The thickness of the first dielectric sublayer 161 is 60 nm to 100 nm, such as 60 nm, 80 nm, or 100 nm. The thickness of the second dielectric sublayer 162 is 100 nm to 150 nm, such as 100 nm, 120 nm, 150 nm, and the like.
In other embodiments of the present application, the dielectric layer 160 may further include more dielectric sublayers, such as a first dielectric sublayer, a second dielectric sublayer, a third dielectric sublayer, a fourth dielectric sublayer, and the like.
Referring to fig. 7, a second electrode layer 170 is formed on the surface of the dielectric layer 160, and the second electrode layer 170 fills the trench 110 around the pillar structure 120.
In some embodiments of the present application, the thickness of the second electrode layer 170 is 250 nm to 350 nm, such as 250 nm, 300 nm, 350 nm, and the like.
In some embodiments of the present application, the second electrode layer 170 is polysilicon doped with N-type dopant concentration of 2E20cm-3。
In some embodiments of the present application, the second electrode layer 170 has a resistivity of 1.5 to 2m Ω · cm, for example 1.5, 1.8, or 2m Ω · cm, and the like.
With continued reference to fig. 8, the semiconductor structure further includes an interlayer dielectric layer 180 on the semiconductor substrate 100, and a plurality of contact structures 190 penetrating the interlayer dielectric layer 180 and electrically connected to the first electrode layer 150 and the second electrode layer 170, respectively. It should be noted that each contact structure 190 can only be electrically connected to the first electrode layer 150 or the second electrode layer 170 individually, and cannot be electrically connected to the first electrode layer 150 and the second electrode layer 170 simultaneously, so that a portion of the second electrode layer 170 on the semiconductor substrate 100 is etched away, so that the second electrode layer 170 does not completely shield the first electrode layer 150.
In some embodiments of the present disclosure, a passivation layer may be further formed on the contact surface of the contact structure 190 and the first and second electrode layers 150 and 170, respectively, and the passivation layer may reduce the resistance of the first and second electrode layers 150 and 170 and increase the conductivity.
In some embodiments of the present application, the material of the passivation layer comprises salicide.
In some embodiments of the present application, the semiconductor structure further comprises an aluminum pad formed on a surface of the contact structure.
In the capacitor structure provided by the technical method, the groove is formed in the semiconductor substrate, the groove is internally provided with a plurality of discrete columnar structures formed by partial semiconductor substrates, and the plurality of columnar structures are distributed in an array form, so that the opening rate of the groove is higher, and secondly, the opening rate of the groove is higher, so that a deeper groove is favorably formed, and the larger side wall area and the larger bottom area of the groove are extended. And the first electrode layer is partially formed along the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and also along the sidewall surface and the top surface of the columnar structure, thereby increasing the effective area of the first electrode layer. And forming a dielectric layer on the surface of the first electrode layer, wherein the dielectric layer is formed along the surface of the first electrode layer, so that the effective area of the first electrode layer is increased. Accordingly, the area of the side of the second electrode layer opposite to the dielectric layer is also increased. The second electrode layer, the dielectric layer and the first electrode layer form a capacitor structure. Therefore, the effective area of the second electrode layer, the dielectric layer and the first electrode layer in the unit area of the substrate is increased, so that the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are improved, and the high-density silicon capacitor is manufactured. In conclusion, the performance of the capacitor structure is improved.
Further, the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the sidewall region and the top region in the columnar structure, or the first electrode layer is located in the top surface of the semiconductor substrate, the partial semiconductor substrate of the trench sidewall and the bottom, and the entire region in the columnar structure. That is, the first electrode layer does not occupy the space of the trench, so that the dielectric layer and the second electrode layer have more filling space, which is beneficial to increasing the thickness of the dielectric layer. This results in an improved breakdown voltage resistance of the capacitor structure. And secondly, the first electrode layer does not occupy the space of the groove, and is positioned in the partial semiconductor substrate at the side wall and the bottom of the groove and in the columnar structure, so that the contact effective area of the first electrode layer and the dielectric layer is further improved, and the electrostatic capacity and the breakdown voltage resistance of the capacitor structure are further improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (20)

1. A method for forming a capacitor structure, comprising:
providing a semiconductor substrate;
forming a groove in the semiconductor substrate, wherein the groove is provided with a plurality of discrete columnar structures formed by partial semiconductor substrate, and the columnar structures are distributed in an array manner;
forming a first electrode layer on the top surface of the semiconductor substrate, the sidewall surface and the bottom surface of the trench, and the sidewall surface and the top surface of the columnar structure;
forming a dielectric layer on the surface of the first electrode layer;
and forming a second electrode layer on the surface of the dielectric layer, wherein the second electrode layer fills the groove around the columnar structure.
2. The method of claim 1, wherein the columnar structure comprises a cylinder.
3. The method as claimed in claim 1, wherein the plurality of pillar structures are distributed in an array, and two adjacent rows of pillar structures are staggered.
4. The method for forming a capacitor structure according to claim 1, wherein the first electrode layer is located on the top surface of the semiconductor substrate, on the sidewall and bottom portions of the trench in the semiconductor substrate, and on the sidewall and top regions of the pillar structure, or is located on the top surface of the semiconductor substrate, on the sidewall and bottom portions of the trench in the semiconductor substrate, and on the entire region of the pillar structure.
5. The method of claim 4, wherein the first electrode layer is formed using a solid state source diffusion process.
6. The method of claim 5, wherein forming the first electrode layer using a solid state source diffusion process comprises:
forming a doping source layer on the surface of the semiconductor substrate, the surface of the groove and the surfaces of the plurality of columnar structures, wherein the doping source layer is provided with diffusion ions;
forming a covering layer on the surface of the doping source layer;
after the covering layer is formed, carrying out thermal driving treatment, and enabling diffused ions in the doping source layer to be diffused into the top surface of the semiconductor substrate, the partial semiconductor substrate on the side wall and the bottom of the groove and the columnar structure to form a first electrode layer;
and removing the covering layer and the doping source layer after the thermal driving treatment is carried out.
7. The method of claim 6, wherein the dopant source layer comprises silicon oxide doped with phosphorus, and the diffusing ions comprise phosphorus.
8. The method of claim 6, wherein the dopant source layer has a thickness of 60 nm to 100 nm; the dopant source layer has a concentration of diffusing ions in the range of 15% to 25% prior to the thermal drive process.
9. The method of claim 6, wherein the material of the capping layer comprises silicon oxide; the thickness of the covering layer is 150 nm to 250 nm.
10. The method of forming the capacitor structure of claim 4, wherein the method of forming the first electrode layer comprises: performing ion implantation on the top surface of the semiconductor substrate, partial semiconductor substrate at the side wall and the bottom of the groove and the side wall area and the top area in the columnar structure; after the ion implantation, annealing treatment is performed.
11. The method of claim 1, wherein the process of forming the first electrode layer comprises a deposition process; the first electrode layer is located outside the semiconductor substrate and outside the columnar structure.
12. The method of claim 1, wherein the step of forming the dielectric layer on the surface of the first electrode layer comprises an atomic layer deposition process.
13. The method of claim 1, wherein the dielectric layer is a single layer structure, and the material of the dielectric layer comprises silicon oxide or silicon nitride; or, the dielectric layer is a multilayer stack structure; the dielectric layer comprises a first dielectric sublayer and a second dielectric sublayer located on the first dielectric sublayer; the material of the first dielectric sublayer comprises silicon oxide, and the material of the second dielectric sublayer comprises silicon nitride.
14. A capacitive structure, comprising:
the semiconductor substrate is provided with a groove, the groove is provided with a plurality of discrete columnar structures formed by partial semiconductor substrates, and the columnar structures are distributed in an array manner;
a first electrode layer on a top surface of the semiconductor substrate, sidewall surfaces and a bottom surface of the trench, and sidewall surfaces and a top surface of the columnar structure;
the dielectric layer is positioned on the surface of the first electrode layer;
and the second electrode layer is positioned on the surface of the dielectric layer, and the groove around the columnar structure is filled with the second electrode layer.
15. The capacitor structure of claim 14, wherein the plurality of columnar structures are cylinders.
16. The capacitor structure of claim 15, wherein each of the pillar structures has a diameter of 0.2 microns to 0.8 microns and a height of 20 microns to 50 microns.
17. The capacitor structure of claim 14, wherein the plurality of pillar structures arranged in an array are staggered in two adjacent rows.
18. The capacitor structure of claim 14, wherein the first electrode layer is located in the top surface of the semiconductor substrate, in the portion of the semiconductor substrate at the trench sidewalls and bottom, and in the sidewall region and the top region in the pillar structures, or wherein the first electrode layer is located in the top surface of the semiconductor substrate, in the portion of the semiconductor substrate at the trench sidewalls and bottom, and in the entire region in the pillar structures.
19. The capacitor structure of claim 14, wherein the first electrode layer is located outside the semiconductor substrate and outside the pillar structures.
20. The capacitor structure of claim 14, wherein the dielectric layer is a single layer structure, and the material of the dielectric layer comprises silicon oxide or silicon nitride; or, the dielectric layer is a multilayer stack structure; the dielectric layer comprises a first dielectric sublayer and a second dielectric sublayer located on the first dielectric sublayer; the material of the first dielectric sublayer comprises silicon oxide, and the material of the second dielectric sublayer comprises silicon nitride.
CN202010202321.5A 2020-03-20 2020-03-20 Capacitor structure and forming method thereof Pending CN113497006A (en)

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