CN1231835C - Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA - Google Patents

Abstract

The present invention relates to a demodulation and logarithm compression subsystem based on FPGA used for a medical ultrasonic imaging system, which belongs to the technical field of medical ultrasonics. The present invention is characterized in that the subsystem comprises a Hilbert conversion circuit, two multipliers, an adder, a register and a square root and logarithm compressing circuit, wherein digital echo signals are input in the Hilbert conversion circuit; the two multipliers respectively calculate the square of the output of the conversion circuit; the adder obtain the sum of the squares; the register extracts the sum of the squares with intervals according to the ratio of sampling rate of the echo signals and the sampling rate of scanning line when images are formed; the square root and logarithm compressing circuit is designed based on the binary tree comparison method and combines the square root operation and the logarithm compression operation; the square root and logarithm compressing circuit only needs one comparator, one 8 bit shift register and an RAM with a size of 2#+[8]*16 bits to realize the logarithm operation with 16 bits input and 8 bits output. The present invention simplifies the hardware structure, and simultaneously, realizes the best demodulation and compression effect.

Description

Be in harmonious proportion the log-compressed subsystem based on the medical ultrasound image system of FPGA with separating

Technical field

Medical ultrasound image system based on FPGA belongs to the medical ultrasound image technical field with separating mediation log-compressed subsystem

Background technology

In B pattern medical ultrasound image (B ultrasonic) system, the echoed signal that array element receives is to be the amplitude-modulated signal of centre frequency with the transmission frequency, need come out the envelope extraction that comprises institutional framework information by demodulation.In order to improve the display capabilities of imaging system, need carry out log-compressed to the echoed signal after the demodulation to the weak signal in the echo.

Simulation system adopts mimic channel that echoed signal is separated the mediation log-compressed.

In the medical ultrasound image system of total digitalization, the ultrasonic echo that array element receives carries out ADC after amplifying through prime at once, obtains digital echo.Therefore, need carry out digital demodulation and log-compressed processing to echoed signal.

Known demodulation method has simple rectification method, biorthogonal demodulation method and Hilbert converter technique.

The demodulation effect of simple rectification method is not as biorthogonal demodulation method and Hilbert converter technique, and the circuit structure more complicated of biorthogonal demodulation method and Hilbert converter technique.

Known log-compressed method has look-up table and piecewise fitting method.The shortcoming of common look-up method is need very big look-up table; The shortcoming of piecewise fitting method is that precision is not so good as look-up table.

Summary of the invention

The object of the present invention is to provide a kind of medical ultrasound image system based on FPGA to be in harmonious proportion the log-compressed subsystem with separating.

The invention is characterized in that it contains:

Be input as the Hilbert translation circuit of echoed signal r (n);

Respectively to the output signal r (n) of Hilbert translation circuit, Carry out two multipliers of square operation;

Output r to two multipliers ²(n),

The totalizer of summation;

Output A to totalizer ²(n) register that extracts;

Output A to register ²(Mn) carry out square root and log-compressed computing, and its output signal is klog ₂The square root and the log compression circuit of (A (Mn)), wherein M=f _s/ f _d, f _sBe the sample frequency of digital echo signal, f _dThe sample frequency of sweep trace during for imaging, k is a scale-up factor, k=2 ^q/ p, p are A ²(Mn) figure place, q is the figure place of image data point, makes A ²(Mn)=2 ^pThe time, klog ₂(A (Mn))=2 ^q

Described Hilbert translation circuit, multiplier, totalizer, register, square root and log compression circuit all are made on the fpga chip;

Described square root and log compression circuit are based on the design of binary tree relative method, and it contains:

8 bit shift register, it is provided with the control input end that resets, input end of clock, reset input 00000001 end, the signal input part that moves to left, and result of calculation output terminal and address output end;

RAM, it is provided with input end of clock and data output end, and it links to each other with the address output end of 8 bit shift register again;

Comparer, it is provided with the input end of the numerical signal that above-mentioned register sends, and it links to each other with the data output end of RAM, the signal input part that moves to left of 8 bit shift register again.

Described Hilbert translation circuit be take from the Hilbert wave filter shock response-(2k+1)～2k+1 part.

Use proof: because square root among the present invention and log compression circuit are to use the binary tree relative method to carry out log-compressed, thereby in the simplified system hardware configuration, obtained the best mediation compression effectiveness of separating on the basis of Hilbert conversion and demodulation.

Description of drawings

Fig. 1. the schematic diagram of the system that the present invention proposes.

Fig. 2. the schematic block circuit diagram of the system that the present invention proposes.

Fig. 3. the theory diagram of Hilbert translation circuit.

Fig. 4. the theory diagram of square root and log compression circuit.

Fig. 5. logarithm operation y=klog ₂(x) curve.

Fig. 6. the synoptic diagram of binary tree relative method.

Fig. 7. demodulation design sketch of the present invention.

Embodiment

Fig. 1 is the synoptic diagram of digital demodulation and log-compressed step.Digital echo signal r (n) is at first through the Hilbert conversion, obtain r (n) and R (n) and Summation obtains A after square ²(n); A ²(n) after the extraction, obtain A ²(Mn); A ²(Mn) obtain klog through square root and logarithm operation ₂(A (Mn)); Klog ₂(A (Mn)) exports follow-up DSC to, and DSC is the digital scanning conversion, obtains ultrasonoscopy.

Among Fig. 1, the interval M of extraction depends on the sample rate f of digital echo signal _sThe sample rate f of sweep trace during with imaging _d:

$M=\frac{f_s}{f_d},$

f _sBe f _dIntegral multiple, M is an integer.

K is a scale-up factor.A ²(Mn) figure place is p, and when the figure place of image data point was q, k was:

$k=\frac{2^q}{p},$

Make A ²(Mn)=2 ^pThe time, klog ₂(A (Mn))=2 ^q

The merging of square root and logarithm operation is handled, and has simplified system architecture.

Utilize the skew-symmetry of Hilbert filter coefficient, with and the even number coefficient be 0 characteristics, adopt mode shown in Figure 3 to realize the Hilbert conversion of digital echo signal.

The Hilbert wave filter is the wave filter of infinite impulse response, in the practical application with its brachymemma.Wave filter shown in Figure 3 has been got desirable Hilbert wave filter shock response-(2k+1)～2k+1 part.

Method square root shown in Figure 1 and log-compressed merge to be carried out, and need not design the square root calculation circuit separately, because:

If adopt simple look-up table, when the sampling precision of echoed signal is 8bits,

It is the number of a 16bits.Therefore the size of look-up table is 2 ¹⁶* 8 ≈ 512kbits.And the size of the required look-up table of the binary tree relative method that adopts us to invent only is 2 ⁸* 16 ≈ 4kbits, and can obtain and the simple duplicate computational accuracy of look-up table.

Fig. 5 is logarithm operation y=klog ₂(x) curve, the effect of coefficient k is to make x=2 ¹⁶The time, y=2 ⁸

Work as x=x _10000000The time, y=2 ⁷, i.e. x 〉=x _10000000The time, the most significant digit of the binary representation of y is " 1 ", x＜x _10000000The time, the most significant digit of the binary representation of y is " 0 ";

Work as x=x _01000000The time, y=2 ⁶, i.e. x _10000000＞x 〉=x _01000000The time, time high position of the binary representation of y is " 1 ", x＜x _01000000The time, time high position of the binary representation of y is " 0 ";

Work as x=x _11000000The time, y=2 ⁷+ 2 ⁶, i.e. x 〉=x _11000000The time, time high position of the binary representation of y is " 1 ", x _11000000＞x 〉=x _01000000The time, time high position of the binary representation of y is " 0 ".

Can the rest may be inferred, until the lowest order of the binary representation of y.

Utilize this characteristics, can adopt binary tree relative method shown in Figure 6 to calculate the logarithm result of calculation y of given x.Relatively export for the first time the 7th of binary representation of y; For the second time relatively export the 6th; The rest may be inferred, relatively exports the 0th the 8th time.

If the method that directly adopts Fig. 6 to describe, hardware realize needing 2 ⁸-1 comparer, x _10000000～x _11111111Distributed storage, the circuit structure more complicated.Circuit shown in Figure 4 only needs a comparer, and one 8 bit shift register and a size are 2 ⁸The RAM of * 16bits just can realize the 16bits input, the logarithm operation of 8bits output.

The course of work of circuit is described below:

If raw data x is latched on the numerical value input data line shown in Figure 4 at the rising edge of first clock.

It is " 00000001 " that the rising edge of first clock makes reset shift register; Negative edge makes the x of RAM OPADD for " 00000001 " _10000000

The rising edge of second clock makes shift register move to left one, (" * " is " 0 " or " 1 " in the output " * " of comparer, decide according to actual conditions) be latched at the lowest order of shift register, this moment, the value of shift register storage was " 0000001 * "; Negative edge makes the x of RAM OPADD for " 0000001 * " _01000000Or x _11000000

The rising edge of the 3rd clock makes shift register move to left one again, and the output " * " of comparer is latched at the lowest order of shift register, and the value of shift register storage this moment is " 000001 * * "; Negative edge makes the data of RAM OPADD for " 000001 * * ".

So until the rising edge of the 9th clock, register move to left that the value of storage becomes after one " * * * * * * * * ", i.e. the result of logarithm operation; When negative edge, this result is latched and exports.

So repeat, per nine clock calculation go out the log-compressed result of a sampling number certificate.

In circuit shown in Figure 4, the RAM data must be by certain form storage.Only need be with x _10000000～x _11111111These are 2 years old ⁸After the upset, the RAM that deposits circuit shown in Figure 4 as the address in gets final product before and after the subscript of-1 number.

Therefore, address ram for " * * * * * * * * " data of (* * * * * * * * ≠ 00000000) can ask for by following method:

1. incite somebody to action " * * * * * * * * " the front and back upset, obtain y;

2. calculate according to following formula, obtain x:

x＝2 ^y/k；

3. y is deposited in the address " * * * * * * * * " in.

Solid line waveform among Fig. 7 is an echoed signal that comes from single scattering.Its parameter is as follows: centre frequency f ₀=5MHz, sample rate f _s=5f ₀=25MHz, the probe bandwidth is 40%.Dotted line waveform among Fig. 7 is the effect of demodulation.

Claims (2)

1, be in harmonious proportion the log-compressed subsystem based on the medical ultrasound image system of FPGA with separating, contain field programmable gate array (FPGA), it is characterized in that it contains:

Be input as the Hilbert translation circuit of echoed signal r (n);

Respectively to the output signal r (n) of Hilbert translation circuit,

Carry out two multipliers of square operation;

Output r to two multipliers ²(n),

The totalizer of summation;

Output A to totalizer ²(n) register that extracts;

Output A to register ²(Mn) carry out square root and log-compressed computing, and its output signal is klog ₂The square root and the log compression circuit of (A (Mn)), wherein M=f _s/ f _d, f _sBe the sample frequency of digital echo signal, f _dThe sample frequency of sweep trace during for imaging, k is a scale-up factor, k=2 ^q/ p, p are A ²(Mn) figure place, q is the figure place of image data point, makes A ²(Mn)=2 ^pThe time, klog ₂(A (Mn))=2 ^q

Described Hilbert translation circuit, multiplier, totalizer, register, square root and log compression circuit all are made on the fpga chip:

Described square root and log compression circuit are based on the design of binary tree relative method, and it contains:

8 bit shift register, it is provided with the control input end that resets, input end of clock, reset input 00000001 end, the signal input part that moves to left, and result of calculation output terminal and address output end;

RAM, it is provided with input end of clock and data output end, and it links to each other with the address output end of 8 bit shift register again;

Comparer, it is provided with the input end of the numerical signal that above-mentioned register sends, and it links to each other with the data output end of RAM, the signal input part that moves to left of 8 bit shift register again.

2, the medical ultrasound image system based on FPGA according to claim 1 is in harmonious proportion the log-compressed subsystem with separating, and it is characterized in that: described Hilbert translation circuit is to take from Hilbert: the shock response of wave filter-(2k+1)～the 2k+1 part.

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