CN108170402A - A kind of floating number logarithmic function implementation method based on FPGA - Google Patents

A kind of floating number logarithmic function implementation method based on FPGA Download PDF

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Publication number
CN108170402A
CN108170402A CN201711189101.8A CN201711189101A CN108170402A CN 108170402 A CN108170402 A CN 108170402A CN 201711189101 A CN201711189101 A CN 201711189101A CN 108170402 A CN108170402 A CN 108170402A
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floating number
logarithmic function
logarithm
floating
log
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Inventor
张柯
王嵚峰
刘志凯
梁成华
王冬
马刚
魏涛涛
崔兰
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Center Control Systems Engineering (cse) Co Ltd
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Center Control Systems Engineering (cse) Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/556—Logarithmic or exponential functions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)

Abstract

The invention belongs to technical field of industrial control, and in particular to a kind of floating number logarithmic function implementation method based on FPGA.Logarithm using a as bottom X is asked for any one, and a is known parameters, and X is input, utilizes the logarithm for formula being refooted by arbitrary logarithm and being turned to 2 bottom of for；Seek log2X：In IEEE754 standards, the true value of the floating number X of a normalization 32 is expressed as：X=(1)S×(1.M)×2e, wherein e=E 127, S represent the sign bit of 754 forms of floating number X, M expression mantissa bits, the exponent of 754 forms of E expression floating numbers X；It is assumed that log2 (1.M)=L, then 1.M=2L, it is constantly squared by both sides, all L values are gradually obtained；By above procedure, logarithmic function is asked to have been converted into the form that hardware is easily achieved, describing the above process in FPGA platform with verilog hardware description languages realizes.Directly using logarithmic function is sought floating number, calculation step is simple.Calculating process does not need to mutually converting for fixed-point number and floating number, and execution cycle is short, and the corresponding time is fast.

Description

A kind of floating number logarithmic function implementation method based on FPGA
Technical field
The invention belongs to technical field of industrial control, and in particular to a kind of floating number logarithmic function realization side based on FPGA Method.
Background technology
I＆C system is digitized, is the control axis of nuclear power station.Because its is efficient, failure rate is low, and the advantages such as easy care are adopted Have become the trend of domestic and international nuclear power developing with digitlization I＆C system.FPGA has reliability high, and speed is fast, design letter Change, the features such as can programming repeatedly, equipment complexity can be reduced, therefore obtained during nuclear power instrument control digitizes upgrading Extensive use.
It needs to use a large amount of algorithm in the mathematical model of digitlization table control system, operational data amount is big, logic function Complexity, algorithm type are more, include the basic operations such as logical operation, floating point math operation, temporal calculation.These are calculated with FPGA etc. Hardware platform realization is relatively difficult, and wherein asks floating number logarithmic function realization method fewer, and calculating process is complicated.
Current floating point number asks logarithmic function to be realized mainly using cordic modes in FPGA platform, realizes fixed-point number logarithm letter Then result is being converted into floating number by several operations, calculating step is more, and fixed-point number is needed to be converted into floating number, transports Evaluation time is long.
Invention content
The purpose of the present invention is to provide a kind of floating number logarithmic function implementation methods based on FPGA, have reliability It is high, algorithm performs are efficient, using it is flexible the features such as, overcome traditional floating number and ask lacking in the hardware realization of logarithmic function Point, improves response speed.
In order to achieve the above objectives, the technical solution used in the present invention is：
A kind of floating number logarithmic function implementation method based on FPGA, includes the following steps：
The first step：Logarithm using a as bottom X is asked for any one, a is known parameters, and X is input, first with refooting Arbitrary logarithm is turned to the logarithm with 2 bottom of for by formula；Demand goes out log2X, then result can be obtained with floating number division；Refoot public affairs Formula：logax=log2X/log2a；
Second step：Seek log2X：In IEEE754 standards, the true value of the floating number X of a normalization 32 is expressed as：X= (-1)S×(1.M)×2e, wherein e=E-127, S represent the sign bit of 754 forms of floating number X, M expression mantissa bits, E expressions The exponent of 754 forms of floating number X；Demand goes out log2 (1.M)；
Third walks：Seek log2 (1.M)：It is assumed that log2 (1.M)=L, then 1.M=2L, it is constantly squared by both sides, gradually it is obtained All L values；
4th step：By above procedure, logarithmic function is asked to have been converted into the form that hardware is easily achieved, uses verilog Hardware description language describes the above process and is realized in FPGA platform.
Having the beneficial effect that acquired by the present invention：
Directly using logarithmic function is sought floating number, calculation step is simple.Calculating process does not need to fixed-point number and floating number Mutually convert, execution cycle is short, and the corresponding time is fast.
Description of the drawings
Fig. 1 is seeks logarithmic function state transition figure.
Specific embodiment
The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.
As shown in Figure 1, the floating number logarithmic function implementation method of the present invention based on FPGA is as follows：
The first step：Logarithm using a as bottom X is asked for any one, a is known parameters, and X is input, first with refooting Arbitrary logarithm is turned to the logarithm with 2 bottom of for by formula.
Refoot formula：logax=log2X/log2a
log2aIt can be used by calculator evaluation as a constant.Demand goes out log2X, then use floating number Division can obtain result.
Second step：Seek log2X：In IEEE754 standards, the true value of the floating number X of a normalization 32 is expressed as：X= (-1)S×(1.M)×2e, wherein e=E-127, wherein, S represents the sign bit of 754 forms of floating number X, and M represents mantissa bit, E Represent the exponent of 754 forms of floating number X.Only consider X>0 situation：
log2 X=log2 (1.M*2^(E-127))=log2 (1.M)+ E-127=log2 (1.M)+ 1+E-127-1=log2 (1.M)+1+E- 128
In this way, log2 (1.M) itself can log2 (1.M)+1 754 forms mantissa, this step can be by final result The step for being converted into 754 form floating number simplifies.Demand goes out log2 (1.M)
Third walks：Seek log2 (1.M)：It is assumed that log2 (1.M)=L, then 1.M=2L, L is one【0,1】One data in section 0.X0X1X2X3X4..., 1.M2=22L=22*0.X 0 X 1 X 2 X 3 X 4... ..=2X 0 .X 1 X 2 X 3 X 4.....
Wherein X0X1X2X3X4... represents fractional part the 0th, the 1st ... the data of respectively
If 1.M2>=2, then X0.X1X2X3X4....>1, so as to integer part X0=1
1.M2=22*0.X 0 X 1 X 2 X 3 X 4... ..=2(1+0.X 0 X 1 X 2 X 3 X 4...)=2*2(0.X 0 X 1 X 2 X 3 x 4....)
Both sides simultaneously divided by 2, then again turn to 2(0.X 0 X 1 X 2 X 3 X 4......)=1/2*1.M2
Continue squared, all values until L is obtained in both sides.
If 1.M2<2, then X0.X1X2X3X4....<1, so as to integer part X0=0
1.M2=2*0.X1X2X3X4X5... both sides continuation square judges X according to the method described above1Value
Value until all L are obtained.
4th step：After above-mentioned steps, logarithmic function can be reduced to shift and add and subtract operation completely, reduce multiple Polygamy is easy to the realization of hardware, and the above process is described with Verilog hardware description languages, later can be in FPGA platform Upper realization.
Natural logrithm lg1000 is asked to further illustrate technical scheme of the present invention with reference to specific example：
Its working method point following steps performs：
The first step：First with the logarithm for refooting formula by arbitrary logarithm and turning to 2 bottom of for.
Refoot formula：Lg1000=log2 1000/log2 10
log2 10It can be used by calculator evaluation as a constant.Demand goes out log2 1000, then use floating-point Number division can obtain result.
Third walks：Seek log2 1000
In IEEE754 standards, the true value of 1000 floating number x is expressed as：X=(1.111101000) × 29, M= 111101000, E=9+127=10001000
log2 1000=log2 (1.M)+ E-127=log2 (1.M)+ 1+E-127-1=log2 (1.111101000)+1+E-128
Third walks：Seek log2 (1.111101000)：
It is assumed that log2 (1.111101000)=L, then 1.111101000=2L, L is one【0,1】One data in section 0.X0X1X2X3X4..., 1.1111010002=22L=22*0.X 0 X 1 X 2 X 3 X 4... ..=2X 0 .X 1 X 2 X 3 X 4.....
Understand 1.M2=11.110010101001>2 X0.X1X2X3X4....>1, so as to integer part X0=1
1.M2=22*0.X 0 X 1 X 2 X 3 X 4... ..=21+0.X 0 X 1 X 2 X 3 X 4=2*2(0.X 0 X 1 X 2 X 3 X 4....)
Both sides simultaneously divided by 2, then again turn to 1/2*1.M2=2(0.X 0 X 1 X 2 X 3 X 4....)
I.e.：1.1110010101001=2(0.X 0 X 1 X 2 X 3 X 4....)
Have be converted into can iteration form, so as to which all values of L be obtained successively
4th step：After above-mentioned steps, logarithmic function can be reduced to shift and add and subtract operation completely, use Verilog hardware description languages describe above-mentioned plus-minus and shifting function, later can be realized in FPGA platform.

Claims (1)

1. a kind of floating number logarithmic function implementation method based on FPGA, it is characterised in that：Include the following steps：
The first step：Logarithm using a as bottom X is asked for any one, a is known parameters, and X is input, first with the formula that refoots Arbitrary logarithm is turned into the logarithm with 2 bottom of for；Demand goes out log2X, then result can be obtained with floating number division；Refoot formula： logax=log2X/log2a；
Second step：Seek log2X：In IEEE754 standards, the true value of the floating number X of a normalization 32 is expressed as：X=(- 1)S ×(1.M)×2e, wherein e=E-127, S represent the sign bit of 754 forms of floating number X, M expression mantissa bits, E expression floating-points The exponent of 754 forms of number X；Demand goes out log2 (1.M)；
Third walks：Seek log2 (1.M)：It is assumed that log2 (1.M)=L, then 1.M=2L, it is constantly squared by both sides, it is gradually obtained all L values；
4th step：By above procedure, logarithmic function is asked to have been converted into the form that hardware is easily achieved, with verilog hardware Description language describes the above process and is realized in FPGA platform.
CN201711189101.8A 2017-11-24 2017-11-24 A kind of floating number logarithmic function implementation method based on FPGA Pending CN108170402A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1431581A (en) * 2003-02-28 2003-07-23 清华大学 Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA
CN1472636A (en) * 2002-07-29 2004-02-04 矽统科技股份有限公司 Floating number logarithm computing method and device
CN1687895A (en) * 2005-06-07 2005-10-26 北京北方烽火科技有限公司 Method for implementing logarithm computation by field programmable gate array in digital auto-gain control
US7346642B1 (en) * 2003-11-14 2008-03-18 Advanced Micro Devices, Inc. Arithmetic processor utilizing multi-table look up to obtain reciprocal operands
CN101317152A (en) * 2005-10-05 2008-12-03 高通股份有限公司 Floating-point processor with selectable subprecision
CN104035745A (en) * 2014-06-05 2014-09-10 杭州电子科技大学 Logarithm loga x operating circuit and implementation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1472636A (en) * 2002-07-29 2004-02-04 矽统科技股份有限公司 Floating number logarithm computing method and device
CN1431581A (en) * 2003-02-28 2003-07-23 清华大学 Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA
US7346642B1 (en) * 2003-11-14 2008-03-18 Advanced Micro Devices, Inc. Arithmetic processor utilizing multi-table look up to obtain reciprocal operands
CN1687895A (en) * 2005-06-07 2005-10-26 北京北方烽火科技有限公司 Method for implementing logarithm computation by field programmable gate array in digital auto-gain control
CN101317152A (en) * 2005-10-05 2008-12-03 高通股份有限公司 Floating-point processor with selectable subprecision
CN104035745A (en) * 2014-06-05 2014-09-10 杭州电子科技大学 Logarithm loga x operating circuit and implementation method thereof

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Application publication date: 20180615