CN104306027B - The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method - Google Patents
The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method Download PDFInfo
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Abstract
A kind of real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method, FPGA sets up data distribution module respectively that be connected with data input signal, the total module of log-compressed being connected is exported with data distribution module, and the Data Integration module that the output of module total with log-compressed is connected, wherein, the total module of log-compressed is to be made up of the log-compressed submodule identical with N+1 output channel number of data distribution module, and N is the figure place of the compression result that Data Integration module is exported.When the present invention is capable of the arrival of each rising edge clock, there is a log-compressed result output, it is ensured that the ultrasonic echo data signal real-time when log-compressed processes.Log-compressed can be effectively compressed the dynamic range of input signal, strengthens small-signal, and reaches the requirement processed in real time.Wherein the space required for ROM is 28× 16bit, it is possible to effectively reduce taking of hardware resource.
Description
Technical field
The present invention relates to a kind of real-time log compression circuit of medical ultrasonic equipment.Particularly relate to a kind of based on FPGA
The real-time log compression circuit of medical ultrasonic equipment builds method
Background technology
Medical ultrasonic equipment is used for carrying out human body soft tissue fault imaging real-time, dynamic.Medical ultrasound diagnostic
System launches ultrasonic wave by ultrasonic transducer, and receives after tissue resorption, scattering etc. decay anti-again by transducer
The ultrasound echo signal being emitted back towards.Echo-signal is converted into data signal through A/D chip, FPGA completes filtering, detection,
The Digital Signal Processing such as log-compressed, realize noise suppressed, the compression of signal solution mediation dynamic range, after finally sending into respectively
End system display ultrasonoscopy.
Wherein, log-compressed is a requisite process during ultrasound echo signal processes.The each soft tissue of human body is to super
The absorption coefficient of sound is 0.6-0.7dB/cm.MHz, causes the dynamic range of ultrasound echo signal to reach more than 100dB, it is difficult to
Terminal display shows.While log-compressed utilizes non-linear relation to be compressed by the signal of Larger Dynamic scope, to can
The weak echo signal of reflection organization of human body details has drawing effect relative to other strong signals, plays the effect increasing contrast.
Traditional log-compressed uses look-up table directly to compress, if by the data that data compression is 8 of 16, the look-up table of needs
Size is 216× 8bit, the hardware resource taken is excessive.Chinese patent medical ultrasonic imaging system based on FPGA is with solving mediation
The log-compressed method used in log-compressed system (03104777.7) needs 9 clocks just can obtain a compression result,
And rear 8 data to be compressed of input will be unable to be processed in time during these 9 clocks, when being applied in actual product,
Data processing speed and imaging real-time can be had a strong impact on.
Summary of the invention
The technical problem to be solved is to provide a kind of data only needed in replacement ROM just can realize difference
The real-time log compression circuit of medical ultrasonic equipment based on FPGA of the compression of curve builds method.
The technical solution adopted in the present invention is: a kind of real-time log compression circuit of medical ultrasonic equipment based on FPGA
Structure method, FPGA sets up respectively be connected with data input signal for input data to be compressed are divided into N+1 way
According to the data distribution module of output, it is connected for the data of N+1 paths are same respectively with described data distribution module output
Shi Jinhang log-compressed computing, and N+1 log-compressed result is carried out the total module of log-compressed exported, and with logarithm pressure
The output of total module that contracts is connected and according to the sequencing arrangement of corresponding data before compression, N+1 log-compressed result is integrated into one
The Data Integration module of road signal, wherein, the total module of described log-compressed is by N+1 with described data distribution module
The log-compressed submodule that output channel number is identical is constituted, and described N is the compression result that Data Integration module is exported
Figure place.
The construction method of described data distribution module is:
1) by N+1 log-compressed in N+1 output channel of data distribution module respectively module total with log-compressed
The input correspondence of module is connected；
2) input data to be compressed are inputted described data distribution module with the frequency of each 1 data of clock；
3) the 1st data of the 1st clock are exported by data distribution module from the 1st paths, by the 2nd of the 2nd clock the
Individual data export from the 2nd paths, until by the N+1 data of N+1 clock after N+1 paths exports, by N
The N+2 data of+2 clocks from the 1st paths output, the most so circulate, until diasonograph terminates to sweep again
Retouch.
The construction method of the total module of described log-compressed is, each log-compressed submodule is receiving data distribution
Each output signal of module, will carry out data process through N+1 clock to received signal, be then output to
Data Integration module.
Described data process and include: dividing two-way by the clock signal being used for controlling sequential, a not gate of leading up to enters
Entering read-only storage, another road is directly entered N bit address selector, and the output of described read-only storage connects comparator
One input, another input of comparator connects the corresponding output of described data distribution module, described comparison
Two outputs of device connect two inputs of N bit address selector respectively, and the output of N bit address selector connects described
The input of read-only storage, the most also constitute the output of log-compressed submodule.
The course of work of described N bit address selector is:
When the 1st clock, the address reset in N bit address selector is 2N-1；When the 2nd clock, N bit address is selected
Select device and the output result of comparator is latched in the highest order of address in N bit address selector, cast out lowest order and form new address；
When the 3rd clock, the output result of comparator is latched in the second highest of address in N bit address selector by N bit address selector
Position, casts out lowest order and forms new address；Carry out successively until during N+1 clock, N bit address selector is by the output of comparator
Result is latched in the lowest order of address in N bit address selector, forms new address, and described new address is that log-compressed submodule is defeated
The compression result gone out.
The course of work of described read-only storage is: setting x in the storage table of read-only storage as storage value, y is
Storage table address, then by logarithm operation curve y=kloga(x+1) trying to achieve x value, wherein, y value is 0～(2N-1), k and a is
Constant.
The construction method of described Data Integration module is:
1) by N+1 log-compressed in N+1 input channel of Data Integration module respectively module total with log-compressed
The output channel correspondence of module is connected.
2) Data Integration module at the 1st clock by defeated from output channel for the compression result of the 1st log-compressed submodule
Go out, at the 2nd clock, the compression result of the 2nd log-compressed submodule is exported from output channel, until at the N+1 clock
The compression result of the N+1 log-compressed submodule is exported from output channel, at the N+2 clock by the N+2 logarithm pressure
The compression result of contracting submodule exports from output channel, the most so circulates, until diasonograph terminates scanning.
The real-time log compression circuit of medical ultrasonic equipment based on FPGA of the present invention builds method, uses FPGA to weigh
Change the circuit of configuration again, meet the high speed processing of big data quantity complex calculation.The present invention is capable of each rising edge clock
During arrival, there is a log-compressed result output, it is ensured that the ultrasonic echo data signal real-time when log-compressed processes.
Log-compressed can be effectively compressed the dynamic range of input signal, strengthens small-signal, and reaches the requirement processed in real time.Its
Space required for middle ROM is 28× 16bit, it is possible to effectively reduce taking of hardware resource.Present invention only requires in replacement ROM
Data just can realize the compression of different curve, have portable well.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention；
Fig. 2 is logarithm operation curve map；
Fig. 3 is the structural representation of log-compressed submodule in the present invention.
In figure
1: data distribution module 2: the total module of log-compressed
21～29: log-compressed submodule 3: Data Integration module
210: read-only storage 211: comparator
212:N bit address selector 213: not gate
Detailed description of the invention
Medical ultrasonic equipment based on the FPGA real-time log-compressed electricity to the present invention below in conjunction with embodiment and accompanying drawing
Road builds method and is described in detail.
First explanation log-compressed utilizes logarithm operation curve y=klog the most exactlya(x+1), (a > 1) is to defeated
Entering signal x and carry out nonlinear modulation, the value of a determines the shape of curve, and the value of k depends on the figure place of input signal x.
As in figure 2 it is shown, described logarithm operation curve is a monotonically increasing curve, then work as x1<x2Time, must there is y1<y2Set up, its
Middle y1、y2Respectively to taking x by x1、x2Time y=kloga(x+1) value.
As it is shown in figure 1, the real-time log compression circuit of medical ultrasonic equipment based on FPGA of the present invention builds method,
The number for input data to be compressed being divided into the output of N+1 circuit-switched data being connected with data input signal is set up respectively on FPGA
According to diverter module, it is connected for the data of N+1 paths to be carried out logarithm the most simultaneously with described data distribution module output
Compaction algorithms, and N+1 log-compressed result is carried out the total module of log-compressed exported, and module total with log-compressed
Output is connected and according to the sequencing arrangement of corresponding data before compression, N+1 log-compressed result is integrated into the number of a road signal
According to integrating module, wherein, the total module of described log-compressed is by N+1 the output channel with described data distribution module
The log-compressed submodule that number is identical is constituted, and described N is the figure place of the compression result that Data Integration module is exported.
In the enforcement of the present invention arranges, described FPGA can use in the Cyclone IV series that ALTERA company produces
Model is the chip of EP4CE55F23C8.
The construction method of described data distribution module is: 1) by N+1 output channel of data distribution module respectively with
In the total module of log-compressed, the input correspondence of N+1 log-compressed submodule is connected；2) by input data to be compressed with often
The frequency of individual 1 data of clock inputs described data distribution module；3) data distribution module is by the 1st data of the 1st clock
From the 1st paths output, the 2nd data of the 2nd clock are exported from the 2nd paths, until by the N+ of N+1 clock
The N+2 data of N+2 clock, after N+1 paths exports, are exported, one by 1 data again from the 1st paths
Straight so circulation, until diasonograph terminates scanning.
Log-compressed submodule is exactly the monotonicity utilizing logarithmic function, by comparing input data and pre-stored data size
Judge each units of compression result successively, it is achieved log-compressed.If by M-bit data boil down to N bit data, and using YN、
YN-1…Y1Represent each units of compression result Y, compare input data and X for the first time100…0(X100…0Represent and work as y=100 ... 0
Time, the value of x；100 ... 0 represents that highest order is 1, and remaining is the number of 0) size judges highest order Y of compression resultNIf,
Input data are more than X100…0, YNIt is 1；Otherwise, YNIt is 0.Second time compares input data and XYN100…0(YN100 ... 0 represents the highest
Position is YN, a secondary high position is 1, and remaining is the number of 0) size judge time high-order YN-1If input data are more than XYN100…0, YN-1For
1；Otherwise, YN-1It is 0.So repeat to judge, until n-th clock compares the value of lowest order Y1, and will at the N+1 clock
Final compression result " YNYN-1…Y1" output.
The construction method of the total module of described log-compressed is, each log-compressed submodule is receiving data distribution
Each output signal of module, will carry out data process through N+1 clock to received signal, be then output to
Data Integration module.Include as it is shown on figure 3, described data process: divide two-way by the clock signal being used for controlling sequential, a road
Entering read-only storage (ROM) 210 by a not gate 213, another road is directly entered N bit address selector, and described is read-only
The output of memory connects an input of comparator 211, and another input of comparator 211 connects described data and divides
The corresponding output of flow module 1, two outputs of described comparator 211 connect the two of N bit address selector 212 respectively
Individual input, the input of the read-only storage 210 described in output connection of N bit address selector 212, it is right the most also to constitute
The output of number compression submodule.Wherein,
The course of work of described N bit address selector is: when the 1st clock, and the address in N bit address selector is multiple
Position is 2N-1；When the 2nd clock, N bit address selector is with being latched in the output result of comparator in N bit address selector
The highest order of location, casts out lowest order and forms new address；When the 3rd clock, N bit address selector is by the output result of comparator
It is latched in a time high position for address in N bit address selector, casts out lowest order and form new address；Carry out until when the N+1 successively
The output result of comparator is latched in the lowest order of address in N bit address selector by Zhong Shi, N bit address selector, and composition is new
Address, described new address is the compression result of log-compressed submodule output.
The course of work of described read-only storage is: setting x in the storage table of read-only storage as storage value, y is
Storage table address, then by logarithm operation curve y=kloga(x+1) trying to achieve x value, wherein, y value is 0～(2N-1), k and a is
Constant.
The construction method of described Data Integration module is: 1) by N+1 input channel of Data Integration module respectively with
In the total module of log-compressed, the output channel correspondence of N+1 log-compressed submodule is connected.2) Data Integration module is when the 1st
The compression result of the 1st log-compressed submodule is exported by clock from output channel, at the 2nd clock by the 2nd log-compressed
The compression result of module exports from output channel, until the compression of the N+1 log-compressed submodule being tied at the N+1 clock
Fruit exports from output channel, at the N+2 clock by defeated from output channel for the compression result of the N+2 log-compressed submodule
Go out, the most so circulate, until diasonograph terminates scanning.
A concrete example be given below:
Data bits M=16 to be compressed, log-compressed result length N=8.
Data distribution module for being divided into 9 circuit-switched data outputs by input data to be compressed.Described input number to be compressed
The frequency of the most each one data of clock inputs described data distribution module, and described data distribution module is by the 1st clock
1st data export from the 1st paths；2nd data of the 2nd clock are exported from the 2nd paths；Until during by the 9th
9th data of clock are after the 9th paths output, by the 10th data of the 10th clock again from the 1st paths output；One
Straight so circulation, until diasonograph terminates scanning.
9 log-compressed submodules in 9 output channels of described data distribution module module total with log-compressed respectively
It is connected, as first log-compressed submodule receives first data at first clock, exports first at the 9th clock
The compression result of data, and receive the 10th data participation compaction algorithms at next clock namely the 10th clock；Other are right
The mode of operation of number compression submodule is similar with first described log-compressed submodule.
Described log-compressed submodular circuits connects as it is shown on figure 3, to implement process as follows:
First rising edge clock latches input data, and reset signal makes address selector be reset to simultaneously
" 10000000 ", then trailing edge is from the X that ROM OPADD is " 10000000 "10000000, carry out in a comparator with input data
Relatively；
Second rising edge clock comes interim, the comparative result Y of first clock8If (input data read number more than ROM
According to, YNIt is 1；Otherwise, YNIt is 0) it is latched in the highest order of address in address selector, form new address " Y81000000 ", decline
Along time in ROM, read new value according to new address and be input to comparator, carry out second time with former input data and compare, obtain
Secondary high-order Y7；
When the 3rd rising edge clock, in address selector, the highest order of address latches Y8Constant, secondary high-order latch the
Secondary comparative result Y7, form new address " Y8Y71000000 ", in ROM, new value is read according to new address during trailing edge defeated
Enter to comparator, carry out third time with former input data and compare, obtain the 3rd high-order Y6；
Repeat latch and combine new address, until being obtained result by address selector during the 9th clock
“Y8Y7Y6Y5Y4Y3Y2Y1”。
When the tenth rising edge clock arrives, again latch one just by data distribution module come to be compressed defeated
Entering data, reset signal makes address selector be reset to " 10000000 " simultaneously, repeats above step, obtains compression result.
Wherein, in ROM storage table, address is the X of QQRepresent as y=Q, the value of x, can be by logarithm operation curve y=
kloga(x+1) try to achieve.
Whenever there being new data to input, namely during reseting signal reset, log-compressed submodule is just according to said process
Calculate log-compressed result, the log-compressed result output of 9 log-compressed submodules in the total module of the most described log-compressed
Being connected with Data Integration module, the log-compressed result of input is pressed the defeated of many corresponding input data by described Data Integration module
Enter sequencing arrangement final compression result to be exported with the frequency of each one result of clock, it is achieved log-compressed in real time.
Claims (7)
1. the real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method, it is characterised in that on FPGA
Set up the data distribution for input data to be compressed being divided into the output of N+1 circuit-switched data being connected with data input signal respectively
Module, is connected for the data of N+1 paths carry out log-compressed fortune the most simultaneously with described data distribution module output
Calculate, and N+1 log-compressed result is carried out the total module of log-compressed exported, and the output phase of module total with log-compressed
Even N+1 log-compressed result is integrated into the Data Integration of a road signal according to the sequencing arrangement of corresponding data before compression
Module, wherein, the total module of described log-compressed is identical by N+1 the output channel number with described data distribution module
Log-compressed submodule constitute, described N is the figure place of the compression result that Data Integration module is exported.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 1, it is special
Levying and be, the construction method of described data distribution module is:
1) by N+1 log-compressed submodule in N+1 output channel of data distribution module respectively module total with log-compressed
Input correspondence be connected；
2) input data to be compressed are inputted described data distribution module with the frequency of each 1 data of clock；
3) the 1st data of the 1st clock are exported, by the 2nd number of the 2nd clock by data distribution module from the 1st paths
Export according to from the 2nd paths, until by the N+1 data of N+1 clock after N+1 paths exports, by N+2
The N+2 data of clock from the 1st paths output, the most so circulate again, until diasonograph terminates scanning.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 1, it is special
Levying and be, the construction method of the total module of described log-compressed is, each log-compressed submodule is receiving data distribution
Each output signal of module, will carry out data process through N+1 clock to received signal, be then output to
Data Integration module.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 3, it is special
Levying and be, described data process and include: divide two-way by the clock signal being used for controlling sequential, and a not gate of leading up to enters
Read-only storage, another road is directly entered N bit address selector, and the output of described read-only storage connects the one of comparator
Individual input, another input of comparator connects the corresponding output of described data distribution module, described comparator
Two outputs connect two inputs of N bit address selector respectively, described in the output of N bit address selector connects
The input of read-only storage, the most also constitutes the output of log-compressed submodule.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 4, it is special
Levying and be, the course of work of described N bit address selector is:
When the 1st clock, the address reset in N bit address selector is 2N-1；When the 2nd clock, N bit address selector
The output result of comparator is latched in the highest order of address in N bit address selector, casts out lowest order and form new address；?
During 3 clocks, the output result of comparator is latched in a time high position for address, house in N bit address selector by N bit address selector
Lowest order is gone to form new address；Carry out successively until during N+1 clock, N bit address selector is by the output result of comparator
Being latched in the lowest order of address in N bit address selector, form new address, described new address is the output of log-compressed submodule
Compression result.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 4, it is special
Levying and be, the course of work of described read-only storage is: setting x in the storage table of read-only storage as storage value, y is for depositing
Storage table address, then by logarithm operation curve y=kloga(x+1) trying to achieve x value, wherein, y value is 0～(2N-1), k and a is normal
Number.
The construction method of the real-time log compression circuit for medical ultrasonic equipment the most according to claim 1, it is special
Levying and be, the construction method of described Data Integration module is:
1) by N+1 log-compressed submodule in N+1 input channel of Data Integration module respectively module total with log-compressed
Output channel correspondence be connected；
2) compression result of the 1st log-compressed submodule is exported from output channel by Data Integration module at the 1st clock,
The compression result of the 2nd log-compressed submodule is exported by the 2nd clock from output channel, until at the N+1 clock by N
The compression result of+1 log-compressed submodule exports from output channel, at the N+2 clock by the N+2 log-compressed submodule
The compression result of block exports from output channel, the most so circulates, until diasonograph terminates scanning.
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| CN110840483B (en) * | 2019-11-15 | 2022-03-18 | 徐州市凯信电子设备有限公司 | Real-time logarithmic compression method and system for digital ultrasonic diagnostic apparatus |
| CN114698368A (en) * | 2020-10-26 | 2022-07-01 | 京东方科技集团股份有限公司 | Signal processing method, readable storage medium and ultrasonic imaging system |
| CN112998750B (en) * | 2021-02-22 | 2021-09-14 | 深圳华声医疗技术股份有限公司 | Ultrasonic image synthesis method and device, ultrasonic equipment and storage medium |
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| CN1231835C (en) * | 2003-02-28 | 2005-12-14 | 清华大学 | Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA |
| CN1952922A (en) * | 2006-11-17 | 2007-04-25 | 徐州市凯信电子设备有限公司 | A new logarithmic compression method based on digital ultrasound diagnostic apparatus |
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