CN104306027A - Medical ultrasonic diagnostic instrument real-time logarithmic compression circuit establishment method based on FPGA - Google Patents
Medical ultrasonic diagnostic instrument real-time logarithmic compression circuit establishment method based on FPGA Download PDFInfo
- Publication number
- CN104306027A CN104306027A CN201410675185.6A CN201410675185A CN104306027A CN 104306027 A CN104306027 A CN 104306027A CN 201410675185 A CN201410675185 A CN 201410675185A CN 104306027 A CN104306027 A CN 104306027A
- Authority
- CN
- China
- Prior art keywords
- data
- compression
- module
- output
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007906 compression Methods 0.000 title claims abstract description 144
- 230000006835 compression Effects 0.000 title claims abstract description 144
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000010354 integration Effects 0.000 claims description 21
- 230000000630 rising effect Effects 0.000 abstract description 6
- 238000010276 construction Methods 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 210000004872 soft tissue Anatomy 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007907 direct compression Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 210000001519 tissue Anatomy 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/13—Tomography
- A61B8/14—Echo-tomography
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/5207—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of raw data to produce diagnostic data, e.g. for generating an image
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/5215—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of medical diagnostic data
- A61B8/5223—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of medical diagnostic data for extracting a diagnostic or physiological parameter from medical diagnostic data
Landscapes
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Engineering & Computer Science (AREA)
- Biomedical Technology (AREA)
- Medical Informatics (AREA)
- Veterinary Medicine (AREA)
- Biophysics (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Pathology (AREA)
- Radiology & Medical Imaging (AREA)
- Public Health (AREA)
- Heart & Thoracic Surgery (AREA)
- Physics & Mathematics (AREA)
- Molecular Biology (AREA)
- Surgery (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Physiology (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
Abstract
Provided is a medical ultrasonic diagnostic instrument real-time logarithmic compression circuit establishment method based on an FPGA. A data distribution module connected with a data input signal, a total logarithmic compression module connected with the output of the data distribution module, and a data integrating module connected with the output of the total logarithmic compression module are established on the FPGA, wherein the total logarithmic compression module is composed of logarithmic compression sub-modules with the number equal to that of N+1 output channels of the data distribution module, and N is the digit number of compression results output by the data integrating module. Through the method, one logarithmic compression result is output every time a clock rising edge comes, and the real-time performance of ultrasonic echo digital signals in the logarithmic compression treatment process is guaranteed. The dynamic changing range of input signals can be effectively compressed through logarithmic compression, small signals are enhanced, and the real-time treatment requirement is met. The space needed by a ROM is 28*16 bit, and occupied hardware resources can be effectively reduced.
Description
Technical Field
The invention relates to a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus. In particular to a method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA
Background
The medical ultrasonic diagnostic apparatus is mainly used for carrying out real-time and dynamic tomography on human soft tissues. The medical ultrasonic diagnostic system transmits ultrasonic waves through an ultrasonic transducer, and also receives ultrasonic echo signals reflected back after being attenuated by tissue absorption, scattering and the like through the transducer. The echo signals are converted into digital signals through an A/D chip, digital signal processing such as filtering, wave detection, logarithmic compression and the like is completed on the FPGA to respectively realize noise suppression, signal demodulation and dynamic range compression, and finally the signals are sent to a back-end system to display ultrasonic images.
Among them, logarithmic compression is an essential process in the ultrasonic echo signal processing. The absorption coefficient of each soft tissue of the human body to the ultrasound is 0.6-0.7dB/cm.MHz, so that the dynamic range of the ultrasonic echo signal reaches more than 100dBAnd the display on the terminal display is difficult. The logarithmic compression utilizes a nonlinear relation to compress signals with a large dynamic range, and meanwhile, has a stretching effect on weak echo signals capable of reflecting human body structure details relative to other strong signals, and plays a role in increasing contrast. The traditional logarithm compression adopts the direct compression of a lookup table, and if 16-bit data is compressed into 8-bit data, the size of the required lookup table is 216X 8bit, the occupied hardware resources are too large. The logarithm compression method adopted in the demodulation and logarithm compression system (03104777.7) for the medical ultrasonic imaging system based on the FPGA in Chinese patent requires 9 clocks to obtain a compression result, and the last 8 data to be compressed input during the 9 clocks cannot be processed in time, so that when the method is applied to an actual product, the data processing speed and the imaging real-time performance are seriously influenced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA, which can realize compression of different curves only by replacing data in a ROM.
The technical scheme adopted by the invention is as follows: a method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA comprises respectively establishing a data shunt module connected with a data input signal and used for dividing input data to be compressed into N +1 paths of data output on FPGA, a logarithm compression total module connected with the output of the data distribution module and used for respectively and simultaneously carrying out logarithm compression operation on the data of the N +1 channels and outputting N +1 logarithm compression results, and a data integration module connected with the output of the logarithm compression total module and used for integrating the N +1 logarithm compression results into a signal according to the sequence of the corresponding data before compression, the total log compression module is composed of log compression submodules with the same number as the N +1 output channels of the data shunting module, and N is the bit number of the compression result output by the data integration module.
The construction method of the data distribution module comprises the following steps:
1) respectively and correspondingly connecting N +1 output channels of the data distribution module with input ends of N +1 logarithm compression sub-modules in the logarithm compression total module;
2) inputting input data to be compressed into the data shunting module at the frequency of 1 data per clock;
3) the data shunting module outputs the 1 st data of the 1 st clock from the 1 st channel, outputs the 2 nd data of the 2 nd clock from the 2 nd channel, and outputs the N +2 nd data of the N +2 th clock from the 1 st channel again after outputting the N +1 th data of the N +1 th clock from the N +1 th channel, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
The construction method of the total log compression module is that each log compression submodule receives each output signal of the data shunt module, processes the data of the received signals through N +1 clocks, and then outputs the signals to the data integration module.
The data processing comprises the following steps: the clock signal for controlling the time sequence is divided into two paths, one path enters a read-only memory through a NOT gate, the other path directly enters an N-bit address selector, the output end of the read-only memory is connected with one input end of a comparator, the other input end of the comparator is connected with the corresponding output end of the data shunting module, the two output ends of the comparator are respectively connected with the two input ends of the N-bit address selector, the output end of the N-bit address selector is connected with the input end of the read-only memory, and meanwhile, the output end of a logarithm compression submodule is formed.
The working process of the N-bit address selector is as follows:
at 1 st clock, the address in the N-bit address selector is reset to 2N-1(ii) a At the 2 nd clock, the N-bit address selector latches the output result of the comparator in the highest order of the address in the N-bit address selectorDiscarding the lowest order bits to form a new address; at the 3 rd clock, the N-bit address selector locks the output result of the comparator in the second highest bit of the address in the N-bit address selector, and the lowest bit is cut off to form a new address; and sequentially locking the output result of the comparator in the lowest order of the address in the N-bit address selector by the N-bit address selector until the (N +1) th clock to form a new address, wherein the new address is the compression result output by the logarithm compression submodule.
The working process of the read-only memory is as follows: if x is set as a storage value and y is set as a storage table address in a storage table of the read-only memory, the logarithm operation curve y is kloga(x +1) obtaining a value of x, wherein y is 0 to (2)N-1), k and a are constants.
The construction method of the data integration module comprises the following steps:
1) and correspondingly connecting the N +1 input channels of the data integration module with the output channels of the N +1 logarithm compression sub-modules in the logarithm compression total module respectively.
2) The data integration module outputs the compression result of the 1 st logarithmic compression sub-module from the output channel at the 1 st clock, outputs the compression result of the 2 nd logarithmic compression sub-module from the output channel at the 2 nd clock until the compression result of the (N +1) th logarithmic compression sub-module is output from the output channel at the (N +1) th clock, and outputs the compression result of the (N + 2) th logarithmic compression sub-module from the output channel at the (N + 2) th clock, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
The invention relates to a method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA, which adopts a circuit that the FPGA can repeatedly change the configuration and meets the high-speed processing of large-data-volume complex operation. The invention can realize that when each clock rising edge arrives, a log compression result is output, and the real-time performance of the ultrasonic echo digital signal during log compression processing is ensured. The logarithmic compression can effectively compress the dynamic change range of the input signal, enhance small signals and meet the requirement of real-time processing. Wherein the space required for the ROM is 28And 16 bits, the occupation of hardware resources can be effectively reduced. The invention can realize the compression of different curves only by replacing the data in the ROM, and has good portability.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a graph of logarithmic operation;
FIG. 3 is a schematic diagram of the structure of the log compression submodule in the present invention.
In the drawings
1: the data distribution module 2: logarithm compression general module
21-29: log compression submodule 3: data integration module
210: the read only memory 211: comparator with a comparator circuit
212: n-bit address selector 213: NOT gate
Detailed Description
The method for constructing the real-time logarithmic compression circuit of the medical ultrasonic diagnostic apparatus based on the FPGA of the present invention is explained in detail with reference to the embodiments and the drawings.
First, it is explained that the logarithm compression is essentially based on the logarithm operation curve y-kloga(x+1),(a>1) The input signal x is modulated in a non-linear way, the value of a determines the shape of the curve, and the value of k depends on the number of bits of the input signal x. As shown in fig. 2, the logarithmic operation curve is a monotonically increasing curve, so when x is1<x2When necessary, there is y1<y2Wherein y is1、y2Are respectively provided withShould x take x1、x2Time y is klogaThe value of (x + 1).
As shown in FIG. 1, the invention relates to a method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA, a data shunt module which is connected with a data input signal and is used for dividing input data to be compressed into N +1 paths of data output is respectively established on the FPGA, a logarithm compression total module connected with the output of the data distribution module and used for respectively and simultaneously carrying out logarithm compression operation on the data of the N +1 channels and outputting N +1 logarithm compression results, and a data integration module connected with the output of the logarithm compression total module and used for integrating the N +1 logarithm compression results into a signal according to the sequence of the corresponding data before compression, the total log compression module is composed of log compression submodules with the same number as the N +1 output channels of the data shunting module, and N is the bit number of the compression result output by the data integration module.
In the embodiment of the invention, the FPGA may adopt a chip of EP4CE55F23C8 in Cyclone IV series manufactured by ALTERA.
The construction method of the data distribution module comprises the following steps: 1) respectively and correspondingly connecting N +1 output channels of the data distribution module with input ends of N +1 logarithm compression sub-modules in the logarithm compression total module; 2) inputting input data to be compressed into the data shunting module at the frequency of 1 data per clock; 3) the data shunting module outputs the 1 st data of the 1 st clock from the 1 st channel, outputs the 2 nd data of the 2 nd clock from the 2 nd channel, and outputs the N +2 nd data of the N +2 th clock from the 1 st channel again after outputting the N +1 th data of the N +1 th clock from the N +1 th channel, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
The logarithm compression submodule utilizes monotonicity of a logarithm function and sequentially judges each digit of a compression result by comparing the size of input data with the size of prestored data to realize logarithm compression. If M-bit data is compressed into N-bit data, and Y is usedN、YN-1…Y1Representing the respective number of bits of the compression result Y, comparing the input data with X for the first time100…0(X100…0Represents the value of x when y is 100 … 0; 100 … 0 represents the number with the highest bit being 1 and the remaining bits being 0) determines the highest bit Y of the compression resultNIf the input data is greater than X100…0，YNIs 1; conversely, YNIs 0. Comparing the input data with X for the second timeYN100…0(YN100 … 0 indicates the highest bit is YNNumber of the second highest bit 1 and the remaining bits 0) is determined as the second highest bit YN-1If the input data is greater than XYN100…0，YN-1Is 1; conversely, YN-1Is 0. The determination is repeated until the Nth clock compares the lowest bit Y1 and the final compression result Y is obtained at the N +1 th clockNYN-1…Y1And outputting.
The construction method of the total log compression module is that each log compression submodule receives each output signal of the data shunt module, processes the data of the received signals through N +1 clocks, and then outputs the signals to the data integration module. As shown in fig. 3, the data processing includes: the clock signal for controlling the time sequence is divided into two paths, one path enters a Read Only Memory (ROM)210 through a NOT gate 213, the other path directly enters an N-bit address selector, the output end of the ROM is connected with one input end of a comparator 211, the other input end of the comparator 211 is connected with the corresponding output end of the data shunting module 1, two output ends of the comparator 211 are respectively connected with two input ends of the N-bit address selector 212, the output end of the N-bit address selector 212 is connected with the input end of the ROM 210, and meanwhile, the output end of a logarithm compression submodule is also formed. Wherein,
the working process of the N-bit address selector is as follows: at 1 st clock, the address in the N-bit address selector is reset to 2N-1(ii) a At the 2 nd clock, the N-bit address selector latches the output result of the comparator in the highest bit of the address in the N-bit address selector, and the most significant bit is discardedThe low bit constitutes the new address; at the 3 rd clock, the N-bit address selector locks the output result of the comparator in the second highest bit of the address in the N-bit address selector, and the lowest bit is cut off to form a new address; and sequentially locking the output result of the comparator in the lowest order of the address in the N-bit address selector by the N-bit address selector until the (N +1) th clock to form a new address, wherein the new address is the compression result output by the logarithm compression submodule.
The working process of the read-only memory is as follows: if x is set as a storage value and y is set as a storage table address in a storage table of the read-only memory, the logarithm operation curve y is kloga(x +1) obtaining a value of x, wherein y is 0 to (2)N-1), k and a are constants.
The construction method of the data integration module comprises the following steps: 1) and correspondingly connecting the N +1 input channels of the data integration module with the output channels of the N +1 logarithm compression sub-modules in the logarithm compression total module respectively. 2) The data integration module outputs the compression result of the 1 st logarithmic compression sub-module from the output channel at the 1 st clock, outputs the compression result of the 2 nd logarithmic compression sub-module from the output channel at the 2 nd clock until the compression result of the (N +1) th logarithmic compression sub-module is output from the output channel at the (N +1) th clock, and outputs the compression result of the (N + 2) th logarithmic compression sub-module from the output channel at the (N + 2) th clock, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
One specific example is given below:
the number of bits M of the data to be compressed is 16, and the number of bits N of the result of logarithmic compression is 8.
The data distribution module is used for dividing input data to be compressed into 9 paths of data to be output. The input data to be compressed is input into the data shunting module at the frequency of one data per clock, and the data shunting module outputs the 1 st data of the 1 st clock from the 1 st channel; outputting the 2 nd data of the 2 nd clock from the 2 nd path; outputting 10 th data of 10 th clock from the 1 st channel again after outputting 9 th data of 9 th clock from the 9 th channel; the above steps are repeated until the ultrasonic diagnostic apparatus finishes scanning.
The data distribution module has 9 output channels respectively connected with 9 log compression submodules in the log compression total module, for example, the first log compression submodule receives the first data at the first clock, outputs the compression result of the first data at the 9 th clock, and receives the 10 th data at the next clock, namely the 10 th clock to participate in the compression operation; the other logarithmic compression sub-modules operate in a mode similar to the first logarithmic compression sub-module.
The logarithmic compression submodule is connected with a circuit shown in fig. 3, and the specific implementation process is as follows:
the first clock rising edge latches an input data, and the reset signal resets the address selector to "10000000", and the falling edge outputs an X with address "10000000" from the ROM10000000Comparing with input data in a comparator;
when the rising edge of the second clock comes, the comparison result Y of the first clock8(if the input data is larger than the ROM read data, YNIs 1; conversely, YN0) is latched in the address selector to form the new address "Y81000000 ″, reading new value from ROM according to new address at falling edge, inputting to comparator, comparing with original input data for the second time to obtain second high-order Y7；
On the rising edge of the third clock, the most significant bit of the address in the address selector latches Y8The second higher order latch does not change, and the second comparison result Y is7Form a new address "Y8Y71000000 ″, reading new value from ROM according to new address at falling edge, inputting to comparator, comparing with original input data for the third time to obtain the third high-order Y6；
Repeatedly latching and combining new addresses until the ninth clock time the result "Y" is obtained by the address selector8Y7Y6Y5Y4Y3Y2Y1”。
When the rising edge of the tenth clock comes, the input data to be compressed which is just sent by the data shunting module is re-latched, meanwhile, the reset signal enables the address selector to be reset to be 10000000, and the steps are repeated to obtain the compression result.
Wherein X with address Q in ROM memory tableQRepresents the value of x when y is Q, which can be calculated from a logarithmic curve y kloga(x + 1).
When new data is input, namely a reset signal is reset, the logarithm compression submodule calculates a logarithm compression result according to the process, meanwhile, logarithm compression results of 9 logarithm compression submodules in the logarithm compression total module are output and connected with the data integration module, the data integration module arranges the input logarithm compression results according to the input sequence of multiple corresponding input data, and the final compression result is output at the frequency of one result per clock, so that real-time logarithm compression is realized.
Claims (7)
1. A method for constructing a real-time logarithmic compression circuit of a medical ultrasonic diagnostic apparatus based on FPGA is characterized in that, a data shunt module which is connected with a data input signal and is used for dividing input data to be compressed into N +1 paths of data output is respectively established on the FPGA, a logarithm compression total module connected with the output of the data distribution module and used for respectively and simultaneously carrying out logarithm compression operation on the data of the N +1 channels and outputting N +1 logarithm compression results, and a data integration module connected with the output of the logarithm compression total module and used for integrating the N +1 logarithm compression results into a signal according to the sequence of the corresponding data before compression, the total log compression module is composed of log compression submodules with the same number as the N +1 output channels of the data shunting module, and N is the bit number of the compression result output by the data integration module.
2. The method for constructing the real-time logarithmic compression circuit for the medical ultrasonic diagnostic apparatus according to claim 1, wherein the data splitting module is constructed by:
1) respectively and correspondingly connecting N +1 output channels of the data distribution module with input ends of N +1 logarithm compression sub-modules in the logarithm compression total module;
2) inputting input data to be compressed into the data shunting module at the frequency of 1 data per clock;
3) the data shunting module outputs the 1 st data of the 1 st clock from the 1 st channel, outputs the 2 nd data of the 2 nd clock from the 2 nd channel, and outputs the N +2 nd data of the N +2 th clock from the 1 st channel again after outputting the N +1 th data of the N +1 th clock from the N +1 th channel, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
3. The method for constructing the real-time logarithmic compression circuit for the medical ultrasonic diagnostic apparatus according to claim 1, wherein the total logarithmic compression module is constructed in such a way that each logarithmic compression submodule, upon receiving each output signal of the data splitting module, processes the received signal by N +1 clocks and then outputs the processed signal to the data integration module.
4. The method for constructing a real-time logarithmic compression circuit for a medical ultrasonic diagnostic apparatus as set forth in claim 3, wherein the data processing comprises: the clock signal for controlling the time sequence is divided into two paths, one path enters a read-only memory through a NOT gate, the other path directly enters an N-bit address selector, the output end of the read-only memory is connected with one input end of a comparator, the other input end of the comparator is connected with the corresponding output end of the data shunting module, the two output ends of the comparator are respectively connected with the two input ends of the N-bit address selector, the output end of the N-bit address selector is connected with the input end of the read-only memory, and meanwhile, the output end of a logarithm compression submodule is formed.
5. The method for constructing the real-time logarithmic compression circuit for the medical ultrasonic diagnostic apparatus as claimed in claim 4, wherein the working process of the N-bit address selector is as follows:
at 1 st clock, the address in the N-bit address selector is reset to 2N-1(ii) a At the 2 nd clock, the N-bit address selector locks the output result of the comparator in the highest bit of the address in the N-bit address selector, and the lowest bit is cut off to form a new address; at the 3 rd clock, the N-bit address selector locks the output result of the comparator in the second highest bit of the address in the N-bit address selector, and the lowest bit is cut off to form a new address; and sequentially locking the output result of the comparator in the lowest order of the address in the N-bit address selector by the N-bit address selector until the (N +1) th clock to form a new address, wherein the new address is the compression result output by the logarithm compression submodule.
6. The method for constructing the real-time logarithmic compression circuit for the medical ultrasonic diagnostic apparatus according to claim 4, wherein the working process of the read only memory is as follows: if x is set as a storage value and y is set as a storage table address in a storage table of the read-only memory, the logarithm operation curve y is kloga(x +1) obtaining a value of x, wherein y is 0 to (2)N-1), k and a are constants.
7. The method for constructing the real-time logarithmic compression circuit for the medical ultrasonic diagnostic apparatus according to claim 1, wherein the data integration module is constructed by:
1) and correspondingly connecting the N +1 input channels of the data integration module with the output channels of the N +1 logarithm compression sub-modules in the logarithm compression total module respectively.
2) The data integration module outputs the compression result of the 1 st logarithmic compression sub-module from the output channel at the 1 st clock, outputs the compression result of the 2 nd logarithmic compression sub-module from the output channel at the 2 nd clock until the compression result of the (N +1) th logarithmic compression sub-module is output from the output channel at the (N +1) th clock, and outputs the compression result of the (N + 2) th logarithmic compression sub-module from the output channel at the (N + 2) th clock, and the cycle is repeated until the ultrasonic diagnostic apparatus finishes scanning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410675185.6A CN104306027B (en) | 2014-11-21 | 2014-11-21 | The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410675185.6A CN104306027B (en) | 2014-11-21 | 2014-11-21 | The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104306027A true CN104306027A (en) | 2015-01-28 |
| CN104306027B CN104306027B (en) | 2016-08-24 |
Family
ID=52361451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410675185.6A Expired - Fee Related CN104306027B (en) | 2014-11-21 | 2014-11-21 | The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104306027B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110840483A (en) * | 2019-11-15 | 2020-02-28 | 徐州市凯信电子设备有限公司 | Real-time logarithmic compression method and system for digital ultrasonic diagnostic apparatus |
| CN112998750A (en) * | 2021-02-22 | 2021-06-22 | 深圳华声医疗技术股份有限公司 | Ultrasonic image synthesis method and device, ultrasonic equipment and storage medium |
| WO2022087781A1 (en) * | 2020-10-26 | 2022-05-05 | 京东方科技集团股份有限公司 | Signal processing method, readable storage medium and ultrasound imaging system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4241608A (en) * | 1978-01-24 | 1980-12-30 | Unirad Corporation | Ultrasonic scanner |
| JP2000185041A (en) * | 1998-10-14 | 2000-07-04 | Toshiba Corp | Ultrasonic diagnostic apparatus |
| CN1431581A (en) * | 2003-02-28 | 2003-07-23 | 清华大学 | Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA |
| CN1952922A (en) * | 2006-11-17 | 2007-04-25 | 徐州市凯信电子设备有限公司 | A new logarithmic compression method based on digital ultrasound diagnostic apparatus |
-
2014
- 2014-11-21 CN CN201410675185.6A patent/CN104306027B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4241608A (en) * | 1978-01-24 | 1980-12-30 | Unirad Corporation | Ultrasonic scanner |
| JP2000185041A (en) * | 1998-10-14 | 2000-07-04 | Toshiba Corp | Ultrasonic diagnostic apparatus |
| CN1431581A (en) * | 2003-02-28 | 2003-07-23 | 清华大学 | Compressing subsystem by demodulation and logarithm being utilized in medical ultrasonic imaging system based on FPGA |
| CN1952922A (en) * | 2006-11-17 | 2007-04-25 | 徐州市凯信电子设备有限公司 | A new logarithmic compression method based on digital ultrasound diagnostic apparatus |
Non-Patent Citations (1)
| Title |
|---|
| 王立伟等: "眼科高频环阵超声波数字化成像技术的研究", 《北京生物医学工程》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110840483A (en) * | 2019-11-15 | 2020-02-28 | 徐州市凯信电子设备有限公司 | Real-time logarithmic compression method and system for digital ultrasonic diagnostic apparatus |
| CN110840483B (en) * | 2019-11-15 | 2022-03-18 | 徐州市凯信电子设备有限公司 | Real-time logarithmic compression method and system for digital ultrasonic diagnostic apparatus |
| WO2022087781A1 (en) * | 2020-10-26 | 2022-05-05 | 京东方科技集团股份有限公司 | Signal processing method, readable storage medium and ultrasound imaging system |
| CN112998750A (en) * | 2021-02-22 | 2021-06-22 | 深圳华声医疗技术股份有限公司 | Ultrasonic image synthesis method and device, ultrasonic equipment and storage medium |
| CN112998750B (en) * | 2021-02-22 | 2021-09-14 | 深圳华声医疗技术股份有限公司 | Ultrasonic image synthesis method and device, ultrasonic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104306027B (en) | 2016-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104306027B (en) | The real-time log compression circuit of medical ultrasonic equipment based on FPGA builds method | |
| US9305369B2 (en) | Method and system for data compression | |
| CN104739448A (en) | Ultrasonic imaging method and device | |
| WO2024146622A1 (en) | Intravascular ultrasound imaging method and apparatus, computer device and storage medium | |
| TWI653033B (en) | Ultrasonic imaging system and ultrasonic imaging method | |
| WO2021074015A1 (en) | Method and apparatus for deep learning-based ultrasound beamforming | |
| Li et al. | Ultrasound beamforming using compressed data | |
| CN109674493A (en) | Method, system and the equipment of medical supersonic automatic tracing carotid artery vascular | |
| CN106024006A (en) | Wavelet-transform-based cetacean sound signal denoising method and device | |
| US20150094591A1 (en) | Speckle and noise reduction in ultrasound images | |
| KR20240130113A (en) | Low-cost, high-performance ultrasound imaging probe | |
| Levesque et al. | Real-time hand-held ultrasound medical-imaging device based on a new digital quadrature demodulation processor | |
| Kozhemyak et al. | Reducing the root-mean-square error at signal restoration using discrete and random changes in the sampling rate for the compressed sensing problem | |
| TWI613459B (en) | Ultrasound beamforming system and method thereof and beamforming circuit | |
| Mayasandra et al. | A distributed arithmetic hardware architecture for real-time hough-transform-based segmentation | |
| TWI521225B (en) | Ultrasound scanning method and ultrasound scanning system | |
| CN105787880B (en) | A kind of palm color ultrasonic image processing method based on data feedback | |
| Zhou et al. | Medical high-frequency ultrasound imaging using Golay-coded pulse excitation | |
| CN108389174B (en) | Ultrasonic imaging system and ultrasonic imaging method | |
| Wagner et al. | Compressed beamforming with applications to ultrasound imaging | |
| CN110956136A (en) | Hydrophone signal denoising method based on ESMD and roughness penalty smoothing technology | |
| US20120108964A1 (en) | Performing gain control process based on application in ultrasound system | |
| TWI453404B (en) | Ultrasound imaging system and image processing method thereof | |
| CN204890032U (en) | GPU removes ultrasonic instrument | |
| CN105976323A (en) | Image processing method for palm color Doppler ultrasound |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160824 Termination date: 20211121 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |