CN1227409A - Method and structure for contact to copper metallization in insulating via on semiconductor - Google Patents
Method and structure for contact to copper metallization in insulating via on semiconductor Download PDFInfo
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- CN1227409A CN1227409A CN 99101288 CN99101288A CN1227409A CN 1227409 A CN1227409 A CN 1227409A CN 99101288 CN99101288 CN 99101288 CN 99101288 A CN99101288 A CN 99101288A CN 1227409 A CN1227409 A CN 1227409A
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Abstract
The invention provides a forming method of a contact to a copper metal inside an insulating layer via on a semiconductor wafer. This contact forming method includes steps comprising forming a wafer having a patterned copper layer, forming an insulating film on the copper layer, forming a via in the insulating film, forming a wafer in reducing atmosphere for reducing a copper oxide on the copper in the via, to produce a copper, and bringing the wafer into contact with the copper inside the via, without exposing the wafer to the oxidizing environment but to make a liner adhere to the wafer. This contact forming method can solve the problem of copper bounce detected in the via cleaned up by conventional sputtering process. In addition, the liner is selected for the adhesion and the avoidance of copper diffusion as well.
Description
The present invention relates to semiconductor element on the contacting of copper wiring.The tight contact that provides between copper wiring and the following one deck metal layer is provided, and the while can be avoided the method to the copper pollution of insulator.More specifically relate to the technology that copper contact surface on the integrated circuit (IC) chip removes cupric oxide.
The copper wiring has than the remarkable low resistivity of conventional aluminium wiring on the integrated circuit, and is hopeful to obtain the quite chip of high speed.Wiring on the chip is to make by being insulated a layer metal pattern layer that separates, and said insulating barrier has window or the through hole that selectively allows metal interlevel to connect.After leaving these through holes, copper just is exposed in the air, forms cupric oxide this moment easily on copper.This cupric oxide is the root that has a resistance, or even hinder and the electrically contacting of following layer of metal, so must before layer of metal under the deposit, it be removed.
It is effectively adopting for example wet etching agent such as hydrofluoric acid to remove cupric oxide before the metal deposit.But cupric oxide can be regenerated fast and is longer than on the copper surface between HF acid treatment and metal deposit subsequently.
At the same vacuum processing chamber that is used for layer of metal under the deposit then, adopt argon sputtering etching cleaning to have through hole on the semiconductor chip of aluminum metallization layers, be effective for the removal of aluminium oxide.This technology also can be used to remove cupric oxide.Because between oxide removal step and depositing step, avoided being exposed to oxidation environment, eliminated the problem of reoxidizing.But the inventor recognizes that argon sputter meeting generation is not the problem of problem for aluminium for copper, and is as described below.
So, need a kind of better solution, so that the oxide-free interface is provided, protect the copper that does not splash on the through-hole side wall simultaneously between metal layer, and do not increase treatment step, following the present invention can provide such method.
Therefore, the purpose of this invention is to provide the another kind of argon sputter clean method of removing the oxide in the through hole, this method is applicable to the copper metallization wafer.
Another purpose of the present invention provides the cupric oxide in a kind of through hole of removing insulating barrier on the semiconductor chip and copper can be splashed to technology on the through-hole side wall.
The invention has the advantages that, can remove cupric oxide and not increase treatment step, with protection copper or through-hole side wall before oxide removal.
Method that utilize to handle the semiconductor wafer with copper metallization can realize these and other objects of the present invention, feature and advantage, and said method may further comprise the steps: provide to have the copper layer of composition and the wafer of the insulating barrier on the said copper layer; In said insulating barrier, provide through hole, wherein may form cupric oxide on the copper of said through hole being exposed to; Said wafer is placed process chamber; In said process chamber, provide reducing environment, being elemental copper with said copper oxide reduction; Wafer be not exposed under the condition of oxidation environment conductor deposited in said through hole.
In addition, the present invention includes a kind of semiconductor structure, this structure comprises: the copper layer of composition; Insulating barrier on the said copper layer; Lead to the through hole of said copper layer in the said insulating barrier, said through hole comprises the sidewall that is made of said insulating barrier; Cover the conductive liner on the elemental copper surface of the said copper layer in the said through hole, said conductive liner also covers on the said sidewall, and wherein said lining provides and stopped do not have copper directly to contact with said sidewall to what copper spread.
Fig. 1 a is sputtering etching with the profile of the through hole on the wafer that has copper metal line behind the cupric oxide on the cleaning copper metallic face, has showed copper that the inventor the recognizes problem of splashing.
Fig. 1 b is the profile of the method for the copper that do not splash on the protective side wall that provides in the US patent application 08/858139.
Fig. 2 a-2f is a profile of showing processing step of the present invention.
Fig. 3 a-3c is the profile that is used to handle the process chamber of wafer of the present invention.
Fig. 4 is a profile of realizing bimetal mosaic structure of the present invention.
Fig. 5 is a profile of realizing inclined wall through-hole structure of the present invention.
The inventor recognizes that the sputtering etching meeting is splashed to copper on the sidewall of each through hole, pollutes through-hole side wall, makes to have undesired copper on it, as shown in Figure 1a.The inventor recognizes that also the copper that is splashed on the sidewall that does not add protection can move by insulating barrier then, reduces the effect of insulating barrier, or these copper can move to silicon layer, causes the gate oxide electric leakage, has reduced the reliability of gate oxide, or has caused junction leakage.
People's such as the common Geffken of transferring US patent application 08/85813 is by providing barrier material 5 in via bottoms with along through-hole side wall 6 on cupric oxide; protect these sidewalls in argon sputtering etching, do not splashed on copper; the problem thereby solution copper splashes is shown in Fig. 1 b.Barrier material 5 can be thin layers such as tantalum, tantalum nitride, tungsten nitride, tungsten nitride silicon, tantalum nitride silicon, titanium silicon nitride or silicon nitride.By this technology, leave through hole 6 after, deposition preventing material 5.Directly corrode barrier material 5 then, remove barrier material 5 from horizontal surface.Directly barrier material had both been removed in corrosion, had also removed the cupric oxide that exposes thus.Can also carry out the sputtering etching step, to leave the opening of copper wiring 3.Directly the corrosion or the sputtering etching step during, barrier material 5 protective side wall 6 does not effectively contact with the copper that sputters.Yet this technology comprises additional deposit and direct corrosion step, has improved production cost.
The present invention solves the problem of splashing by saving the argon sputter, and among the present invention, cupric oxide is original copper surface by electronation.Then, under the condition that is not exposed to oxidizing atmosphere,, the wafer of going back native copper carries out ensuing metal deposit to being arranged in the through hole.Also the chemical reaction of native copper is without any mechanism, and in the argon sputter, copper can splash along insulative sidewall.So, do not need to provide the additional step of side wall protective layer in the reduction step.In addition, owing to avoided reoxidizing the additional treatment step on the copper surface that do not need protection.
The first step provides electronic component, for example has the semiconductor wafer 20 of copper layer 22 and insulating barrier 24, shown in Fig. 2 a.Insulating barrier 24 is made of silicon dioxide or polymer.Silicon dioxide utilizes as method deposits such as CVD or plasma-enhanced CVDs.Insulating barrier 24 can also by can spin coating or the material of curing constitute for example spin-coating glass or organic polymer etc.Insulators such as silicon dioxide can contain just like dopants such as phosphorus or boron.Polymer comprises as materials such as polyimides and hydrogenation silsequioxane.
Then, utilize the standard photoetching composition and, in insulating barrier 24, form through hole 26, shown in Fig. 2 b with sidewall 26 ' as etching processs such as wet etching or plasma etchings.Through hole 26 can have the tapered sidewalls that is used for conventional interconnection that utilizes known list or dual damascene process, or is used for the vertical sidewall of stud interconnect.Do not pay particular attention to the oxidation of avoiding forming through hole 26 back exposed copper surface.So, easily on copper wiring layer 22, form thin copper oxide 28 in the place that copper is exposed to through hole 26.
Next step places process chamber 30 with wafer 20, and reducing environment 32 is provided, and may be formed at cupric oxide 28 in the through hole 26 with reduction, shown in Fig. 2 c and 3a.Reductive copper oxide 28, forming element copper surface 22 '.
In reducing process, utilize as H
2Form gas (N
2And H
2), reducing gas electronation cupric oxide 28 such as NOx or CO.Also can be with atomic hydrogen or hydrogen ion.It is the pure hydrogen of about 10T-760T that pressure is provided, under 350 ℃, with about 1-10 minute reductive copper oxide, forming element copper surface 22 '.It is better than low pressure to have found to work under the high pressure of 500T at least.Can obtain good result in about 4 minutes with 500T.Evaporation and take out the reduction reaction product water with pump.In addition, can use H
2Plasma or have H
2With plasma, provide hydrogen ion as carriers such as He or Ar.
Next step utilizes wafer transport handler 37 to shift out wafer 20 from process chamber 30, and it is delivered to the conveying room 34 with vacuum environment 36, shown in Fig. 3 b.Then wafer 20 is transplanted on process chamber 40, at the sputtering deposit that component exposure is not descended one deck conductor under the condition of oxidation environment, shown in Fig. 3 c with vacuum environment 42.In order to realize this transmission, at first process chamber 30 is bled, and be evacuated.Then wafer 20 is transplanted on conveying room 34, delivers to vacuum chamber 40 then, with depositing metal under the pressure of milli torr.The chamber 30 that is used for reduction step links to each other with the chamber 40 that is used for the metal depositing step, so that wafer 20 can be moved on to another chamber from a chamber, and it is not exposed to oxidation environment.Nature also can provide reducing environment, and in the same indoor metal deposit of carrying out, and in this chamber, carry out reduction step and depositing step.In chamber 40, the conductor 50 that deposit contacts with elemental copper surface 22 ' in the through hole 26 is shown in Fig. 2 d-2e.If conductor 50 is another copper wiring layer, then conductor 50 is made of thin lining 52 and copper 54 two parts at least.At first; deposit selects to be used to adhere to and prevent the thin lining 52 of copper diffusion; cover elemental copper surface 22 '; protective side wall does not contact copper 54; in the US patent 5676587 and 5695810 that transfers people such as Landers jointly, this is had more fully and describe; here it is for referencial use to introduce these documents, shown in Fig. 2 d.The thickness of thin lining 52 generally is no more than 1000 dusts, comprises the titanium and the titanium nitride membrane that are arranged alternately each other, constitutes Ti/TiN lamination or tantalum and tantalum nitride membrane, constitutes the Ta/TaN lamination, or Ta.This lining is to utilize the physical vapor deposition deposit be known as sputtering deposit, or available chemical vapor deposition method deposit, to form the coating of more conformal.Then, cement copper 54 on lining 52, with filling vias 26, shown in Fig. 2 e.
What the present invention was useful especially is, the composition utilization of copper layer is embedded into technology, conductor deposited 54, and to fill the groove in insulating barrier 24 and the lining 52, then, polished wafer 20 is to be planarized to conductor 54 and lining 52 on the surface 24 ' of insulating barrier 24.Utilize dual damascene technique composition copper as shown in Figure 4 to have same effect.Except that two embolisms 60, this technology is undertaken by the order of Fig. 2 a-2f, before the liner deposition step of the reduction step of Fig. 2 c and Fig. 2 d, shelters with corrosion step with two steps and to leave wire channels 62.
In addition, the present invention be advantageous in that to have sloped sidewall shown in Figure 5 26 " through hole 26.Because directly the corrosion meeting is removed lining 5,52 from the angled side walls surface, so cannot adopt the technology of No. 08858139 patent application in this case.By the present invention, do not need to carry out direct corrosion step, lining 52 continues on the level that remaines in, the vertical and surface that tilts.Deposit behind the copper 54, composition also corrodes it, provides by the through hole in the insulating barrier 24 26 " connect up 70 with wiring 22 copper that contacts.
Although specifically describe here and showed several embodiments of the present invention and changed shape, should be understood that also to exist do not break away from the scope of the invention various to change shape with accompanying drawing.Above specification is not to be intended to limit the scope of the present invention to be narrower than appended claims.Given example only is used for illustration, but not gets rid of.
Claims (28)
1. a processing has the method for the semiconductor wafer of copper metallization, may further comprise the steps:
A) provide and have the copper layer of composition and the wafer of the insulating barrier on the said copper layer;
B) in said insulating barrier, provide through hole, wherein may form cupric oxide on the copper in being exposed to said through hole;
C) said wafer is placed process chamber;
D) in said process chamber, provide reducing environment, being elemental copper with said copper oxide reduction; And
E) wafer be not exposed under the condition of oxidation environment conductor deposited in said through hole.
2. the method for claim 1 is characterized in that, the said conductor of said step (e) comprises thin lining, and said lining is used for copper diffusion barrier.
3. method as claimed in claim 2 is characterized in that, along the said thin lining of the sidewall deposit of said through hole.
4. method as claimed in claim 3 is characterized in that, said thin lining comprises a kind of in tantalum, tantalum nitride, titanium, titanium nitride, tantalum nitride silicon and the tungsten nitride.
5. method as claimed in claim 2 is characterized in that, said thin liner deposition is on said elemental copper.
6. method as claimed in claim 2 also is included on the said thin lining conductor deposited to fill the step of said through hole.
7. method as claimed in claim 6 also comprises the step of polishing said conductor and stopping at said insulating barrier.
8. method as claimed in claim 2 is characterized in that said conductor comprises copper.
9. the method for claim 1 is characterized in that, the said insulating barrier of said step (a) comprises silicon dioxide.
10. the method for claim 1 is characterized in that, the said insulating barrier of said step (a) comprises polymer.
11. method as claimed in claim 10 is characterized in that the said polymer comprises polyimides.
12. the method for claim 1 is characterized in that, the said reducing environment of said step (d) comprises hydrogen.
13. the method for claim 1 is characterized in that, the said reducing environment of said step (d) comprises hydrogen ion.
14. the method for claim 1 is characterized in that, the said reducing environment of said step (d) comprises carbon monoxide.
15. the method for claim 1 is characterized in that, the said reducing environment of said step (d) comprises NOx.
16. the method for claim 1 is characterized in that, said depositing step (e) carries out in the said chamber of said step (c).
17. the method for claim 1 is characterized in that, said depositing step (e) carries out in second process chamber.
18. the method for claim 1 is characterized in that, the said chamber from said step (c) moves on to said second Room with said wafer by transfer chamber after, carries out said depositing step (e).
19. a semiconductor structure comprises:
The copper layer of composition;
Insulating barrier on the said copper layer;
Lead to the through hole of said copper layer in the said insulating barrier, said through hole comprises the sidewall that is made of said insulating barrier;
Cover the conductive liner on the elemental copper surface of the said copper layer in the said through hole, said conductive liner also covers on the said sidewall, and wherein said lining provides and stopped do not have copper directly to contact with said sidewall to what copper spread.
20. structure as claimed in claim 19 is characterized in that, said thin lining comprises a kind of in tantalum, tantalum nitride, titanium, titanium nitride, tantalum nitride silicon and the tungsten nitride.
21. structure as claimed in claim 19 is characterized in that, also is included in the conductor that is used to fill said through hole on the said lining.
22. structure as claimed in claim 21 is characterized in that, said conductor and said insulating barrier are smooth.
23. structure as claimed in claim 19 is characterized in that, said insulating barrier comprises silicon dioxide.
24. structure as claimed in claim 19 is characterized in that, said insulating barrier comprises polymer.
25. structure as claimed in claim 24 is characterized in that the said polymer comprises polyimides.
26. structure as claimed in claim 19 is characterized in that, said through hole has angled side walls.
27. structure as claimed in claim 19 is characterized in that, said through hole has vertical sidewall.
28. structure as claimed in claim 27 is characterized in that, the sidewall that said through hole not only has vertical sidewall but also has level.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3163098A | 1998-02-27 | 1998-02-27 | |
| US09/031630 | 1998-02-27 | ||
| US09/031,630 | 1998-02-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1227409A true CN1227409A (en) | 1999-09-01 |
| CN1149654C CN1149654C (en) | 2004-05-12 |
Family
ID=21860551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991012887A Expired - Fee Related CN1149654C (en) | 1998-02-27 | 1999-01-26 | Method and structure for contact to copper metallization in insulating via on semiconductor |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH11312734A (en) |
| KR (1) | KR19990072296A (en) |
| CN (1) | CN1149654C (en) |
| SG (1) | SG73615A1 (en) |
| TW (1) | TW396429B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378953C (en) * | 2004-10-14 | 2008-04-02 | 国际商业机器公司 | Method of forming low resistance and reliable via in inter-level dielectric interconnect |
| CN101630656B (en) * | 2008-07-15 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Methods for forming contact hole and dual damascene structure |
| CN101771020B (en) * | 2009-01-05 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Through-silicon via with scalloped sidewalls |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223549A (en) | 1999-01-29 | 2000-08-11 | Canon Inc | Substrate carrier, substrate carrying method, hand mechanism for carrying substrate, ashing apparatus and ashing method |
| KR100445551B1 (en) * | 2001-12-21 | 2004-08-25 | 동부전자 주식회사 | Method of remove a residual metal-oxidation product of a semiconductor device fabrication process |
| JP3734447B2 (en) * | 2002-01-18 | 2006-01-11 | 富士通株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
| JP2004087807A (en) * | 2002-08-27 | 2004-03-18 | Fujitsu Ltd | Semiconductor device and method for manufacturing the same |
| JP2010153897A (en) * | 2010-02-22 | 2010-07-08 | Fujitsu Semiconductor Ltd | Method for producing semiconductor device |
| CN116034460A (en) * | 2020-08-27 | 2023-04-28 | 朗姆研究公司 | Material-reducing copper etching |
-
1999
- 1999-01-26 CN CNB991012887A patent/CN1149654C/en not_active Expired - Fee Related
- 1999-01-27 KR KR1019990002477A patent/KR19990072296A/en not_active Application Discontinuation
- 1999-02-01 TW TW88101497A patent/TW396429B/en not_active IP Right Cessation
- 1999-02-18 JP JP3969299A patent/JPH11312734A/en not_active Withdrawn
- 1999-02-23 SG SG1999001011A patent/SG73615A1/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378953C (en) * | 2004-10-14 | 2008-04-02 | 国际商业机器公司 | Method of forming low resistance and reliable via in inter-level dielectric interconnect |
| CN101630656B (en) * | 2008-07-15 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Methods for forming contact hole and dual damascene structure |
| CN101771020B (en) * | 2009-01-05 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Through-silicon via with scalloped sidewalls |
Also Published As
| Publication number | Publication date |
|---|---|
| TW396429B (en) | 2000-07-01 |
| SG73615A1 (en) | 2000-06-20 |
| JPH11312734A (en) | 1999-11-09 |
| CN1149654C (en) | 2004-05-12 |
| KR19990072296A (en) | 1999-09-27 |
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