CN101630656B - Methods for forming contact hole and dual damascene structure - Google Patents
Methods for forming contact hole and dual damascene structure Download PDFInfo
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- CN101630656B CN101630656B CN2008100405661A CN200810040566A CN101630656B CN 101630656 B CN101630656 B CN 101630656B CN 2008100405661 A CN2008100405661 A CN 2008100405661A CN 200810040566 A CN200810040566 A CN 200810040566A CN 101630656 B CN101630656 B CN 101630656B
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Abstract
A method for forming a contact hole comprises the following steps: providing a semiconductor substrate which is orderly provided with a metallic layer, an inter-layer insulating layer and a blocking layer; etching the blocking layer and the inter-layer insulating layer until the metallic layer is exposed to form the contact hole; introducing gas to reduce the oxidized surface of the exposed metallic layer. The invention also provides a method for forming a dual damascene structure. The method for forming the contact hole improves the effectiveness of contacting the metallic layer with following metallic substances, and further improves the electrical property of a semiconductor device.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, relate in particular to the method that forms contact hole and dual-damascene structure.
Background technology
In recent years, along with the development of semiconductor integrated circuit manufacturing technology, the quantity of contained device constantly increases in the integrated circuit, and size of devices is also constantly dwindled because of the lifting of integrated level, and is therefore also increasing for the demand of good circuit connection.And the quality that circuit connects is determined by a plurality of factors, and one of them is a whether defectiveness of formed metal level.Along with the develop rapidly of very lagre scale integrated circuit (VLSIC) ULSI (Ultra Large ScaleIntegration), integrated circuit fabrication process becomes and becomes increasingly complex with meticulous.In order to improve integrated level; Reduce manufacturing cost, the characteristic size of device (Critical Size) constantly diminishes, and the number of elements in the chip unit are constantly increases; Plane routing has been difficult to satisfy element high density distribution requirements; Can only adopt polylaminate wiring technique, utilize the vertical space of chip, further improve the integration density of device.
Have now in the process that forms metal interconnect structure referring to figs. 1 to Fig. 4.As shown in Figure 1, at first, on Semiconductor substrate 100, form metal level 102, the material of metal level 102 is copper or aluminium etc.; On metal level 102, form interlayer insulating film 104 with physical vapour deposition (PVD) or chemical vapour deposition technique, the material of said interlayer insulating film 104 is can be tetraethoxysilane (TEOS), silica or fluorine silex glass etc.; Then, on interlayer insulating film 104, form barrier layer 106 with physical vapour deposition (PVD) or chemical vapour deposition technique, the material on said barrier layer 106 is silicon nitride or silicon oxynitride etc.; On barrier layer 106, form photoresist layer 108 with spin-coating method; Through overexposure, developing process, on photoresist layer 108, form contact hole pattern 110.
As shown in Figure 2, photoresist layer 108 as mask, along contact hole pattern 110, to exposing metal level 102, is formed contact hole 112 with dry etching method etching barrier layer 106 and interlayer insulating film 104; Ashing method is removed photoresist layer 108.
As shown in Figure 3, then, in contact hole 112, fill full conductive materials, form conductive plunger 114; Then, continue on the barrier layer, to form metal wiring layer (figure does not show), be communicated with metal level 102, form metal interconnect structure through leading connector 114.
In Chinese patent 02106882.8, can also find much more more and the relevant information of above-mentioned formation metal interconnect structure technical scheme.
Have now after etching forms contact hole,, cause its surface oxidized, and then cause the electrical property of metal level to reduce because metal level is exposed to the open air.
Summary of the invention
The problem that the present invention solves provides a kind of method that forms contact hole and dual-damascene structure, prevents that the electrical property of metal level from reducing.
For addressing the above problem, the present invention provides a kind of method that forms contact hole, comprises the following steps: to provide the Semiconductor substrate that is formed with metal level, interlayer insulating film and barrier layer successively; Etching barrier layer and interlayer insulating film form contact hole to exposing metal level; Feed gas, will expose the oxidized layer on surface of metal in back to the open air and reduce.
Optional, the gas of said feeding is hydrogen.The flow of said hydrogen is 90sccm～150sccm.The required pressure of said feeding hydrogen is 80 millitorrs～150 millitorrs.The required power of said feeding hydrogen is 1200W～1800W.
The present invention also provides a kind of method that forms dual-damascene structure, comprises the following steps: to provide the Semiconductor substrate that is formed with metal level, cover layer, interlayer insulating film, barrier layer successively; Etching barrier layer, interlayer insulating film form contact hole to exposing cover layer; Form bottom anti-reflection layer in contact hole and on the barrier layer; The etching bottom anti-reflection layer, the bottom anti-reflection layer on the barrier layer is removed fully, and the thickness of the bottom anti-reflection layer in the contact hole can be protected metal level in the subsequent etching process; Etching barrier layer and interlayer insulating film form groove, and the connection corresponding with the position of contact hole of the position of said groove; After removing the bottom anti-reflection layer in the contact hole, the etching cover layer forms dual-damascene structure to exposing metal level; Feed gas, will expose the oxidized layer on surface of metal in back to the open air and reduce.
Optional, the gas of said feeding is hydrogen.The flow of said hydrogen is 90sccm～150sccm.The required pressure of said feeding hydrogen is 80 millitorrs～150 millitorrs.The required power of said feeding hydrogen is 1200W～1800W.
Compared with prior art; The present invention has the following advantages: after forming contact hole and dual-damascene structure, feed gas; To expose the oxidized layer on surface of metal in back to the open air reduces; Become metal again through reduction back metal oxide, improved the validity that metal level contacts with follow-up metallics, and then improved the electrical property of semiconductor device.
Description of drawings
Fig. 1 to Fig. 3 has the sketch map that in making the contact hole process, forms metal interconnect structure now;
Fig. 4 is the practical implementation process chart that the present invention removes the layer on surface of metal defective;
Fig. 5 is the practical implementation process chart that the present invention forms contact hole;
Fig. 6 to Fig. 8 is the embodiment sketch map that the present invention forms contact hole;
Fig. 9 is the practical implementation process chart that the present invention forms dual-damascene structure;
Figure 10 to Figure 14 is the embodiment sketch map that the present invention forms dual-damascene structure.
Embodiment
The present invention feeds gas after forming contact hole and dual-damascene structure; To expose the oxidized layer on surface of metal in back to the open air reduces; Become metal again through reduction back metal oxide, improved the validity that metal level contacts with follow-up metallics, and then improved the electrical property of semiconductor device.
Fig. 4 is the practical implementation process chart that the present invention removes the layer on surface of metal defective.As shown in Figure 4, execution in step S101 provides the Semiconductor substrate that is formed with metal level, and said layer on surface of metal is oxidized;
In this implementing process, said metal level so its surface is oxidized easily, generates the oxidized metal thing owing to expose to the open air in the air.
Execution in step S102 feeds gas, and the layer on surface of metal of oxidation is reduced.
In this implementing process, said gas specifically can be hydrogen, and the flow of said hydrogen is 90sccm (cubic centimetre/minute)～150sccm, specifically can be 90sccm, 100sccm, 110sccm, 120sccm, 130sccm, 140sccm or 150sccm etc.The required pressure of said feeding hydrogen is 80 millitorrs (1 holder=133.3 Pascals)～150 millitorrs, specifically can is 80 millitorrs, 90 millitorrs, 100 millitorrs, 110 millitorrs, 120 millitorrs, 130 millitorrs, 140 millitorrs or 150 millitorrs etc.; The required power of said feeding hydrogen is 1200W～1800W, specifically can be 1200W, 1300W, 1400W, 1500W, 1600W, 1700W or 1800W etc.
Fig. 5 is the practical implementation process chart that the present invention forms contact hole.As shown in Figure 5, execution in step S201 provides the Semiconductor substrate that is formed with metal level, interlayer insulating film and barrier layer successively; Execution in step S202, etching barrier layer and interlayer insulating film form contact hole to exposing metal level; Execution in step S203 feeds gas, will expose the oxidized layer on surface of metal in back to the open air and reduce.
Fig. 6 to Fig. 8 is the embodiment sketch map that the present invention forms contact hole.As shown in Figure 6, at first, Semiconductor substrate 200 is provided, said Semiconductor substrate 200 is silicon, silicon-on-insulator etc.; On Semiconductor substrate 200, form metal level 202, the material of metal level 202 is copper or aluminium etc., and the method for said formation metal level 202 can be chemical vapour deposition technique or vapour deposition method etc.; Use physical vaporous deposition or chemical vapour deposition technique on metal level 202, to form the interlayer insulating film 204 that thickness is 3000 dusts～5000 dusts, the material of said interlayer insulating film 204 is can be tetraethoxysilane (TEOS), silica or fluorine silex glass etc.; Then, use physical vaporous deposition or chemical vapour deposition technique on interlayer insulating film 204, to form the barrier layer 206 that thickness is 3000 dusts～4000 dusts, the material on said barrier layer 206 is silicon nitride or silicon oxynitride etc.; On barrier layer 206, form photoresist layer 208, the method that forms photoresist layer 208 is coated to photoresist on the barrier layer 206 for well known to a person skilled in the art technology, dries then, baking step; Through overexposure, developing process, on photoresist layer 208, form contact hole pattern 210.
In the present embodiment, the thickness of interlayer insulating film 204 specifically can be 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts or 5000 dusts etc., preferred 4000 dusts.
In the present embodiment, the thickness on barrier layer 206 specifically can be 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts or 5000 dusts etc., preferred 4000 dusts.
The thickness of photoresist layer 208 is 15000 dusts～20000 dusts, and concrete thickness is 15000 dusts, 16000 dusts, 17000 dusts, 18000 dusts, 19000 dusts or 20000 dusts etc. for example, preferred 18000 dusts.
As shown in Figure 7, photoresist layer 208 as mask, along contact hole pattern 210, to exposing metal level 202, is formed contact hole 212 with dry etching method etching barrier layer 206 and interlayer insulating film 204; Then, remove photoresist layer 208 with ashing method.
The temperature of ashing photoresist layer 208 is 200 ℃～300 ℃, and actual temp can be 200 ℃, 220 ℃, 240 ℃, 260 ℃, 280 ℃ or 300 ℃, preferred 250 ℃.
In the present embodiment, behind the formation contact hole 212, metal level 202 is exposed in the air, and is oxidized to metal oxide layer 211.
As shown in Figure 8, then, the Semiconductor substrate 200 that will have metal level 202, interlayer insulating film 204 and barrier layer 206 is put into reaction chamber, in reaction chamber, feeds gas 213, with metal oxide layer 211 reactions, makes it be reduced to metal.
In the present embodiment, said gas specifically can be hydrogen, and its flow is 90sccm～150sccm, specifically can be 90sccm, 100sccm, 110sccm, 120sccm, 130sccm, 140sccm or 150sccm etc.; The required pressure of said feeding hydrogen is 80 millitorrs (1 holder=133.3 Pascals)～150 millitorrs, specifically can is 80 millitorrs, 90 millitorrs, 100 millitorrs, 110 millitorrs, 120 millitorrs, 130 millitorrs, 140 millitorrs or 150 millitorrs etc.; The required power of said feeding hydrogen is 1200W～1800W, specifically can be 1200W, 1300W, 1400W, 1500W, 1600W, 1700W or 1800W etc.
In the present embodiment, the gas that feeding can be reduced the layer on surface of metal of oxidation has improved the validity that metal level contacts with follow-up metallics, and then has improved the electrical property of semiconductor device.
Afterwards, in contact hole 212, fill full conductive materials, form conductive plunger; Then, continue on the barrier layer, to form metal wiring layer, be communicated with metal level, form metal interconnect structure through leading connector.
Fig. 9 is the practical implementation process chart that the present invention forms dual-damascene structure.As shown in Figure 9, execution in step S301 provides the Semiconductor substrate that is formed with metal level, cover layer, interlayer insulating film, barrier layer successively; Execution in step S302, etching barrier layer, interlayer insulating film form contact hole to exposing cover layer; Execution in step S303 forms bottom anti-reflection layer in contact hole and on the barrier layer; Execution in step S304, the etching bottom anti-reflection layer, the bottom anti-reflection layer on the barrier layer is removed fully, and the thickness of the bottom anti-reflection layer in the contact hole can be protected metal level in the subsequent etching process; Execution in step S305, etching barrier layer and interlayer insulating film form groove, and the connection corresponding with the position of contact hole of the position of said groove; Execution in step S306, after the bottom anti-reflection layer in the removal contact hole, the etching cover layer forms dual-damascene structure to exposing metal level; Execution in step S307 feeds gas, will expose the oxidized layer on surface of metal in back to the open air and reduce.
Figure 10 to Figure 14 is the embodiment sketch map that the present invention forms dual-damascene structure.Shown in figure 10, Semiconductor substrate 300 is provided, said Semiconductor substrate contains semiconductor device; On Semiconductor substrate 300, form metal level 302, the material of said metal level 302 can be aluminium or copper; On metal level 302, form cover layer 304, the thickness of said cover layer 304 is 600 dusts～800 dusts, and concrete example is like 600 dusts, 650 dusts, 700 dusts, 750 dusts or 800 dusts etc., preferred 700 dusts; On cover layer 304, form interlayer insulating film 306 with chemical vapour deposition technique then, the thickness of interlayer insulating film 306 is 3000 dusts～4000 dusts, and concrete example is like 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts or 5000 dusts etc., preferred 4000 dusts.
The material of said cover layer 304 is silicon nitride (SiN) or silicon oxynitride (SiON) or nitrogen silicon oxide carbide (SiCNO) etc. for example; Can prevent that the metal level 302 on the Semiconductor substrate 300 is diffused in the interlayer insulating film 306; Also can be used as etching stop layer, prevent that the metal level on the Semiconductor substrate 300 302 is etched in the subsequent etching process.The material of said interlayer insulating film 306 can be tetraethoxysilane, silica or fluorine silex glass etc.
Afterwards, on interlayer insulating film 306, forming thickness is the barrier layer 308 of 3000 dusts～4000 dusts, and the material on said barrier layer 308 is silicon nitride, silicon oxynitride etc. for example; Subsequently, on barrier layer 308, form first photoresist layer 310, on first photoresist layer 310, form first opening, the corresponding follow-up position that needs to form contact hole in the dual-damascene structure of first aperture position through exposure imaging technology; With first photoresist layer 310 is mask, and edge first opening until exposing cover layer 304, forms contact hole 312 with dry etching method etching barrier layer 308, interlayer insulating film 306.
The concrete thickness on said barrier layer 308 is 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts or 5000 dusts etc. for example, preferred 4000 dusts.
The thickness of said first photoresist layer 310 is 15000 dusts～20000 dusts, and concrete thickness is 15000 dusts, 16000 dusts, 17000 dusts, 18000 dusts, 19000 dusts or 20000 dusts etc. for example, preferred 18000 dusts.
Shown in figure 11, on barrier layer 308, form bottom anti-reflection layer 314 with chemical vapour deposition technique or spin-coating method, and fill full contact hole 312.308 lip-deep thickness are 1000 dusts～8000 dusts to said bottom anti-reflection layer 314 on the barrier layer, and present embodiment is preferably 2000 dusts～5500 dusts.
Then; Bottom anti-reflection layer 314 on bottom anti-reflection layer 314 to the barrier layer 308 on the etching barrier layer 308 is removed fully; And keeping the part bottom anti-reflection layer 314 in the contact hole 312, the thickness of wherein staying the bottom anti-reflection layer 314 in the contact hole 312 should guarantee in the technical process of the dual-damascene structure of etching formation subsequently, to avoid metal level 302 to be etched.Described etching technics can be dry method or wet-etching technology.Wherein, existing etching technics can be through flow or the concentration of etching solution of control etching gas, and parameter such as etch period makes the thickness of the bottom anti-reflection layer 314 in the contact hole 312 reach technological requirement.
Shown in figure 12; On barrier layer 308 and bottom anti-reflection layer 314, form second photoresist layer 316 with spin-coating method; The thickness of said second photoresist layer 316 is 15000 dusts～20000 dusts; Concrete thickness is 15000 dusts, 16000 dusts, 17000 dusts, 18000 dusts, 19000 dusts or 20000 dusts etc. for example, preferred 18000 dusts.
Second photoresist layer 316 is carried out exposure imaging technology, form second opening, the corresponding follow-up position that needs to form groove in the dual-damascene structure of said second aperture position, the width of second opening is greater than the width of contact hole 312.
With second photoresist layer 316 is mask, with dry etching method etching barrier layer 308 and interlayer insulating film 306, forms groove 318 along second opening, and the connection corresponding with the position of contact hole 312 of the position of said groove 318.After etching forms groove 318, because the restriction of etching technics, also can residual fraction bottom anti-reflection layer 314 in the contact hole 312.
Shown in figure 13, remove second photoresist layer 316 and the bottom anti-reflection layer 314 that residues in the contact hole 312 with ashing method; Then, remove the second residual photoresist layer 316 with wet etching again; Then, with the dry etching method along contact hole 312 etching cover layers 304 to exposing metal level 302, form the dual-damascene structure 320 that constitutes by contact hole 312 and groove 318.
In the present embodiment, behind the formation dual-damascene structure 320, metal level 302 is exposed in the air, and is oxidized to metal oxide layer 319.
Shown in figure 14, then, the Semiconductor substrate 300 that will have each rete is put into reaction chamber, in reaction chamber, feeds gas 313, with metal oxide layer 319 reactions, makes it be reduced to metal.
In the present embodiment, said gas specifically can be hydrogen, and its flow is 90sccm～150sccm, specifically can be 90sccm, 100sccm, 110sccm, 120sccm, 130sccm, 140sccm or 150sccm etc.; The required pressure of said feeding hydrogen is 80 millitorrs (1 holder=133.3 Pascals)～150 millitorrs, specifically can is 80 millitorrs, 90 millitorrs, 100 millitorrs, 110 millitorrs, 120 millitorrs, 130 millitorrs, 140 millitorrs or 150 millitorrs etc.; The required power of said feeding hydrogen is 1200W～1800W, specifically can be 1200W, 1300W, 1400W, 1500W, 1600W, 1700W or 1800W etc.
In the present embodiment, the gas that feeding can be reduced the layer on surface of metal of oxidation has improved the validity that metal level contacts with follow-up metallics, and then has improved the electrical property of semiconductor device.
Afterwards, deposit metallic material in forming dual-damascene structure 320 forms metal connecting line.Described metal material is copper, aluminium etc. for example.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and revise, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. a method that forms contact hole is characterized in that, comprises the following steps:
The Semiconductor substrate that is formed with metal level, interlayer insulating film and barrier layer successively is provided;
Etching barrier layer and interlayer insulating film form contact hole to exposing metal level;
Feeding flow is 90sccm～150sccm hydrogen, will expose the oxidized layer on surface of metal in back to the open air and reduce.
2. according to the method for the said formation contact hole of claim 1, it is characterized in that the required pressure of said feeding hydrogen is 80 millitorrs～150 millitorrs.
3. according to the method for the said formation contact hole of claim 2, it is characterized in that the required power of said feeding hydrogen is 1200W～1800W.
4. a method that forms dual-damascene structure is characterized in that, comprises the following steps:
The Semiconductor substrate that is formed with metal level, cover layer, interlayer insulating film, barrier layer successively is provided;
Etching barrier layer, interlayer insulating film form contact hole to exposing cover layer;
Form bottom anti-reflection layer in contact hole and on the barrier layer;
The etching bottom anti-reflection layer, the bottom anti-reflection layer on the barrier layer is removed fully, and the thickness of the bottom anti-reflection layer in the contact hole can be protected metal level in the subsequent etching process;
Etching barrier layer and interlayer insulating film form groove, and the connection corresponding with the position of contact hole of the position of said groove;
After removing the bottom anti-reflection layer in the contact hole, the etching cover layer forms dual-damascene structure to exposing metal level;
Feed gas, will expose the oxidized layer on surface of metal in back to the open air and reduce.
5. according to the method for the said formation dual-damascene structure of claim 4, it is characterized in that the gas of said feeding is hydrogen.
6. according to the method for the said formation dual-damascene structure of claim 5, it is characterized in that the flow of said hydrogen is 90sccm～150sccm.
7. according to the method for the said formation dual-damascene structure of claim 6, it is characterized in that the required pressure of said feeding hydrogen is 80 millitorrs～150 millitorrs.
8. according to the method for the said formation dual-damascene structure of claim 7, it is characterized in that the required power of said feeding hydrogen is 1200W～1800W.
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| US10734968B2 (en) * | 2016-08-26 | 2020-08-04 | Samsung Electro-Mechanics Co., Ltd. | Bulk acoustic resonator and filter including the same |
| CN107731745B (en) * | 2017-10-18 | 2020-03-10 | 武汉新芯集成电路制造有限公司 | Preparation method of vase-shaped contact hole |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1227409A (en) * | 1998-02-27 | 1999-09-01 | 国际商业机器公司 | Method and structure for contact to copper metallization in insulating via on semiconductor |
| KR20020013013A (en) * | 2000-08-10 | 2002-02-20 | 박종섭 | Method for forming contact plug of semiconductor device |
| CN1383192A (en) * | 2001-04-23 | 2002-12-04 | 日本电气株式会社 | Semiconductor device and its preparing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1227409A (en) * | 1998-02-27 | 1999-09-01 | 国际商业机器公司 | Method and structure for contact to copper metallization in insulating via on semiconductor |
| KR20020013013A (en) * | 2000-08-10 | 2002-02-20 | 박종섭 | Method for forming contact plug of semiconductor device |
| CN1383192A (en) * | 2001-04-23 | 2002-12-04 | 日本电气株式会社 | Semiconductor device and its preparing method |
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