SG73615A1 - Method and structure for contact to copper metallization in an insulating via on a semiconductor - Google Patents
Method and structure for contact to copper metallization in an insulating via on a semiconductorInfo
- Publication number
- SG73615A1 SG73615A1 SG1999001011A SG1999001011A SG73615A1 SG 73615 A1 SG73615 A1 SG 73615A1 SG 1999001011 A SG1999001011 A SG 1999001011A SG 1999001011 A SG1999001011 A SG 1999001011A SG 73615 A1 SG73615 A1 SG 73615A1
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor
- contact
- copper metallization
- insulating via
- insulating
- Prior art date
Links
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3163098A | 1998-02-27 | 1998-02-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG73615A1 true SG73615A1 (en) | 2000-06-20 |
Family
ID=21860551
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1999001011A SG73615A1 (en) | 1998-02-27 | 1999-02-23 | Method and structure for contact to copper metallization in an insulating via on a semiconductor |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPH11312734A (en) |
KR (1) | KR19990072296A (en) |
CN (1) | CN1149654C (en) |
SG (1) | SG73615A1 (en) |
TW (1) | TW396429B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000223549A (en) | 1999-01-29 | 2000-08-11 | Canon Inc | Substrate carrier, substrate carrying method, hand mechanism for carrying substrate, ashing apparatus and ashing method |
KR100445551B1 (en) * | 2001-12-21 | 2004-08-25 | 동부전자 주식회사 | Method of remove a residual metal-oxidation product of a semiconductor device fabrication process |
JP3734447B2 (en) * | 2002-01-18 | 2006-01-11 | 富士通株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
JP2004087807A (en) * | 2002-08-27 | 2004-03-18 | Fujitsu Ltd | Semiconductor device and method for manufacturing the same |
US7223691B2 (en) * | 2004-10-14 | 2007-05-29 | International Business Machines Corporation | Method of forming low resistance and reliable via in inter-level dielectric interconnect |
CN101630656B (en) * | 2008-07-15 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Methods for forming contact hole and dual damascene structure |
US8049327B2 (en) * | 2009-01-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with scalloped sidewalls |
JP2010153897A (en) * | 2010-02-22 | 2010-07-08 | Fujitsu Semiconductor Ltd | Method for producing semiconductor device |
US20230298869A1 (en) * | 2020-08-27 | 2023-09-21 | Lam Research Corporation | Subtractive copper etch |
-
1999
- 1999-01-26 CN CNB991012887A patent/CN1149654C/en not_active Expired - Fee Related
- 1999-01-27 KR KR1019990002477A patent/KR19990072296A/en not_active Application Discontinuation
- 1999-02-01 TW TW88101497A patent/TW396429B/en not_active IP Right Cessation
- 1999-02-18 JP JP3969299A patent/JPH11312734A/en not_active Withdrawn
- 1999-02-23 SG SG1999001011A patent/SG73615A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN1149654C (en) | 2004-05-12 |
KR19990072296A (en) | 1999-09-27 |
JPH11312734A (en) | 1999-11-09 |
TW396429B (en) | 2000-07-01 |
CN1227409A (en) | 1999-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0700080A3 (en) | Method of producing self-aligned contacts on semiconductor devices and self-aligned contact structure | |
GB2333179B (en) | A method for forming a self aligned contact in a semiconductor device | |
SG79292A1 (en) | Semiconductor integrated circuit and its manufacturing method | |
SG84606A1 (en) | A method to avoid copper contamination during copper etching and cmp | |
IL112294A0 (en) | A method for forming solid conductive vias in substrates | |
HK1015897A1 (en) | Power-generation detection circuit, semiconductor device, electronic device, timepiece, power-generation detection method, and power consumption control method | |
SG70606A1 (en) | System and method for reducing power consumption in an electronic circuit | |
EP0973191A4 (en) | Method for manufacturing semiconductor integrated circuit device | |
EP0983612A4 (en) | A thermal conducting trench in a semiconductor structure and method for forming the same | |
SG99903A1 (en) | Method of making metallization and contact structures in an integrated circuit | |
GB0029288D0 (en) | Method of forming a copper wiring in a semiconductor device | |
GB2326281B (en) | A method for forming contact plugs in a semiconductor device | |
GB9716265D0 (en) | System and method for reducing power consumption in an electronic circuit | |
SG89366A1 (en) | Process for forming a semiconductor device and a conductive structure | |
GB9909492D0 (en) | Method for forming a self aligned contact in a semiconductor device | |
SG73615A1 (en) | Method and structure for contact to copper metallization in an insulating via on a semiconductor | |
GB2294587B (en) | Method for forming contacts in a semiconductor device | |
GB2348888B (en) | Method of forming a copper wiring in a semiconductor device | |
GB9930222D0 (en) | Barrier for copper metallization | |
GB2363678B (en) | Method of forming a copper wiring in a semiconductor device | |
GB9912175D0 (en) | Patterning method in semiconductor device fabricating process | |
EP1049175A4 (en) | Reverse conducting thyristor, mechanical contact semiconductor device, and semiconductor substrate | |
GB2298738B (en) | Method for forming metal contacts in semiconductor devices | |
GB2331872A9 (en) | Insulated electrical conductor and contacting method | |
GB2337161B (en) | Method for forming a contact plug and simultaneously planarizing a substrate surface in an intergrated circuit |