CN1207670C - 具有重叠读写操作和可伸缩地址流水线化的数据传送系统 - Google Patents
具有重叠读写操作和可伸缩地址流水线化的数据传送系统 Download PDFInfo
- Publication number
- CN1207670C CN1207670C CN01121951.3A CN01121951A CN1207670C CN 1207670 C CN1207670 C CN 1207670C CN 01121951 A CN01121951 A CN 01121951A CN 1207670 C CN1207670 C CN 1207670C
- Authority
- CN
- China
- Prior art keywords
- machine
- signal
- request
- bus
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Abstract
Description
Claims (24)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21304000P | 2000-06-21 | 2000-06-21 | |
US60/213,040 | 2000-06-21 | ||
US09/855,831 US6772254B2 (en) | 2000-06-21 | 2001-05-15 | Multi-master computer system with overlapped read and write operations and scalable address pipelining |
US09/855,831 | 2001-05-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1337630A CN1337630A (zh) | 2002-02-27 |
CN1207670C true CN1207670C (zh) | 2005-06-22 |
Family
ID=26907716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN01121951.3A Expired - Fee Related CN1207670C (zh) | 2000-06-21 | 2001-06-21 | 具有重叠读写操作和可伸缩地址流水线化的数据传送系统 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6772254B2 (zh) |
CN (1) | CN1207670C (zh) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605679B1 (en) * | 1997-07-23 | 2003-08-12 | E. I. Du Pont De Nemours And Company | Polymerization of olefins |
KR100644597B1 (ko) * | 2000-08-05 | 2006-11-10 | 삼성전자주식회사 | 버스 시스템 및 그 커맨드 전달방법 |
US6775727B2 (en) * | 2001-06-23 | 2004-08-10 | Freescale Semiconductor, Inc. | System and method for controlling bus arbitration during cache memory burst cycles |
US6857035B1 (en) | 2001-09-13 | 2005-02-15 | Altera Corporation | Methods and apparatus for bus mastering and arbitration |
JP2003186824A (ja) * | 2001-12-18 | 2003-07-04 | Canon Inc | バス使用権優先度調整装置およびシステム |
US7281140B2 (en) * | 2001-12-28 | 2007-10-09 | Intel Corporation | Digital throttle for multiple operating points |
US7174401B2 (en) * | 2002-02-28 | 2007-02-06 | Lsi Logic Corporation | Look ahead split release for a data bus |
US7246184B2 (en) * | 2002-04-12 | 2007-07-17 | Siemens Aktiengesellschaft | Method for configuring and/or operating an automation device |
US6948019B2 (en) * | 2002-04-30 | 2005-09-20 | Lsi Logic Corporation | Apparatus for arbitrating non-queued split master devices on a data bus |
US7107365B1 (en) * | 2002-06-25 | 2006-09-12 | Cypress Semiconductor Corp. | Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus |
US7054971B2 (en) * | 2002-08-29 | 2006-05-30 | Seiko Epson Corporation | Interface between a host and a slave device having a latency greater than the latency of the host |
US20040123054A1 (en) * | 2002-12-20 | 2004-06-24 | Gould Geoffrey A. | Portable computing device having a non-volatile memory device adapted to detect when a current memory operation is to be suspended and method therefor |
JP2004334410A (ja) * | 2003-05-06 | 2004-11-25 | Hitachi Ltd | 情報処理装置及びプロセッサ |
WO2004099995A2 (en) * | 2003-05-09 | 2004-11-18 | Koninklijke Philips Electronics N.V. | Hierarchical memory access via pipelining |
US7079147B2 (en) | 2003-05-14 | 2006-07-18 | Lsi Logic Corporation | System and method for cooperative operation of a processor and coprocessor |
US6970962B2 (en) * | 2003-05-19 | 2005-11-29 | International Business Machines Corporation | Transfer request pipeline throttling |
US7051146B2 (en) * | 2003-06-25 | 2006-05-23 | Lsi Logic Corporation | Data processing systems including high performance buses and interfaces, and associated communication methods |
US7013357B2 (en) * | 2003-09-12 | 2006-03-14 | Freescale Semiconductor, Inc. | Arbiter having programmable arbitration points for undefined length burst accesses and method |
US7181556B2 (en) * | 2003-12-23 | 2007-02-20 | Arm Limited | Transaction request servicing mechanism |
US7209998B2 (en) * | 2004-02-04 | 2007-04-24 | Qualcomm Incorporated | Scalable bus structure |
US7143220B2 (en) * | 2004-03-10 | 2006-11-28 | Intel Corporation | Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies |
US7353297B2 (en) * | 2004-06-08 | 2008-04-01 | Arm Limited | Handling of write transactions in a data processing apparatus |
US7213092B2 (en) * | 2004-06-08 | 2007-05-01 | Arm Limited | Write response signalling within a communication bus |
US7305510B2 (en) * | 2004-06-25 | 2007-12-04 | Via Technologies, Inc. | Multiple master buses and slave buses transmitting simultaneously |
US20060176890A1 (en) * | 2005-02-10 | 2006-08-10 | International Business Machines Corporation | Data processing system, method and interconnect fabric for improved communication in a data processing system |
US7451231B2 (en) * | 2005-02-10 | 2008-11-11 | International Business Machines Corporation | Data processing system, method and interconnect fabric for synchronized communication in a data processing system |
JP4668645B2 (ja) * | 2005-02-24 | 2011-04-13 | パナソニック株式会社 | Dmaコントローラ及びデータ転送制御方法 |
US7617343B2 (en) * | 2005-03-02 | 2009-11-10 | Qualcomm Incorporated | Scalable bus structure |
CN100435123C (zh) * | 2005-07-19 | 2008-11-19 | 威盛电子股份有限公司 | 用于稀疏线写操作的装置和方法 |
US7283418B2 (en) * | 2005-07-26 | 2007-10-16 | Micron Technology, Inc. | Memory device and method having multiple address, data and command buses |
US7836809B2 (en) * | 2005-09-23 | 2010-11-23 | John Noveske | Flash suppression system |
JP2007122410A (ja) * | 2005-10-28 | 2007-05-17 | Nec Electronics Corp | バス調停回路及びバス調停方法 |
FR2894696A1 (fr) * | 2005-12-14 | 2007-06-15 | Thomson Licensing Sas | Procede d'acces a un bus de transmission de donnees, dispositif et systeme correspondant |
US7412669B1 (en) * | 2006-07-06 | 2008-08-12 | Xilinx, Inc. | Generation of graphical design representation from a design specification data file |
EP2080300B1 (en) * | 2006-10-31 | 2018-09-19 | NXP USA, Inc. | Network and method for setting a time-base of a node in the network |
JP2009116702A (ja) * | 2007-11-07 | 2009-05-28 | Toshiba Corp | 半導体集積回路 |
US7787310B2 (en) * | 2008-02-21 | 2010-08-31 | Micron Technology, Inc. | Circuits, devices, systems, and methods of operation for capturing data signals |
US8583845B2 (en) * | 2008-08-07 | 2013-11-12 | Nec Corporation | Multi-processor system and controlling method thereof |
US8122159B2 (en) | 2009-01-16 | 2012-02-21 | Allegro Microsystems, Inc. | Determining addresses of electrical components arranged in a daisy chain |
DE112010003368T5 (de) * | 2010-02-26 | 2012-06-14 | Hewlett-Packard Development Company, L.P. | Wiederherstellung der Stabilität eines instabilen Busses |
GB2478795B (en) * | 2010-03-19 | 2013-03-13 | Imagination Tech Ltd | Requests and data handling in a bus architecture |
JP5528939B2 (ja) * | 2010-07-29 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | マイクロコンピュータ |
US8825933B2 (en) * | 2011-11-30 | 2014-09-02 | Andes Technology Corporation | Bus apparatus with default speculative transactions and non-speculative extension |
US20130339638A1 (en) * | 2012-06-19 | 2013-12-19 | Tal Lazmi | Status polling of memory devices using an independent status bus |
US9634715B2 (en) * | 2014-02-18 | 2017-04-25 | Allegro Microsystems, Llc | Signaling between master and slave components using a shared communication node of the master component |
US9787495B2 (en) | 2014-02-18 | 2017-10-10 | Allegro Microsystems, Llc | Signaling between master and slave components using a shared communication node of the master component |
US9785605B2 (en) * | 2014-11-05 | 2017-10-10 | Qualcomm Incorporated | Predefined static enumeration for dynamic enumeration buses |
US9892067B2 (en) | 2015-01-29 | 2018-02-13 | International Business Machines Corporation | Multiprocessor cache buffer management |
US10642500B2 (en) | 2015-09-28 | 2020-05-05 | Sandisk Technologies Llc | Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues |
US9927983B2 (en) * | 2015-09-28 | 2018-03-27 | Sandisk Technologies Llc | Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues |
US10866910B2 (en) | 2015-09-28 | 2020-12-15 | Sandisk Technologies Llc | Systems, methods, and computer-readable media for managing instruction fetch in virtual computing environments |
US11467769B2 (en) | 2015-09-28 | 2022-10-11 | Sandisk Technologies Llc | Managed fetching and execution of commands from submission queues |
US10747708B2 (en) | 2018-03-08 | 2020-08-18 | Allegro Microsystems, Llc | Communication system between electronic devices |
US10891071B2 (en) | 2018-05-15 | 2021-01-12 | Nxp Usa, Inc. | Hardware, software and algorithm to precisely predict performance of SoC when a processor and other masters access single-port memory simultaneously |
CN113556294A (zh) * | 2021-06-01 | 2021-10-26 | 水发兴业能源(珠海)有限公司 | 数据收发方法、数据收发装置、服务器及存储介质 |
CN113886305B (zh) * | 2021-09-30 | 2023-11-03 | 山东云海国创云计算装备产业创新中心有限公司 | 一种基于总线的仲裁方法、系统、存储介质及设备 |
CN113900864B (zh) * | 2021-11-18 | 2023-11-21 | 南昌华勤电子科技有限公司 | 一种数据读写装置及方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626843A (en) | 1983-09-27 | 1986-12-02 | Trw Inc. | Multi-master communication bus system with parallel bus request arbitration |
US5555425A (en) | 1990-03-07 | 1996-09-10 | Dell Usa, L.P. | Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters |
JP2625277B2 (ja) * | 1991-05-20 | 1997-07-02 | 富士通株式会社 | メモリアクセス装置 |
US5440751A (en) | 1991-06-21 | 1995-08-08 | Compaq Computer Corp. | Burst data transfer to single cycle data transfer conversion and strobe signal conversion |
US5809552A (en) * | 1992-01-29 | 1998-09-15 | Fujitsu Limited | Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions |
US5553248A (en) | 1992-10-02 | 1996-09-03 | Compaq Computer Corporation | System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal |
US5469544A (en) | 1992-11-09 | 1995-11-21 | Intel Corporation | Central processing unit address pipelining |
US5640527A (en) | 1993-07-14 | 1997-06-17 | Dell Usa, L.P. | Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states |
US5699516A (en) | 1994-12-22 | 1997-12-16 | Motorola, Inc. | Method and apparatus for implementing a in-order termination bus protocol within a data processing system |
US5784636A (en) * | 1996-05-28 | 1998-07-21 | National Semiconductor Corporation | Reconfigurable computer architecture for use in signal processing applications |
US6081860A (en) | 1997-11-20 | 2000-06-27 | International Business Machines Corporation | Address pipelining for data transfers |
-
2001
- 2001-05-15 US US09/855,831 patent/US6772254B2/en not_active Expired - Fee Related
- 2001-06-21 CN CN01121951.3A patent/CN1207670C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1337630A (zh) | 2002-02-27 |
US20020062414A1 (en) | 2002-05-23 |
US6772254B2 (en) | 2004-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1207670C (zh) | 具有重叠读写操作和可伸缩地址流水线化的数据传送系统 | |
CN1102265C (zh) | 用于在多条总线之间传送信息的系统和方法 | |
CN1082210C (zh) | 存储器直接存取控制设备 | |
US5850530A (en) | Method and apparatus for improving bus efficiency by enabling arbitration based upon availability of completion data | |
CN1069426C (zh) | 信息处理系统 | |
CN1111799C (zh) | 用于多处理器系统的改进的信号发送协议方法和信号发送协议电路 | |
EP0870239B1 (en) | Burst-broadcasting on a peripheral component interconnect bus | |
CN1037982A (zh) | 在有仲裁的80386/82385微机系统运行中80386对系统总线的抢用 | |
CN1694085A (zh) | 内部总线系统 | |
JPH0642236B2 (ja) | コマンダノードからのインターロック読み取りコマンドメッセージをレスポンダノードで実行する装置 | |
CN1760847A (zh) | 总线桥和数据传输方法 | |
JP3641003B2 (ja) | 調停機構付きバス・システム | |
EP2423824A1 (en) | Data transfer device, method of transferring data, and image forming apparatus | |
CN1892632A (zh) | 总线系统和仲裁其的方法 | |
KR20020009823A (ko) | 버스 시스템 및 그 버스 중재방법 | |
EP1811393A1 (en) | Method and system for data transfer | |
CN1224918C (zh) | 总线、属于此总线的冗余总线系统和其内传输信息的方法 | |
JP4583590B2 (ja) | バストランザクションにおける制御チップセットのアービトレーション | |
EP1187029B1 (en) | Peripheral component interconnect arbiter implementation with dynamic priority scheme | |
CN1161696C (zh) | 在一条共用线上传输信号的方法与装置 | |
CN1355635A (zh) | 使用总线的预仲裁装置及其方法 | |
CN1581125A (zh) | 仲裁器和仲裁方法 | |
CN1296844C (zh) | 数据传送方法和数据传送系统 | |
CN1165004C (zh) | 温备用双工设备及其操作方法 | |
CN101075221A (zh) | 管理分离总线上总线代理之间的数据流的方法和系统 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: INTEL CORP . Free format text: FORMER OWNER: INTERNATIONAL BUSINESS MACHINES CORPORATION Effective date: 20130913 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130913 Address after: American California Patentee after: Intel Corporation Address before: American New York Patentee before: International Business Machines Corp. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050622 Termination date: 20150621 |
|
EXPY | Termination of patent right or utility model |