CN1206467A - Integrated circuit device tester - Google Patents
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- CN1206467A CN1206467A CN 97191480 CN97191480A CN1206467A CN 1206467 A CN1206467 A CN 1206467A CN 97191480 CN97191480 CN 97191480 CN 97191480 A CN97191480 A CN 97191480A CN 1206467 A CN1206467 A CN 1206467A
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Abstract
In an IC device tester for testing IC devices held in contact with a test head, optical signals are employed for all signal exchanges between a tester mainframe and the test head and signal transmission lines therebetween are all formed by optical fibers, whereby the cable group interconnecting the tester mainframe and the test head can be made small in diameter and can be extended as required.
Description
Background of the present invention
The present invention relates to be used for the integrated circuit device tester of measuring semiconductor integrated device electronics (IC) or large scale integrated circuit equipment (LSI).
Fig. 1 shows the basic structure of the integrated circuit device tester that is widely used with the square form.Label 100 is represented measuring head, and 200 represent tester main system (main frame).Capability test board 101 and switching electronic circuit (pin electronics) 102 are housed on the measuring head 100.Have the socket (not drawing) of laying equipment under test (being referred to as DUT later on) on the capability test board 101, it has set up the electric connecting relation between equipment under test and the tester.
Switching electronic circuit 102 has driver bank 103, analog comparator group 104 and junction matrix translation circuit 105, wherein, driver bank 103 is used to drive DUT, analog comparator group 104 is used to check replying output signal and whether having the normal voltage value so that determine their H and L logic of DUT, and junction matrix translation circuit 105 is used for the equipment group on each terminal that is connected to DUT is switched.
The comparative result of pattern comparator group 104 is sent back in the tester main system 200 by answer signal transmission line 302, and compare on the logic comparator in main system 200 203 with from the desired pattern of mode generator 201, thereby measure inoperative component so that measure not matching between them.Label 204 is represented dead-file, and whenever logic comparator 203 detects when not matching, H that representative was lost efficacy or L logic just are written in the address that takes place of losing efficacy.
Usually, the reference clock CLK of A shown in capable carries out obtaining determining behind the frequency division full sized pules (rate pulse) RAT (B among Fig. 2 is capable) of test interval or period T among 204 couples of Fig. 2 of timing generator; In addition, timing generator 204 also makes full sized pules RAT postpone arbitrary time span, thereby produce various timing signals, as rising timing signal and decline timing signal, the gating timing signal of analog comparator group 104 and the compare operation timing signal of logic comparator 203 etc. of test mode signal waveform.
Therefore, timing generator 202 has many delay circuits, and these delay circuits can or be no more than in the scope that is no more than test period T and make full sized pules time-delay arbitrary time span in several times of scopes; These delay circuits are used for producing the various timing signals of the timing signal T1 of the capable and D of the C that resembles Fig. 2 shown in capable and T2 and so on, and these timing signals are than the reference timing signal arbitrary time span that lags behind.
These delay circuits in the timing generator 205 are made up of thick delay circuit DY1 group and accurate delay circuit bank DY2, and wherein, each thick delay circuit is counted and produced with clock clk cycle τ time clock CLK
1Be the delay time of unit, each accurate delay circuit is to clock clk cycle τ
1Thereby the interval segment and determine delay time; For example, these delay circuits can make the rising timing of test mode signal and the resolution of decline timing reach picosecond.
Tester main system 200 also comprises DC test component 206, load testing parts 207, first reference voltage source 208, second reference voltage source 209 and power supply unit 211, wherein, first reference voltage source 208 is used to be provided with the H of mode signal and the magnitude of voltage VIH and the VIL of L logic, second reference voltage source is used to provide the comparative voltage VOH and the VOL of analog comparator group 104, and power supply unit 211 is used for providing operating voltage to DUT.The setting of DC test component 206, load testing parts 207, first reference voltage source 208, second reference voltage source 209, power supply unit 211, mode generator 201, formatter 202, dead-file 204 and timing generator 205 and operation are controlled by control bus 11 by processor controls 10 fully.
Fig. 3 shows the annexation between measuring head 100 and the tester main system 200.Tester main system 200 is connected with each other by cable group 300 with measuring head 100.Because tester main system 200 is to couple together by the various signal wires that the front is mentioned in Fig. 1 with measuring head 100, so the cable count that cable group 300 is comprised is a lot.
The number of IC terminal increases along with the increase of the integrated level of IC.The increase of IC operating rate also can make the cable count of the cable group 300 that connects tester main system 200 and measuring head 100 increase.For example, in the tester that has corresponding to the test capacity of 1000 IC terminals, the number of signals of exchange reaches several ten thousand between tester main system 200 and the measuring head 100; In addition, owing to will use twisted-pair feeder, concentric cable, many sealing lines and similar special cable in occasions such as relating to high speed, high precision and noise resistance, therefore the actual quantity of lead is than big several times of the quantity of processed signal, so cable group 300 has formed a bale, thereby very difficult mobile test 100 (for example, be installed on the processor or remove) from processor.
Another shortcoming of prior art is: even the length of cable group 300 increases the phase mutual interference that a bit can cause between the cable a little, thereby reduce measuring accuracy.In addition, transmit so a large amount of signals and can consume a large amount of electric energy, this means has increased the heat that produces thereby has caused cooling difficulty, has also increased the quantity of terminating resistance simultaneously.These factors have hindered the miniaturization of system.
General introduction of the present invention
Therefore, the purpose of this invention is to provide a kind of integrated circuit device tester that can suppress the phase mutual interference between the signal, the test main system of this tester is convenient to operation with very little its measuring head that makes of cable group that is connected between the measuring head.
According to the present invention, a kind of IC device tester is provided, it is under the control of processor controls, produce mode data and expected data by mode generator, by formatter mode data is formatted into the preassigned pattern waveform, by driver mode waveform is applied on the tested IC equipment with the reference voltage form, by analog comparator will from the answer signal of tested IC equipment with compare with reference to logic level after make logic determines, logical and after will being judged by logic comparator compares the back from the expected data of mode generator and judges that tested IC equipment is substandard products or certified products, and fail data is written in the dead-file.This IC device tester comprises:
Tester main system with processor controls;
Be contained in the first serial data transceiver devices that is used to export serial data in the tester main system, the reference logic level that it is used to that the reference voltage of driver is set and analog comparator is set;
Be contained in the electric to optic converter device in the tester main system, it is used for converting serial data to lightwave signal;
Measuring head with driver and analog comparator, wherein, driver is used for test pattern is applied to tested IC equipment, and analog comparator is used to judge the logic of replying of IC equipment;
Be contained in the light/electrical converter device in the measuring head, it is used for converting lightwave signal to the electric signal serial data;
Be contained in the second serial data transceiver devices in the measuring head, it is used for converting serial data to parallel reference voltage data and parallel with reference to the logic level data;
The D/A converter device, it is used for parallel reference voltage data and walks abreast converting analog reference voltage respectively to and also above-mentioned transformation result being set to analog comparator and logic comparator respectively with reference to logic level with reference to the logic level data; With
Fiber device, it is used for electric to optic converter device and light/electrical switching device are coupled together.
According to the present invention, can adopt such structure: the mode with the light serial signal is transmitted as each IC terminal data designated or various timing signal from the tester main system to measuring head, serial data transceiver devices in the measuring head receives above-mentioned data or timing signal and converts them to confession the parallel signal that register setting stores is set, and in the lightwave signal mode data of measuring or the result who measures is sent back in the tester main system then.
According to the present invention, also be provided with mode memory and formatter in the measuring head, the digital test mode data that mode generator produces are sent to the form of light serial signal and deposit mode memory in the measuring head in.When beginning to test, from mode memory, read the wherein test pattern data of storage, then the test pattern data (digital signal) that is read out is become the simulation model signal by the formatter form, this mode signal is applied on the tested IC equipment by driver again.
Concerning structure of the present invention, even adopt plastic optical fiber, the diameter of optical transmission line is also only had an appointment 200 to 500 millimicrons, and different with the situation of transmission of electric signals, the unnecessary bidirectional conductor of using of each passage; Therefore can reduce the diameter and the weight of signal transmssion line.Adopt to transmit and receive the structure of light serial signal, can make used optical fiber especially less and the diameter of cable group and weight are further reduced.In addition, because therefore the phase mutual interference can not take place only along its core transmission light in optical fiber.So, can do cable group longer.
Brief description of drawings
Fig. 1 is the block scheme that is used to illustrate prior art;
Fig. 2 is the oscillogram that is used to illustrate the work of prior art;
Fig. 3 is the skeleton view that is used to illustrate prior art;
Fig. 4 is the block scheme of the embodiment of the invention;
Fig. 5 is the block scheme of switching part structure among Fig. 4;
Fig. 6 is the skeleton view of the framework of used in the embodiment shown in fig. 5 switching part;
Fig. 7 is the skeleton view of example that is used to install the framework of switching part shown in Figure 6;
Fig. 8 is the cut-open view of the example of photoelectricity compoboard shown in Figure 7;
Fig. 9 is the block scheme of another embodiment of the present invention;
Figure 10 is the block scheme of the switching part structure in embodiment illustrated in fig. 9;
Figure 11 is the block scheme of another embodiment of the present invention; With
Figure 12 is the block scheme of the switching part structure in embodiment illustrated in fig. 11.
DETAILED DESCRIPTION OF THE PREFERRED
Fig. 4 shows embodiment according to IC device tester of the present invention with the square form.The present invention adopts optical cable to be connected tester main system 200 and measuring head 100 with the power lead cable.Utilize optical cable can transmit various test datas, transmit and variously data to be set and to transmit various timing signals.Use by the restriction cable only is used on the power supply it and by adopting optical cable as much as possible to connect can to reduce the volume that is connected cable between tester main system 200 and the measuring head 100.
The DC test component 206, load testing parts 207 and first reference voltage source 208 that are contained in the tester main system 200 shown in Figure 1 are moved in the measuring head 100 in this embodiment, and serial data transceiver 212 and light I/O (I/O) module 213 are contained in the tester main system 200.On the other hand, switching part 110 is contained in the measuring head 100, with reference to Fig. 5 switching part 100 is described specially later on.Function element such as DC measurement component, load measure parts and first reference voltage source and switching electronic circuit are housed in the switching part 110.Contain in the light I/O module 213 electric to optic converter 2EO1 to 2EO5 and light/electric transducer 2OE1 to 2OE5.This light I/O module 213 is connected on the switching part 110 of measuring head 100 to OPF10 and optical coupling part 126 by optical fiber OPF1.
Fig. 5 shows the structure of the converting member 110 among Fig. 4 embodiment with the square form, this switching part 110 is delivered to comparative result in the test main system 200 then to supply a pattern signal and to doing simulation relatively from the output signal of terminals P of the terminals P of DUT.
In this example, switching part 110 comprises switching electronic circuit 102A, junction matrix translation circuit 105, local switching controller 111, DC test component 116 and light I/O module 113, wherein, driver 103A, analog comparator 104A and the load testing circuit 117 of a terminals P that is used to drive DUT is equipped with in switching in the electronic circuit.
Light I/O module 113 have light/electric transducer OE1 to OE5 and electric to optic converter EO1 to EO5, by light/electric transducer OE1 to OE5 its in the future the light signal of self-test device main system 200 convert electric signal to, these signals can be used for carrying out function and test with DC.
That is to say, the magnitude of voltage of the H logic voltage VIH that confession driver 103A uses and the magnitude of voltage of L logic voltage VIL and comparative voltage VOH and the VOL that uses for analog comparator 104A are stored among the registers group 111B, thereby registers group 111B offers D/A converter 111E with these voltage signals with the form of parallel data again and converts analog voltage to, and these analog voltages are provided for driver 103A and analog comparator 104A then.In addition, the work test condition of load testing circuit 117 also is stored among the registers group 111B, thereby also can be used for load testing from the data that registers group 111B reads.
Be stored among the registers group 111C is that DC tests necessary control signal and DC test result, for example, in test pattern (the current measurement pattern of the voltage measurement pattern/impressed voltage of impressed current), the setting of control signal control impressed voltage/current value, measurement range setting, the termination of measurement initial sum etc.When needs, test result can be sent to by serial data transceiver 111A and convert light signal TX on the electric to optic converter EO1 to, and then is sent in the tester main system 200.
Be stored among the registers group 111D is the control signal that is used to control junction matrix translation circuit 105.This control signal is imported into removes control switching electronic circuit 102A and junction matrix translation circuit 105 among the relay and control circuit 111F, thereby makes the corresponding state of test pattern that they are in and are set up.That is, in the work test process, driver 103A and analog comparator 104A are connected to that DC test component 116 then disconnects with it on the terminals P of DUT.In the DC test process, the pin portion of switching electronic circuit 102A and DUT separates on the pin P that DC parts 116 then are connected to DUT.
Like this, local switching controller 111 according to test pattern with the condition setting of each terminals P in registers group 111B, 111C and 111D.Because being the forms with light serial signal RX, the data among registers group 111B to be deposited, 111C and the 111D send, therefore as long as just enough as their transmission line with an optical fiber OPF1, the light signal RX that transmits in optical fiber OPF1 is input among the serial data transceiver 111A by after light/electric transducer OE1 converts electric signal to again.
In this example, when needing, can from registers group 111B, 111C and 111D, read the various data that are provided with that they store, by electric to optic converter EO1 these data-switching are become light signal TX then, by optical fiber OPF2 light signal TX is sent back in the tester main system 200 again, in this process, need the setting of checkout device whether correct.
Optical fiber OPF3 is the mode signaling line, and it transmits the mode signal that is applied on the terminals P with the form of light signal PAT.Mode signal PAT is input on the driver 103A that is contained in the switching electronic circuit 102A after being converted to electric signal by light/electric transducer OE2 again, thereby is input on the terminals P.
That transmit in optical fiber OPF4 is driver control signal DRE, and this signal DRE is used for the state of Control Driver 103A in functional test procedures.Under the situation that reads answer signal from DUT, control signal DRE makes the output of driver 103A in high-impedance state, can effectively be read among the analog comparator 104A so that reply output signal.
Optical fiber OPF5 and OPF6 are the strobe pulse transmission lines, and they transmit the strobe pulse of analog comparator 104A respectively with the form of light signal STRB-H and STRB-L, and wherein strobe pulse is in order to determine the comparison moment of H logic level and L logic level.Light signal STRB-H is the pulse that is used for the H logic simulation cycle of the signal that gating reads from DUT, and light signal STRB-L is the pulse that is used for the L logic simulation cycle of gating read output signal.
Light signal STRB-H and STRB-L are converted to by light/electric transducer OE5 and OE6 and are re-used as strobe pulse behind the electric signal and are applied on the analog comparator 104A.
Optical fiber OPF7 and OPF8 are from the transmission line of measuring head 100 to tester main system 200 loopback strobe pulses.The strobe pulse RSTRB-H and the RSTRB-L that are sent back to tester main system 200 provide time-delay by the side circuit arrangement, between time delay, they move between tester main system 200 and analog comparator 104A, and are used as the strobe pulse that is contained in the logic comparator in the tester main system 200.That is, the judged result of analog comparator 104A is sent in the tester main system 200 from optical fiber OPF7 and OPF8 after converting light signal to, and is input in the logic comparator; In this case, for transmission delay time of making judged result and the delay time of strobe pulse conform to each other, strobe pulse is moved between tester main system 200 and measuring head 100.Optical fiber OPF9 and OPF10 are the judged results with analog comparator 104A, and promptly the functional test results of DUT sends back to transmission line in the tester main system 200 with SH and SL form in this example.
As mentioned above, embodiment shown in Figure 4 provides signal exchange between tester main system and the measuring head 100 by means of 10 optical fiber corresponding to each terminals P of DUT.Even adopt 500 millimicrons of relatively large plastic optical fibers of diameter, the diameter of the fibre bundle of 10 optical fiber compositions also is very little, even also much smaller than cable group 300 (see figure 3)s by the diameter of the fibre bundle of forming corresponding to 1000 optical fiber of 1000 IC terminals.Although strobe pulse RSTRB-H that above usefulness is returned and RSTRBR-L provide comparison regularly for logic comparison 203, but can also produce logic comparison timing signal and it is offered logic comparator 203 with timing generator 205, shown in dotted line, this situation does not need optical fiber OPF7 and OPF8, so the quantity of the corresponding minimizing optical fiber of energy.On the other hand, can adopt such structure: only with the analog comparator 104A that deposits the analog comparator of function as measuring head 100 not with lock, thereby it is compared continuously and do not need to provide strobe pulse STRB-H and STRB-L to it, then constantly in the timing of strobe pulse STRB-H and STRB-L, sample in tester main system 200 side compared result, and sampled data is offered logic comparator 203.
Fig. 6 shows the framework of switching part that is used for each element shown in Figure 5 is installed together each pin of DUT.The electrical cnnector 114 that switching electronic circuit 102A, junction matrix translation circuit 105, light I/O module 113, the power supply source that the integrated circuit component, the integrated circuit component that constitutes DC test component 116 that constitute local switching controller 111 is housed on the wiring board 110B in cabinet 110A, contains driver 103A and analog comparator 104A and load testing circuit 117 used, be used for the connector 115 that is connected or separates with capability test board.Label 112 expression heat radiator.
Fig. 7 shows a kind of being used for switching part 110 is installed to member on the measuring head 100.Label 121 expression photoelectricity compoboards.This photoelectricity compoboard 121 has structure shown in Figure 8.In the fitting surface of multilayer circuit layer 122 an optical fiber embeding layer 123 is arranged, the inner optical fiber OPF that is 45 ° of oblique angles shown in S1 is embedded in the optical fiber embeding layer 123 side by side; The angled end-face of every optical fiber is facing to circuit layer 122, so that the propagation luminous energy in the optical fiber is reflected out with the direction vertical with PCB surface, the light I/O module 113 that is contained in the switching part 110 (Fig. 6) is placed along reflection direction, thereby sets up optically-coupled between the light I/O module 113 in optical fiber OPF and switching part 110.
The other end of optical fiber OPF is exposed on the end face of wiring board.Optical cable 124 (see figure 7)s extend to exposing on the end face S2 of optical fiber OPF by optically-coupled from tester main system 200 (not expressing Fig. 7), and tester main system 200 can couple together by optical transmission line with the switching part 110 that is contained in measuring head 100 1 sides.By the way, the electrical cnnector 114 that is contained in the switching part 110 (Fig. 6) is connected on the circuit layer 122 by common electric connecting elements, and then is connected on the tester main system 200 by circuit layer 122.
Among Fig. 7, the feed cable that label 125 expressions extend out from tester main system 200, the optical coupling part that label 126 representatives form on photoelectricity compoboard 121 surfaces, label 127 is represented electrical cnnector.By the electrical cnnector 114 on light I/O module 113 and the switching part 110 is connected respectively on optical coupling part 126 and the electrical cnnector 127, switching part 110 is connected on the tester main system 200.
The switching part 110 of requirement a large amount of optical coupling part 126 and electrical cnnector 127 arranged, so that can be installed on the surface of photoelectricity compoboard 121.Although in the above description photoelectricity compoboard 121 is used for being connected between switching part 110 and the optical cable 124, but needn't always adopt photoelectricity compoboard 121, also can switching part 110 and optical cable 124 be coupled together in this case with the optical connector that is contained in the circuit layer surface.On the other hand, by respectively optical connector and electrical cnnector being connected respectively to the end of optical cable 124 and cable 125, optical cable 124 and cable 125 are directly connected on the switching part 110.
In Fig. 7, label 128 expression cooling systems, it can make mechanical support to switching part 110, has refrigerating function simultaneously again.This cooling system 128 has some parts mounting hole 128A, such as being double-layer clapboard, can be used as cooling-water duct between the double-layer clapboard around the mounting hole 128A.Label 128B, 128C represent the inlet and the outlet of chilled water respectively.
The endways electrical cnnector of having placed on the top end face of switching part 110, switching part 110 is connected on the capability test board 101 by these electrical cnnectors.By the way, Fig. 7 shows such a case: a plurality of switching part 110-A that are used to connect tested IC equipment are directly installed on the end face of capability test board 101 so that reduce the length of circuit; Therefore, this structure is particularly suitable for testing High Speed ICs equipment.
Fig. 9 shows an alternative embodiment of the invention.The formatter 202 and the logic comparator 203 that are contained in the tester main system 200 embodiment illustrated in fig. 4 are moved on the measuring head 100 in this embodiment, thereby saved the gating signal exchange between tester main system 200 and the measuring head 100, thereby the corresponding quantity that reduces used optical fiber.Therefore, the mode data PAD that mode generator 201 produces converts light signal to by electric to optic converter 2EO2, this light signal is input to by optical fiber OPF3 in the switching part 100 of measuring head 100, and waveform shown in Figure 10 or form controller 130 produce the test mode signal of actual waveform according to mode data PAD and it is applied on the DUT.Answer signal from DUT compares with expectation value in switching part 110, comparative result (fail data) FDAT is sent in the main system 200 by optical fiber OPF7 after being transferred into light signal, in main system 200, it is converted to electric signal by light/electric transducer 2OE2 again, and then is written in the dead-file 204.
The accurate Control work that makes timing generator 205 shown in Figure 4 produce the delay time shorter than the clock period is finished in the first side of test.Timing generator 205 clocking CLK, with the clock period standard signal RATE that postpones to control of unit and the accurate delay control data DCT that is used for accurate delay control, these signals convert light signal to by electric to optic converter 2EO4,2EO5 and 2EO3, and these light signals send measuring head 100 to by optical fiber OPF5, OPF6 and OPF4.
As shown in figure 10, waveform or form controller 130, local switching controller 111 and DC test component 116 are housed in the measuring head 100, this configuration produces mode signal with form controller 130 and carries out the part and relatively work.Promptly, also be equipped with serial data transceiver 131 in the form controller 130,131 pairs of serial data transceivers receive by the serial signal from the test pattern data PAD of mode generator 201 (Fig. 9) that optical fiber OPF3 transmits, and it is offered formatter 132, formatter 132 produces the analog waveform mode signals.
For fear of the size that increases measuring head 100, just the accurate delay circuit DY2 among Fig. 1 is moved on to the first side of test from the timing generator 133 of Fig. 1, so that reduce the circuit scale of the timing generator 133 in the measuring head 100.Therefore, in this embodiment, by thick delay circuit DY1 is that the full sized pules that unit did slightly to delay time is converted to light signal by electric to optic converter 2EO5 with the clock period in tester main system 200, and this light standard pulse RATE is sent in the switching part 110 by optical fiber OPF4.This light signal converts full sized pules RATE to by light/electric transducer OE3 again, and be imported in the timing generator 133 with the form of electric standard pulse RATE, 133 pairs of these full sized puless of timing generator RATE makes accurate delay and it is assigned on the associated components as timing signal.Accurate delay control data DCT is input to the timing signal controller 135 from optical fiber OPF5 by serial data transceiver 131.Timing signal controller 135 is controlled timing generator 133 according to this accurate delay control data DCT.
The test pattern data PAD (digital signal) that 134 pairs of logic comparators are input to formatter 132 carries out logic relatively with answer signal from DUT, and comparative result sent to serial data transceiver 131 as disablement signal FDAT, this comparative result is sent to electric to optic converter EO5 again thus to convert light signal to, sends by optical fiber OPF7 then.
Figure 11 shows the block scheme of another embodiment of the present invention.This embodiment further moves on to the first side of test shown in Figure 9 with mode generator 201, dead-file 204 and timing generator 205, and in tester main system 200, increased serial data transceiver 214, necessary data take place with optical fiber OPF4 transfer mode in this configuration, and with optical fiber OPF5 acceptance test result.The used optical fiber total amount of this structure is lacked than used optical fiber total amount embodiment illustrated in fig. 9.
In order to produce mode signal, timing memory 141, mode memory 142 and dead-file 143 can be contained in the switching part 110 of measuring head 100, as shown in figure 12 with form controller 130 in the first side of test.
Serial data transceiver 214 stores for it to the mode data RXX that mode memory 142 sends the serial signal form by optical fiber OPF4 in advance.In addition, at one's leisure between in serial data transceiver 214 store for it to timing memory 141 forward delay interval control datas (timing data) by optical fiber OPF5.Therefore, before test beginning, just the data for all terminals uses of DUT can be sent to from tester main system 200 in each switching part 110 measuring head 200 and store.
When beginning to test, mode data PAD is read out and is provided for formatter 132 from mode memory 142, convert the analog waveform mode signal to by formatter 132 again.When mode data PAD was read out, time-delay control data PAD was also read out and is provided for timing generator 133 from timing memory, and timing generator 133 produces the standard signal RATE that represents test period according to clock signal clk again.Standard signal RATE postponed corresponding to the very short time interval that postpones control data DCT, thereby the generation timing signal is determined each rise and fall of comparing the moment and mode signal moment etc. thereby these timing signals are provided for formatter 32, analog comparator 104A and logic comparator 134.
For example, when logic comparator 134 detected the situation that do not match of representative inefficacy, the inefficacy that the H logical signal just is written in the dead-file 143 took place in the address.During in test idle period of time or in end of test (EOT), so be stored in fail data (test result) in the dead-file 143 and be sent to by memory bus MBUS and serial data transceiver 131 and convert light signal TXX on the electric to optic converter EO2 to, this light signal is sent in the tester main system 200 by optical fiber OPF5 again.Effect of the present invention
As mentioned above, according to the present invention, data, clock and other signal of exchange all transmit with optical fiber between tester main system 200 and measuring head 100.The diameter maximum of this optical fiber be 500 millimicrons, it is more much smaller than cable size.Therefore, even used number of fibers is identical with the quantity of general cable, the diameter of fibre bundle is also much smaller than the diameter of bunch of cables.In addition, because optical fiber is lighter than cable, so the very light in weight of fibre bundle is easy to use.
By adopting Fig. 9 or serial data transceiver 111A and 131 shown in Figure 11 can reduce the quantity of cable.Specifically, under situation, can in common fiber, transmit different signals with as shown in figure 11 mode memory 142, timing memory 141 and dead-file 143.Therefore, the used number of fibers of each terminal of DUT can reduce to about six roots of sensation, as shown in figure 11.This makes the connection tester main system 200 and the diameter of the cable group 300 of measuring head 100 reduce.
Because optical fiber can not produce big decay and not have light to leak light, so tester main system 200 can a good distance off distance with measuring head 100.So, the tester main system 200 that produces big calorimetric can be placed on different places with measuring head 100, perhaps for example, only measuring head is placed in the toilet.In addition, owing to, therefore do not need to provide terminating resistance for every transmission line with the various signals of light signal exchange.This also helps to reduce the heat that tester produces.
Obviously, many modifications can be made in new thought range of the present invention and change.
Claims (14)
1. integrated circuit device tester, it is under the control of processor controls, produce mode data and expected data by mode generator, by formatter described mode data is formatted into the preassigned pattern waveform, by driver described mode waveform is applied on the tested IC equipment with the reference voltage form, by analog comparator will from the answer signal of described tested IC equipment with compare with reference to logic level, make logic determines then, logical and after will being judged by logic comparator compares from the expected data of described mode generator, to judge that described tested IC equipment is substandard products or certified products, and fail data is written in the dead-file, described IC device tester comprises:
The tester main system of described processor controls is housed;
Be contained in the first serial data transceiver devices that is used to export serial data in the described tester main system, it is used to described driver that described reference voltage is set and is provided with described with reference to logic level for described analog comparator;
Be contained in the electric to optic converter device in the described tester main system, it is used for converting described serial data to light signal;
Measuring head with described driver and analog comparator, wherein, described driver is used for test pattern is applied to described IC equipment, and analog comparator is used to judge the logic of replying of described IC equipment;
Be contained in the light/electrical converter device in the described measuring head, it is used for described light signal is converted to the serial data of electric signal;
Be contained in the second serial data transceiver devices in the described measuring head, it is used for converting described serial data to parallel reference voltage data and parallel with reference to the logic level data;
Be contained in the D/A converter device in the described measuring head, it is used for described parallel reference voltage data and describedly parallelly converts analog reference voltage respectively to and with reference to logic level with reference to the logic level data, and these transformation results are set to respectively on described driver and the described analog comparator; With
Fiber device, it is used for described electric to optic converter device and described light/electrical converter device are coupled together.
2. tester according to claim 1, the wherein said second serial data transceiver devices comprise and are used to preserve received serial data and are used for various the register setting that parallel data form is exported these signals being set.
3. tester according to claim 2, also comprise the DC test component that is contained in the described measuring head, in tester, described tester main system is sent to the form of control signal with the light serial signal on the described DC test component, thereby control described DC test component tested IC equipment is carried out the DC test.
4. tester according to claim 3, stored the data and the DC test result that are provided with for each terminal in the described register setting of the wherein said second serial data transceiver devices in described measuring head, and data have been set and described DC test result is sent in the described tester main system with light serial signal form described.
5. tester according to claim 4, wherein: the mode signal of waiting to be applied on the described tested IC equipment is input on the described measuring head from described tester main system as the form to the light signal of each terminal of described tested IC equipment, and is applied on the described tested IC equipment by the described driver that is contained in the described measuring head; The signal of reading from described tested IC equipment is checked by described analog comparator so that determine whether this signal has normal H or L logic level; Convert the light serial signal with the judged result of doing for described each terminal of described tested IC equipment to by described electric to optic converter device, and send described tester main system to by described fiber device.
6. tester according to claim 3, wherein: the 3rd serial data transceiver devices, described formatter and described logic comparator promptly are set in the described measuring head corresponding to every butt lead-in wire of described tested IC equipment; The figure pattern data of using for described each terminal are sent on the described measuring head from described tester main system with light serial signal form, and are received and convert to the parallel schema data by described the 3rd serial data transceiver devices; Described parallel schema data are converted to the simulation model signal by described formatter; Described mode signal is applied on described each terminal by described driver; The signal that reads out from described tested IC equipment is detected by described analog comparator so that determine whether its logic level is normal; This judged result with on described logic comparator, carry out logic relatively from the digital desired pattern data of described tester main system; Be sent in the described tester main system by the form of described the 3rd serial data transceiver devices with the logic comparative result with the light serial signal.
7. tester according to claim 6, wherein: be provided with timing generator in the described measuring head; The digital timing data that transmits with light serial signal form is provided for described timing generator later on being converted to parallel signal by described the 3rd serial data transceiver devices; And the work of described formatter, described logic comparator and described analog comparator is subjected to the control from the timing signal of described timing generator.
8. tester according to claim 3, wherein: be provided with mode memory, dead-file and timing memory in the described measuring head; Be stored in advance in these storeies from mode data and the timing data that described tester main system is sent to described mode memory and the described timing memory with the light signal form; In the test beginning, described mode data and described timing data are read out and are provided for described formatter and described timing generator from described mode memory and described timing memory, produce mode signal and timing signal by them again; The functional test of described IC equipment is carried out with described mode signal and described timing signal; The result of described functional test is obtained and is stored in the described dead-file by described logic comparator; Be sent in the described tester main system by form with described storage data with light signal.
9. integrated circuit device tester, it is under the control of processor controls, produce mode data and expected data by mode generator, by formatter described mode data is formatted into the preassigned pattern waveform, by driver described mode waveform is applied on the tested IC equipment with the reference voltage form, by analog comparator will from the answer signal of described tested IC equipment with compare to make logic determines with reference to logic level, logical and after will being judged by logic comparator compares from the expected data of described mode generator, to judge that described tested IC equipment is substandard products or certified products, fail data is written in the dead-file, and described IC device tester comprises:
Tester main system with described processor controls, described mode generator, described formatter, described logic comparator and described dead-file;
Be contained in the first electric to optic converter device in the described tester main system, it is used for the test pattern waveform transformation of described formatter output is become light signal;
Measuring head with described driver and described analog comparator;
Be contained in the first light/electrical converter device in the described measuring head, the test pattern waveform transformation that it is used for offering it with the light signal form becomes the test pattern waveform of electrical signal form, and the latter is applied on the described driver;
Be contained in the second electric to optic converter device in the described measuring head, it is used for converting the comparative result of described analog comparator to light signal;
Be contained in the second light/electrical converter device in the described tester main system, the described comparative result that it is used for offering it with described light signal form converts electric signal to, and the latter is applied on all logic comparators;
First fiber device that connects the input end of the output terminal of the described first electric to optic converter device and described first light/electrical converter device, it be used for from the former backward the person transmit the test pattern light signal; With
Second fiber device that connects the input end of the output terminal of the described second electric to optic converter device and described second light/electrical converter device, it be used for from the former backward the person transmit the comparative result light signal.
10. tester according to claim 9 also comprises:
Be contained in the first serial data transceiver devices in the described tester main system, it is used for exporting the data of the described reference voltage of using for described driver of setting and setting the described data of using for described analog comparator with reference to logic level with serial data form;
Be contained in the 3rd electric to optic converter device in the described tester main system, it is used for converting described serial data to light signal;
Be contained in the 3rd light/electrical converter device in the described measuring head, it is used for converting described light signal to the electric signal serial data;
Be contained in the second serial data transceiver devices in the described measuring head, it is used to receive described serial data and these data is exported with parallel reference voltage data with parallel form with reference to the logic level data;
Be contained in the D/A converter device in the described measuring head, it is used for described parallel reference voltage data and describedly parallelly converts analog reference voltage respectively to and with reference to logic level with reference to the logic level data, and these transformation results are set to respectively on described driver and the described analog comparator; With
The 3rd fiber device that connects described the 3rd electric to optic converter device and described the 3rd light/electrical converter device.
11. tester according to claim 10, the wherein said second serial data transceiver devices comprises the register setting that is used to preserve received serial signal data and is used for exporting with the parallel data form of various settings these signals.
12. tester according to claim 11, also comprise the DC test component that is contained in the described measuring head, in tester, described tester main system is sent to the form of control signal with the light serial signal on the described DC test component, thereby controls described DC test component to carried out the DC test by IC equipment.
13. tester according to claim 12, stored data and DC test result that each terminal for described tested IC equipment is provided with in the described register setting of the wherein said second serial data transceiver devices in described measuring head, and data have been set and described DC test result is sent in the described tester main system with light serial signal form described.
14. according to claim 3,4,12 or 13 described testers, also comprise the junction matrix translation circuit that is located in the described measuring head, it is used for selectively the output terminal of described output end of driver and described DC test component is connected to described tested IC equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97191480 CN1206467A (en) | 1996-11-15 | 1997-11-13 | Integrated circuit device tester |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP304933/96 | 1996-11-15 | ||
| CN 97191480 CN1206467A (en) | 1996-11-15 | 1997-11-13 | Integrated circuit device tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1206467A true CN1206467A (en) | 1999-01-27 |
Family
ID=5178982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97191480 Pending CN1206467A (en) | 1996-11-15 | 1997-11-13 | Integrated circuit device tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1206467A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100432689C (en) * | 2003-03-31 | 2008-11-12 | 爱德万测试株式会社 | Test device and test method |
| CN100465656C (en) * | 2004-10-14 | 2009-03-04 | 横河电机株式会社 | Integrated circuit test device |
| CN101738578A (en) * | 2009-12-24 | 2010-06-16 | 成都市华为赛门铁克科技有限公司 | Method, device and system for measuring energy consumption of integrated circuits |
-
1997
- 1997-11-13 CN CN 97191480 patent/CN1206467A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100432689C (en) * | 2003-03-31 | 2008-11-12 | 爱德万测试株式会社 | Test device and test method |
| CN100465656C (en) * | 2004-10-14 | 2009-03-04 | 横河电机株式会社 | Integrated circuit test device |
| CN101738578A (en) * | 2009-12-24 | 2010-06-16 | 成都市华为赛门铁克科技有限公司 | Method, device and system for measuring energy consumption of integrated circuits |
| CN101738578B (en) * | 2009-12-24 | 2012-12-19 | 成都市华为赛门铁克科技有限公司 | Method, device and system for measuring energy consumption of integrated circuits |
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