CN1187073A - Low power required input buffer - Google Patents

Low power required input buffer Download PDF

Info

Publication number
CN1187073A
CN1187073A CN97112489A CN97112489A CN1187073A CN 1187073 A CN1187073 A CN 1187073A CN 97112489 A CN97112489 A CN 97112489A CN 97112489 A CN97112489 A CN 97112489A CN 1187073 A CN1187073 A CN 1187073A
Authority
CN
China
Prior art keywords
nmos pass
buffer
pass transistor
transistor
output
Prior art date
Application number
CN97112489A
Other languages
Chinese (zh)
Inventor
郑德柱
Original Assignee
Lg半导体株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR77503/96 priority Critical
Application filed by Lg半导体株式会社 filed Critical Lg半导体株式会社
Priority to CN97112489A priority patent/CN1187073A/en
Publication of CN1187073A publication Critical patent/CN1187073A/en

Links

Abstract

A low power consumption input buffer is disclosed which exhibits reduced power consumption, especially that of a peak current consumed, to make a semiconductor chip operated in a more stable manner. The buffer employs a switching unit to block a current path so as to decrease current consumption. Noise due to a peak in the current during transmission of an input signal is decreased by using a transistor ducting and connecting with outer voltage, so reaching chip operated in a stable manner.

Description

Low power required input buffer

The present invention relates to a kind of input buffer, particularly a kind of low power required input buffer is used to reduce required electric current and peak current, makes the semiconductor chip steady operation.

As shown in Figure 1, comprise according to the input buffer of routine techniques: the 2nd PMOS transistor P2, its source links to each other with external voltage Vcc, and grid link to each other with the output of inverter IN1; The one PMOS transistor P1, its source links to each other with the transistorized leakage of the 2nd PMOS, leaks to link to each other with output OUT, and grid link to each other with input IN; The first nmos pass transistor N1, its leakage links to each other with output OUT, and the source links to each other with ground voltage Vss, and grid link to each other with input IN; The inverter IN1 of receiving chip enabling signal CE; And the second nmos pass transistor P2, its leakage links to each other with output OUT, and grid link to each other with inverter IN1, and the source links to each other with ground voltage Vss.

Working condition below in conjunction with the so conventional input buffer that constitutes of Fig. 1-4 explanation.

At first, when chip start signal CE was high potential, the output valve of inverter IN1 became electronegative potential, so that make the 2nd PMOS transistor P2 conducting, the second nmos pass transistor N2 ends.

At this moment, as shown in Figure 2, when input signal AI was high potential, a PMOS transistor P1 ended, and the first nmos pass transistor N1 conducting is so that output signal AO becomes electronegative potential.

On the contrary, when input signal AI is electronegative potential, a PMOS transistor P1 conducting, the first nmos pass transistor N1 ends, so that output signal AO becomes high potential.

Then, when chip start signal was electronegative potential, the output valve of inverter IN1 kept high potential, so that the 2nd PMOS transistor P2 ends the second nmos pass transistor N2 conducting.Therefore, no matter the level of input signal AI how, output signal AO keeps electronegative potential.

As shown in Figure 4, when adding the logic threshold voltage of about 1.5V for input signal AI, a PMOS transistor P1 and first all conductings of nmos pass transistor N1, the result is because superfluous operating current ISS causes power consumption to increase.

In addition, as shown in Figure 3,,, influence chip operation so produce noise when input signal AI becomes electronegative potential or conversely the time, the peak electricity rheology is big from high potential.

Therefore, the purpose of this invention is to provide a kind of low power required input buffer, reduce power consumption, prevent because the noise due to peak current increases during the input signal conversion to reduce operating current consumption.

To achieve these goals, low power required input buffer according to the present invention comprises: the switch element that carries out ON/OFF (on/off) operation according to input and output signal; Receive, the buffer cell of anti-phase and output input signal; And the operating unit of the output of receiving chip enabling signal control buffer cell.

Fig. 1 is the schematic block diagram of conventional input buffer;

Fig. 2 is a time dependent graph of relation between input signal and output signal in the presentation graphs 1;

Fig. 3 is a peak operation current time history plot in the presentation graphs 1;

Fig. 4 is the curve chart that operating current changes with input signal in the presentation graphs 1;

Fig. 5 is the schematic diagram according to the input buffer of the low power required input buffer of first embodiment of the invention;

Fig. 6 is a time dependent graph of relation between input signal and output signal in the presentation graphs 5;

Fig. 7 is a peak operation current time history plot in the presentation graphs 5;

Fig. 8 is the curve chart that operating current changes with input signal in the presentation graphs 5;

Fig. 9 is the schematic block diagram according to the second embodiment of the invention low power required input buffer;

Figure 10 is a time dependent graph of relation between input signal and output signal in the presentation graphs 9;

Figure 11 is a peak operation current time history plot in the presentation graphs 9;

Figure 12 is the curve chart that operating current changes with input signal in the presentation graphs 9.

As shown in Figure 5, the low power required input buffer according to first embodiment of the invention comprises: the switch element 10 that blocks operating current ISS path; Receiving inputted signal AI and output are by the buffer cell 20 of the anti-phase output signal AO of input signal AI; And receiving chip enabling signal CE also controls the operating unit 30 from the output of buffer cell 20.

Switch element 10 comprises: PMOS transistor P3, and its grid link to each other with input IN, leak to link to each other with external voltage Vcc, and the source links to each other with buffer cell 20; And nmos pass transistor N3, its grid link to each other with output OUT, and the source links to each other with external voltage Vcc, leaks to link to each other with buffer cell 20.

Buffer cell 20 comprises: PMOS transistor P5, and its leakage links to each other with switch element 10, and the source links to each other with output OUT; PMOS transistor P4, its grid link to each other with input IN, leak to link to each other with the grid of PMOS transistor P5, and the source links to each other with operating unit 30; Nmos pass transistor N4, its grid link to each other with input IN, and the source links to each other with output OUT; Nmos pass transistor N5, its grid link to each other with external voltage Vcc, and the source links to each other with nmos pass transistor N4, leaks to link to each other with operating unit 30.

Operating unit 30 comprises: nmos pass transistor N6, and its grid link to each other with chip start signal CE, leak to link to each other with buffer cell 20, and the source links to each other with ground voltage Vss; The inverter IN2 of receiving chip enabling signal CE; And nmos pass transistor N7, its grid link to each other with inverter IN2, leak to link to each other with output OUT, and the source links to each other with ground voltage Vss.

Below in conjunction with the such working condition that constitutes of Fig. 5-8 explanation according to low-power consumption buffer of the present invention.

At first, when chip start signal CE is high potential, nmos pass transistor N6 conducting, nmos pass transistor N7 ends.At this moment, nmos pass transistor N5 keeps conducting.

Then, when chip start signal CE is high potential, nmos pass transistor N6 conducting, nmos pass transistor N7 ends.At this moment, nmos pass transistor N5 keeps conducting.

As shown in Figure 6, when input signal was high potential, PMOS transistor P4 ended, and nmos pass transistor N4 conducting is so that output signal AO becomes electronegative potential.

On the contrary, when input signal AI is electronegative potential, PMOS transistor P3, P4, P5 conducting, nmos pass transistor N4 ends, so that output signal AO becomes high potential.

In addition, when chip start signal CE was electronegative potential, nmos pass transistor N6 ended, and nmos pass transistor N7 conducting is so that output signal AO is no matter how the level of input signal AI keeps electronegative potential always.

As shown in Figure 9, except that switch unit 10, low-voltage input buffer according to second embodiment of the invention is identical with the buffer shown in Figure 5 of showing first embodiment of the invention, the switch element of this embodiment comprises: PMOS transistor P6, its grid link to each other with the output of inverter IN2 in the operating unit 30, and the source links to each other with external voltage Vcc; PMOS transistor P3, its grid link to each other with input IN, leak to link to each other with the leakage of PMOS transistor P6, and the source links to each other with buffer cell 20; Nmos pass transistor N3, its grid link to each other with output OUT, and the source links to each other with the leakage of PMOS transistor P6, leaks to link to each other with buffer cell 20.

Below in conjunction with the working condition of Fig. 9-12 explanation according to input buffer of the present invention.

At first, when chip start signal CE is high potential, nmos pass transistor N6 conducting, nmos pass transistor N7 ends, PMOS transistor P6 conducting.

Here, during standby mode, be high potential, and when adding M signal, electric current can flow through PMOS transistor P3 and the nmos pass transistor N3 that is one another in series in the switch element 10 when making input signal AI, PMOS transistor P6 is as the switch of electric current.At this moment, nmos pass transistor N5 keeps conducting.

As shown in figure 10, when input signal AI was high potential, PMOS transistor P4 ended, and nmos pass transistor N4 conducting is so that output signal AO becomes electronegative potential.

On the contrary, when input signal AI is electronegative potential, PMOS transistor P4 conducting, nmos pass transistor N4 ends, so that output signal AO becomes high potential.

Then, when chip start signal CE was electronegative potential, nmos pass transistor N6 ended, nmos pass transistor N7 conducting, and PMOS transistor P6 ends, so that output signal AO is no matter how input signal AI all keeps electronegative potential.

Therefore, when output signal AO became electronegative potential, nmos pass transistor N3 ended, and input signal AI keeps high potential, so that PMOS transistor P3 conducting is blocked the current path from external voltage Vcc to ground voltage Vss, thus to reduce current drain.

Yet when output signal AO was high potential, nmos pass transistor N3 became conducting, because input signal AI is an electronegative potential, so PMO transistor P3 becomes conducting.

In addition, because input signal AI is an electronegative potential, nmos pass transistor N4 change ends.

And nmos pass transistor N5 length-width ratio difference is very little, and this reduces its resistance, thereby has reduced current drain.

As mentioned above, and shown in Fig. 6-9, because the current path in the switch element 10 blocks, nmos pass transistor N5 has big resistance, so, to compare with routine techniques, low-power consumption buffer according to the present invention can make operating current ISS greatly reduce.

And, shown in Fig. 8-11, in low-power consumption buffer according to the present invention, because the eternal conducting of nmos pass transistor N5, so, to compare with routine techniques, peak current greatly reduces, thereby has reduced noise, has realized steady operation.

Claims (18)

1. low power required input buffer comprises:
Carry out the switch element of ON/OFF (on/off) operation according to input and output signal;
Receive, the buffer cell of anti-phase and output input signal; And
The receiving chip enabling signal is with the operating unit of the output of control buffer cell.
2. according to the buffer of claim 1, it is characterized in that switch element comprises a PMOS transistor and first nmos pass transistor parallel with one another.
3. according to the buffer of claim 2, it is characterized in that first nmos pass transistor carries out on/off operation according to input signal, a PMOS transistor carries out on/off operation according to output signal.
4. according to the buffer of claim 1, it is characterized in that buffer cell comprises:
The 2nd PMOS transistor of receiving inputted signal;
Be series at output in the switch element and the 3rd PMOS transistor and first nmos pass transistor between the operating unit mutually.
5. according to the buffer of claim 4, it is characterized in that the transistorized leakage of the 2nd PMOS links to each other with the transistorized grid of the 3rd PMOS, the 2nd PMOS transistor receiving inputted signal, the 2nd PMOS transistor and second nmos pass transistor source separately are connected to operating unit altogether.
6. according to the buffer of claim 1, it is characterized in that described output signal is added to the leakage of the transistorized source of the 3rd PMOS and second nmos pass transistor.
7. according to the buffer of claim 4, also comprise, be one another in series in the output of switch element and the 3rd PMOS transistor and second nmos pass transistor between the operating unit second nmos pass transistor of connecting with second nmos pass transistor.
8. according to the buffer of claim 7, it is characterized in that external voltage is applied to the input of the 3rd nmos pass transistor, to carry out stable work.
9. according to the buffer of claim 1, it is characterized in that operating unit comprises:
The 4th nmos pass transistor of receiving chip enabling signal, this transistor are connected between buffer cell and the ground voltage;
The inverter of receiving chip enabling signal; And
Receive the 5th nmos pass transistor of the output valve of inverter, this transistor is connected between output signal end and the ground voltage.
10. low power required input buffer comprises:
Carry out the switch element of ON/OFF (on/off) operation according to input and output signal;
Receive, the buffer cell of anti-phase and output input signal;
The operating unit of the output of receiving chip enabling signal control buffer cell; And
Be connected on the 4th PMOS transistor between external voltage and the closing and opening device, be used to receive the output of inverter.
11. the buffer according to claim 10 is characterized in that, switch element comprises a PMOS transistor and first nmos pass transistor that is connected in parallel to each other.
12. the buffer according to claim 11 is characterized in that, first nmos pass transistor carries out on/off operation according to input signal, and a PMOS transistor carries out on/off operation according to output signal.
13. the buffer according to claim 10 is characterized in that, buffer cell comprises:
The 2nd PMOS transistor of receiving inputted signal;
Output in switch element and the 3rd PMOS transistor and first nmos pass transistor between the operating unit are one another in series.
14. buffer according to claim 13, it is characterized in that, the transistorized leakage of the 2nd PMOS links to each other with the transistorized grid of the 3rd PMOS, the 2nd PMOS transistor receiving inputted signal, and the 2nd PMOS transistor and second nmos pass transistor source separately are connected to operating unit altogether.
1 5. buffers according to claim 10 is characterized in that, add output signal for the leakage of the transistorized source of the 3rd PMOS and second nmos pass transistor.
16. the buffer according to claim 13 also comprises, is being one another in series in the output of switch element and the 3rd PMOS transistor and second nmos pass transistor between the operating unit second nmos pass transistor of connecting with second nmos pass transistor.
17. the buffer according to claim 16 is characterized in that, external voltage imposes on the input of the 3rd nmos pass transistor, to carry out stable work.
18. the buffer according to claim 10 is characterized in that, operating unit comprises:
The 4th nmos pass transistor of receiving chip enabling signal, this transistor are connected between buffer cell and the ground voltage;
The inverter of receiving chip enabling signal;
Receive the 4th PMOS transistor of the output of inverter;
Receive the 5th nmos pass transistor of the output valve of inverter, this transistor is connected between output signal end and the ground voltage.
CN97112489A 1996-12-30 1997-06-17 Low power required input buffer CN1187073A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR77503/96 1996-12-30
CN97112489A CN1187073A (en) 1996-12-30 1997-06-17 Low power required input buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN97112489A CN1187073A (en) 1996-12-30 1997-06-17 Low power required input buffer

Publications (1)

Publication Number Publication Date
CN1187073A true CN1187073A (en) 1998-07-08

Family

ID=5172296

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97112489A CN1187073A (en) 1996-12-30 1997-06-17 Low power required input buffer

Country Status (1)

Country Link
CN (1) CN1187073A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101860356A (en) * 2009-04-13 2010-10-13 台湾积体电路制造股份有限公司 Level shifters, integrated circuits, systems, and method for operating the level shifters
CN101867363A (en) * 2010-05-25 2010-10-20 中国电子科技集团公司第二十四研究所 LVDS driving circuit with stable difference common-mode voltage
CN101213460B (en) * 2005-05-04 2011-08-31 Nxp股份有限公司 A peak or zero current comparator
CN101707482B (en) * 2009-07-29 2011-12-28 天津理工大学 Profibus device protocol input and output device with short circuit protection and self-diagnosis
CN101577540B (en) * 2008-05-08 2012-07-11 索尼株式会社 Misjudgment correction circuit and optical disk drive
CN101854167B (en) * 2009-03-30 2012-12-12 南亚科技股份有限公司 Ocd driver system with controllable slew rate and related method
CN101663816B (en) * 2007-03-29 2013-04-24 高通股份有限公司 Software programmable logic using spin transfer torque magnetoresistive devices
CN104348476A (en) * 2013-08-07 2015-02-11 南亚科技股份有限公司 Data buffer system and power control method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101213460B (en) * 2005-05-04 2011-08-31 Nxp股份有限公司 A peak or zero current comparator
CN101663816B (en) * 2007-03-29 2013-04-24 高通股份有限公司 Software programmable logic using spin transfer torque magnetoresistive devices
CN103151068B (en) * 2007-03-29 2016-02-17 高通股份有限公司 Use the software programmable logic of spin transfer torque magnetoresistive devices
CN103151068A (en) * 2007-03-29 2013-06-12 高通股份有限公司 Software programmable logic using spin transfer torque magnetoresistive random access memory
CN101577540B (en) * 2008-05-08 2012-07-11 索尼株式会社 Misjudgment correction circuit and optical disk drive
CN101854167B (en) * 2009-03-30 2012-12-12 南亚科技股份有限公司 Ocd driver system with controllable slew rate and related method
CN101860356B (en) * 2009-04-13 2012-09-05 台湾积体电路制造股份有限公司 Level shifters,level shift method, and integrated circuits
CN101860356A (en) * 2009-04-13 2010-10-13 台湾积体电路制造股份有限公司 Level shifters, integrated circuits, systems, and method for operating the level shifters
CN101707482B (en) * 2009-07-29 2011-12-28 天津理工大学 Profibus device protocol input and output device with short circuit protection and self-diagnosis
CN101867363A (en) * 2010-05-25 2010-10-20 中国电子科技集团公司第二十四研究所 LVDS driving circuit with stable difference common-mode voltage
CN104348476A (en) * 2013-08-07 2015-02-11 南亚科技股份有限公司 Data buffer system and power control method

Similar Documents

Publication Publication Date Title
US8225125B2 (en) Power supply selector and power supply selection method
CN100334797C (en) Boost type active interlaced parallel soft switch circuit
AU748163B2 (en) Self-biased power isolator system
CN100578418C (en) Bootstrapping circuit capable of sampling inputs beyond supply voltage
US6750680B2 (en) Semiconductor integrated circuit, logic operation circuit, and flip flop
CN1214526C (en) Current-limited switch with fast transient response
US6927441B2 (en) Variable stage charge pump
KR100744640B1 (en) Clock driver
CN1790912B (en) Semiconductor integrated circuit device
CN1294692C (en) Voltage step down circuit, power source circuit ands emiconductor integrated circuit
JP3372171B2 (en) Semiconductor device
TWI551190B (en) Driving circuit and related error detection circuit and error detection method
CN1244200C (en) Circuit simulating diode
CN1067497C (en) Driving circuit for IGBT
CN101963819B (en) Reference voltage circuit and electronic device
CN1260888C (en) Level drift circuit and active matrix driver
US7233468B2 (en) Level shifter ESD protection circuit with power-on-sequence consideration
US7408399B2 (en) Active driving of normally on, normally off cascoded configuration devices through asymmetrical CMOS
CN1329990C (en) Semiconductor integrated circuit device
TWI437789B (en) Fet switch and method for reducing insertion loss and providing power down protection for the same
US6917239B2 (en) Level shift circuit and semiconductor device
US6242962B1 (en) Level shift circuit having plural level shift stage stepwise changing potential range without applying large potential difference to component transistors
US4363978A (en) Reduced power tristate driver circuit
CN1477773B (en) Electric charge pump circuit based on coupling capacitance share
US20070120578A1 (en) Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMOS Transistors

Legal Events

Date Code Title Description
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
PB01 Publication
C06 Publication
RJ01 Rejection of invention patent application after publication
C12 Rejection of a patent application after its publication