CN1185918C - 具有聚合物厚膜电阻器的平面印刷电路板的制造方法 - Google Patents

具有聚合物厚膜电阻器的平面印刷电路板的制造方法 Download PDF

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CN1185918C
CN1185918C CN00800830.2A CN00800830A CN1185918C CN 1185918 C CN1185918 C CN 1185918C CN 00800830 A CN00800830 A CN 00800830A CN 1185918 C CN1185918 C CN 1185918C
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conductive layer
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格雷戈里·邓恩
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Abstract

一种印刷电路板的制造方法，电路板具有聚合物厚膜(PTF)电阻器，通过提供具有电阻器要淀积的平坦表面的电路板结构提高精度地限定尺寸。要获得需要的板结构，代替牺牲电镀抗蚀膜，使用永久光介质层作为电镀掩模，电解地图形电镀电阻器的互连。可以在印刷PTF电阻器墨之前或之后构图互连。通过淀积工艺确定电阻器的x和z尺寸(分别为宽度和厚度)，同时通过铜端部精确地确定y尺寸(电长度)。

Description

具有聚合物厚膜电阻器的平面印刷电路板的制造方法
本申请由政府支持的DARPA授予的协议No.F33615-96-2-1838完成。政府享有本发明的一定的权利。
本发明一般涉及电路板及其制造。具体地，本发明涉及在电路板上提供平表面以允许丝网印刷具有改进尺寸和电学容差的聚合物厚膜电阻器。
在混合电子电路中使用厚膜电阻器，以提供宽范围的电阻值。所述电阻器通过在基板上印刷，例如丝网印刷厚膜电阻膏或墨形成，所述基板可以为印制布线板(PWB)、柔性电路、或陶瓷或者硅衬底。在有机印制布线板结构中所使用的厚膜墨通常包括导电材料、有利地影响电阻器的最终电性质所使用的各种添加剂、有机粘结剂以及有机媒介物(vehicle)。印刷之后，通常加热厚膜墨，以干燥墨并将它转变为适合于粘附到基板的膜。如果使用聚合物厚膜(PTF)膜，那么有机粘结剂为聚合物基质(matrix)材料，加热步骤用于除去有机媒介物并固化聚合物基质材料。
厚膜电阻器的电阻取决于制造电阻的精确度、电阻器材料的稳定性以及电阻器端部的稳定性。矩形PTF电阻器的“x”和“z”(分别为电阻器的宽度和厚度)通常由丝网印刷工艺决定，而“y”尺寸(电阻器的电长度)由电阻器端部的图形决定。常规的丝网印刷技术通常使用带有要生成的电阻器的正图像开口的模板。称做丝网掩模的模板被放置于要在其上形成电阻器的基板之上并非常接近其表面。然后用PTF电阻性墨填充掩模，在掩模表面上移动刮墨辊，按压墨穿过开口到基板的表面上。通常在淀积墨之前通过附加性(additive)电镀或去除性(subtractive)腐蚀的电解镀板电镀形成铜端部，这两种方法都能够获得高边缘清晰度，能够精确地确定电阻器的电学长度(y)。
与许多其它的淀积工艺相比，丝网印刷为较粗糙的工艺。由此，丝网印刷的PTF电阻器通常局限为大于约一毫米的尺寸，在所述下限，尺寸容差通常大于约±10％。虽然通过使用适当的工艺形成端部可以精确地确定丝网印刷的PTF电阻器的y尺寸(电学长度)，但是通过网目较粗的丝网和淀积后的墨流动根本上限制了对PTF电阻器的x和z(宽度和厚度)尺寸的控制。由于在上印刷电阻性墨的表面的易变性，主要是由于通常厚度约10到35微米的这些电阻器构图的铜互连，使电阻器尺寸的控制进一步复杂。互连妨碍了表面上平滑的辊压操作，导致不完整的丝网图像印刷和电阻器墨不均匀的淀积。因此，用丝网印刷的PTF电阻器不用激光修整(对于复杂的电路来讲往往是一种其难以承受的工艺)很难获得小于±20％的电阻容差。
从以上可以看出，需要一种具有更精确尺寸的PTF电阻器的形成方法。可以使用完全附加性无电电镀来制造基本上与介质共平面的铜互连，生成能提高印刷精确度的平板表面。然而，与电解板电镀和随后的去除性腐蚀相比，无电电镀很慢并且工艺很昂贵。
根据本发明，提供一种具有聚合物厚膜(PTF)电阻器的印刷电路板的制造方法，通过提供具有要淀积电阻器的平坦表面的电路板结构，以改善的精度限定电阻器的尺寸。要获得需要的板结构，代替牺牲电镀抗蚀膜，使用永久光介质层作为电镀掩模，电解地电镀电阻器的互连图形。可以在印刷PTF电阻器墨之前或之后构图互连。通过淀积工艺确定电阻器的x和z尺寸(分别为宽度和厚度)，同时通过铜端部精确地确定y尺寸(电长度)。
本发明的方法通常需要在介质基板上形成第一导电层；在第一导电层中形成开口，露出基板的一部分表面，然后形成介质层，覆盖基板的裸露表面部分，优选第一导电层附近的表面部分；同时露出第一导电层的表面部分。使用介质层做掩模，然后在第一导电层上淀积第二导电层，以便介质层和第二导电层限定了基本上共平面的表面。在优选实施例中，然后除去第一和第二导电层部分，限定由介质层分开的一对端部，之后在介质层和端部上丝网印刷聚合物厚膜电阻性材料，限定了聚合物厚膜电阻器。此外，在限定端部之前，可以在介质层和第二导电层上丝网印刷聚合物厚膜电阻性材料。
如上所述，本领域中的技术人员将理解，由于厚膜电阻器墨被淀积在基本上平坦的表面区域，本发明的方法能制造厚度可被更精确地控制的PTF电阻器。在优选实施例中，虽然和另一实施例相比，对于给定的电阻器尺寸平坦表面区域的表面积较小，但由于足够的局部平面性提供其间并且包含端部，仍然可以实现厚度控制的显著改善。优选实施例的额外优点为可以在印刷之后立即测试PTF电阻器。
从下面详细的说明可以更好地理解本发明的其它目的和优点。
从下面结合附图的说明中，本发明的以上和其它优点将变得更加明显，其中：
图1到12为根据本发明的优选实施例在丝网印刷的PTF电阻器的制造中使用的工艺步骤的剖面和平面图；以及
图13和14分别为图9和10中示出的替代工艺步骤的剖面和平面图。
根据本发明制造聚合物厚膜(PTF)电阻器的工艺步骤呈现在图1到12中，图9和10的替代工艺步骤显示在图13和14中。就形成具有改进厚度容差的PTF电阻器而言，图中所介绍和显示的工艺达到了本发明的有利特点。虽然在图中显示了具体的电阻结构，但本领域中的技术人员应理解可以有多种修改和变形，所述修改和变形在本发明的范围内。
参考图1和2，显示了其上已形成铜膜12的介质基板10。通常，基板10可以为任何适当材料，包括印刷布线板、柔性电路、陶瓷或硅衬底、或其它多层电路的介质层，但也可以使用其它合适的基板和材料。可以通过如无电电镀、电镀、或叠置铜箔的方法形成铜膜12，膜12的适当厚度范围约1到约30微米。虽然优选铜膜12，但本领域中技术人员应理解，膜12可以由其它合适的导电材料形成，例如镍。
铜膜12的选择腐蚀的结果显示在图3和4中，开口14被构图在铜膜12中，露出基板10的表面区域16。常规的掩蔽和腐蚀技术可以用于该工艺步骤，因此不再作进一步详细讨论。图5和6示出了介质层18选择性地形成在部分铜膜12和基板10的裸露表面区域16上。介质层18优选由可光致成像的厚膜聚合物形成，由此可以使用公知的光致成像和显影技术以构图图5和6所示的层18。合适的厚膜聚合物的成分通常包括树脂、感光剂以及硬化剂。树脂成分可以是任何合适的液体树脂或固体树脂，能使树脂混合物容易以液体形式淀积到铜膜12和区域16的表面上，或叠置形成介质层18。可用的树脂包括热塑性树脂、热固性树脂、弹性橡胶及其混合物，和感光材料混合时生成可光致成像的合成物。厚膜聚合物需要的性质包括稳定的物理特性，不仅在介质层18的淀积和光致成像过程中始终保持稳定，而且由于层18被用做电路结构的永久介质层，还要在电路结构的工作环境中仍保持稳定。由于这些原因，环氧树脂类特别适合作为介质层18的树脂，优选的环氧基合成物为可从Ciba-Geigy和VIALUX81购买的PROBELEC，从E.I.du Pont de Nemour&Company购买的干膜材料。
从图6中可以看出，介质层18已光致成像并显影，由此它覆盖了由开口14露出的表面区域16的有限面积和开口14相对侧上铜膜12有限的表面部分。更具体地，介质层18覆盖了表面区域16的中间部分和与表面区域16的中间部分相邻并由中间部分和开口14分开的铜膜12的两个边缘区域。介质层18优选如图所示覆盖在铜膜12的边缘区域上，以允许未对准。由于开口14，位于介质层18之下的铜膜12不连续，以不使将在介质层18上形成的电阻器30短路，从图11和12中可以看出。由介质层18露出的其余部分为由介质层18分开的表面区域16的两侧边区域22，至少铜膜12的部分表面20环绕介质膜18。侧边区域22的目的是容许介质层18的未对准。
为了整个膜12具有电连续性，图5和6中所示的结构允许在铜膜12上电解电镀额外的铜，以便在电镀期间可以施加并保持电位。图7和8示出了已淀积在铜膜12的裸露表面20上的铜层24，由此介质层18和铜层24限定了基本上共平面的表面，从图7中可以容易看出。铜层24优选使用永久介质层18作为电镀抗蚀膜，通过电镀铜膜12(即，“平面镀敷”)形成。从图8中可以看出，铜层24没有淀积在基板10的两个裸露区域22上。介质和铜层18和24的适当厚度约10到约50微米。
在图9和10中，铜层24已被构图，在介质层18的相对两端形成一对端部26。铜层24可以任何合适的方式构图，例如通过涂敷和构图光致抗蚀剂，然后腐蚀铜层24的裸露部分。由于铜层24基本上与介质层18共平面(图7)，因此端部26也基本上与介质层18共平面，如图9所示。图11和12示出了工艺最终步骤的结果，聚合物厚膜电阻性材料28已淀积在介质层18和端部26上形成聚合物厚膜电阻器30。图11示出了在铜膜12中构图开口以防止端部26之间短路的重要性。由于介质层18和端部26提供了局部的平面性，因此和使用现有技术的丝网印刷技术形成PTF电阻器相比，电阻性材料28可以丝网印刷得更均匀。局部的平面性也有利于通过其它方法淀积电阻性材料28，例如用微型笔(micropen)或其它任何合适的模板印刷或直接写淀积。根据常规的做法，通过淀积工艺确定电阻器30的x尺寸(宽度)，而通过铜端部26确定y尺寸(电长度)，铜端部26在板结构上的位置通过构图介质层18使用的光致成像工艺精确地确定。电阻性材料28基本上可以是可以通过丝网印刷或选择淀积方法适当地淀积的任何PTF电阻器墨。适合于丝网印刷的墨的例子为可从日本东京的Asahi Chemical Research Company购买的TU-00-8墨系列。
由图1到12的工艺步骤可以看出，在淀积电阻性材料28之前，限定由铜层24的剩余部分形成的端部26和互连，允许立即测试电阻器30。在图13和14中示出的另一实施例中，在腐蚀铜层24之前，丝网印刷电阻性材料28。腐蚀图13和14中所示结构的铜的结果基本上与图11和12所示的相同。本发明的替代工艺步骤的优点是为改善丝网印刷的电阻性材料28的厚度控制而提供了较大的平面区域。然而其弱点是电阻器30被由铜层24所形成的连续的导电区域与电路的其它部件短路，妨碍了印刷时电阻器30的电测试。
虽然根据特定的实施例介绍了本发明，但显然本领域的技术人员可以采用其它的形式，因此本发明的范围仅由下面的权利要求书限定。

Claims (10)

1.一种具有聚合物厚膜电阻器的平面印刷电路板的制造方法，该方法包括以下各步骤：
在介质基板(10)上形成第一导电层(12)，第一导电层中具有开口(14)，露出了基板的区域(16)，第一导电层具有与所述露出的区域相邻、并由所述露出区域分开的两个边缘区域；
形成介质层(18)，覆盖基板露出区域的中间部分，介质层具有覆盖第一导电层的两个边缘区域的两个端部，第一导电层具有由介质层露出的表面区域，其中通过在第一导电层上淀积光介质材料形成介质层，然后光致成像并显影光介质材料以限定介质层；
在至少与介质层的两个端部相邻的表面区域部分上淀积第二导电层(24)；
除去部分第二导电层和部分第一导电层，由此限定了由介质层分开的一对端部(26)；以及
在介质层和端部上淀积聚合物厚膜电阻性材料(28)，由此限定了聚合物厚膜电阻器(30)。
2.根据权利要求1的方法，其中淀积第二导电层，由此介质层和第二导电层限定了基本上共平面的表面。
3.根据权利要求1的方法，其中通过选自无电电镀、电镀和叠置中的一种方法形成第一导电层。
4.根据权利要求1的方法，其中通过电镀淀积第二导电层。
5.根据权利要求1的方法，其中通过丝网印刷淀积聚合物厚膜电阻性材料。
6.一种具有聚合物厚膜电阻器的平面印刷电路板的制造方法，该方法包括以下各步骤：
在介质基板上形成第一导电层，第一导电层中具有开口，露出了基板的一个区域，第一导电层具有与所述露出的区域相邻、并由所述露出的区域分开的两个边缘区域；
形成介质层，覆盖基板露出区域的中间部分，介质层具有覆盖第一导电层的两个边缘区域的两个端部，第一导电层具有由介质层露出的表面区域，其中通过在第一导电层上淀积光介质材料形成介质层，然后光致成像并显影光介质材料以限定介质层；
在至少与介质层的两个端部相邻的表面区域部分上淀积第二导电层；
在介质层和第二导电层上淀积聚合物厚膜电阻性材料；以及
除去部分第二导电层和部分第一导电层，由此限定了由介质层分开的一对端部，聚合物厚膜电阻性材料和端部限定了聚合物厚膜电阻器。
7.根据权利要求6的方法，其中淀积第二导电层，由此介质层和第二导电层限定了基本上共平面的表面。
8.根据权利要求6的方法，其中通过选自无电电镀、电镀和叠置中的一种方法形成第一导电层。
9.根据权利要求6的方法，其中通过电镀淀积第二导电层。
10.根据权利要求6的方法，其中通过丝网印刷淀积聚合物厚膜电阻性材料。
CN00800830.2A 1999-05-11 2000-02-25 具有聚合物厚膜电阻器的平面印刷电路板的制造方法 Expired - Fee Related CN1185918C (zh)

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