CN118431294A

CN118431294A - Trench gate transistor

Info

Publication number: CN118431294A
Application number: CN202410889022.1A
Authority: CN
Inventors: 韩玉亮
Original assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Current assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Priority date: 2024-07-04
Filing date: 2024-07-04
Publication date: 2024-08-02
Anticipated expiration: 2044-07-04
Also published as: CN118431294B

Abstract

The embodiment of the application relates to a trench gate transistor, which comprises: a layer of semiconductor material comprising a first surface and a second surface opposite each other; a gate trench extending from the first surface of the semiconductor material layer to an interior of the semiconductor material layer, the gate trench including sidewalls and a bottom wall; the gate dielectric layer is positioned in the gate groove and comprises a first dielectric part and a second dielectric part which cover the side wall of the gate groove; the first electric field shielding structure is positioned outside the grid groove and is adjacent to the first medium part; the body region is positioned outside the gate trench and adjacent to the second dielectric part, and the part, close to the gate trench, of the body region is used for forming a channel region; wherein the thickness of the first medium part is larger than that of the second medium part; therefore, by increasing the thickness of the gate dielectric layer adjacent to the non-channel region, the reduction of the input capacitance is realized, the increase of the switching loss of the device is avoided, and the conduction performance of the device is not affected.

Description

Trench gate transistor

Technical Field

The application relates to the technical field of semiconductors, in particular to a trench gate transistor.

Background

Compared with a planar gate transistor, the trench gate transistor can greatly reduce the cell size, thereby greatly improving the current density. For example, compared with a planar gate MOSFET, the performance of the trench gate Metal-Oxide-Semiconductor Field-Effect Transistor field effect transistor (MOSFET) is greatly improved, so that not only can the higher channel mobility be obtained, but also the on-state resistance R _sp is reduced, and the on-state current density and the on-state performance of the device are improved.

However, since the gate dielectric layer of the trench-gate transistor is formed in the gate trench, the gate dielectric layer is usually thin, so that a larger input capacitance C _iss is easily formed, and especially as the channel density increases, the input capacitance of the device also increases, which increases the switching loss of the device.

Disclosure of Invention

Accordingly, embodiments of the present application provide a trench gate transistor to solve at least one of the problems in the background art.

In a first aspect, an embodiment of the present application provides a trench gate transistor, including:

a layer of semiconductor material comprising a first surface and a second surface opposite each other;

A gate trench extending from a first surface of the semiconductor material layer to an interior of the semiconductor material layer, the gate trench including sidewalls and a bottom wall;

the gate dielectric layer is positioned in the gate trench and comprises a first dielectric part and a second dielectric part which cover the side wall of the gate trench;

a first electric field shielding structure located outside the gate trench and adjacent to the first dielectric portion;

A body region located outside the gate trench and adjacent to the second dielectric portion, wherein a portion of the body region adjacent to the gate trench is used to form a channel region;

wherein the thickness of the first medium part is greater than the thickness of the second medium part.

In combination with the first aspect of the present application, in an alternative embodiment, the first dielectric portions and the second dielectric portions are alternately arranged along an extending direction of a sidewall of the gate trench, where the extending direction refers to an extending direction of the sidewall on a plane where the first surface of the semiconductor material layer is located.

With reference to the first aspect of the present application, in an optional embodiment, the first electric field shielding structure further extends below the gate trench; the gate dielectric layer comprises a third dielectric part and a fourth dielectric part which cover the bottom wall of the gate trench; in a direction perpendicular to the first surface of the semiconductor material layer, the projection of the third dielectric portion falls within the range of the projection of the first electric field shielding structure, and the projection of the fourth dielectric portion is not coincident with the projection of the first electric field shielding structure;

Wherein the thickness of the third medium part is greater than the thickness of the fourth medium part.

With reference to the first aspect of the present application, in an optional implementation manner, the method further includes: the grid electrode is positioned in the grid electrode groove and is isolated from the side wall and the bottom wall of the grid electrode groove through the grid dielectric layer; the gate includes a first gate portion adjoining the first dielectric portion from within the gate trench and a second gate portion adjoining the second dielectric portion from within the gate trench;

the line width of the first grid electrode part is smaller than that of the second grid electrode part.

With reference to the first aspect of the present application, in an optional implementation manner, the method further includes:

a drift region located below the channel region;

The second electric field shielding structures are located below the first electric field shielding structures and extend at least partially below the channel regions, so that the width of the drift region located between two adjacent second electric field shielding structures is smaller than the width of the channel regions along the extending direction of the side walls of the gate trenches, and the extending direction refers to the extending direction of the side walls on the plane where the first surface of the semiconductor material layer is located.

With reference to the first aspect of the present application, in an alternative embodiment, the bottom of the first electric field shielding structure is further away from the first surface of the semiconductor material layer than the bottom of the body region, so that a gap exists between the second electric field shielding structure and the body region;

With reference to the first aspect of the present application, in an optional implementation manner, along the extension direction, a width of a portion of the drift region located between two adjacent second electric field shielding structures is smaller than a width of a portion located between two adjacent first electric field shielding structures;

with reference to the first aspect of the present application, in an alternative embodiment, the second electric field shielding structure is spaced from the body by 0.25 μm to 1.2 μm.

With reference to the first aspect of the present application, in an alternative embodiment, the ion doping concentration of the second electric field shielding structure is greater than the ion doping concentration of the first electric field shielding structure.

In combination with the first aspect of the present application, in an alternative embodiment, a width of a portion of the drift region located between two adjacent second electric field shielding structures increases from a direction approaching the gate trench to a direction separating from the gate trench.

With reference to the first aspect of the present application, in an alternative embodiment, the second electric field shielding structure is adjacent to a bottom of the first electric field shielding structure;

In combination with the first aspect of the application, in an alternative embodiment, both the second electric field shielding structure and the first electric field shielding structure are connected to a ground potential.

And the third electric field shielding structure is positioned below the grid electrode groove and has an overlapping area with the first electric field shielding structure, and the third electric field shielding structure is in conductive connection with the first electric field shielding structure through the overlapping area.

The trench gate transistor provided by the embodiment of the application comprises the following components: a layer of semiconductor material comprising a first surface and a second surface opposite each other; a gate trench extending from the first surface of the semiconductor material layer to an interior of the semiconductor material layer, the gate trench including sidewalls and a bottom wall; the gate dielectric layer is positioned in the gate groove and comprises a first dielectric part and a second dielectric part which cover the side wall of the gate groove; the first electric field shielding structure is positioned outside the grid groove and is adjacent to the first medium part; the body region is positioned outside the gate trench and adjacent to the second dielectric part, and the part, close to the gate trench, of the body region is used for forming a channel region; wherein the thickness of the first medium part is larger than that of the second medium part; therefore, by increasing the thickness of the gate dielectric layer adjacent to the non-channel region, the reduction of the input capacitance is realized, the increase of the switching loss of the device is avoided, and the conduction performance of the device is not affected.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

fig. 1 is a schematic perspective view of a trench gate transistor in the related art;

FIG. 2 is a schematic view of a projection along the second direction in FIG. 1;

FIG. 3 is a schematic view of the structure of section A-A of FIG. 1;

FIG. 4 is a schematic view of the structure of section B-B of FIG. 1;

FIG. 5 is a schematic perspective view in section taken along section C-C of FIG. 1;

Fig. 6 is a schematic cross-sectional structure of another trench-gate transistor according to the related art;

Fig. 7 is a schematic perspective view of a trench gate transistor according to an embodiment of the present application;

FIG. 8 is a schematic view of a projection along the second direction in FIG. 7;

FIG. 9 is a schematic view of the structure of section A-A of FIG. 7;

FIG. 10 is a schematic view of the structure of section B-B of FIG. 7;

FIG. 11 is a schematic perspective view in section taken along section C-C of FIG. 7;

fig. 12 is a schematic cross-sectional structure of another trench-gate transistor according to an embodiment of the present application;

FIG. 13 is a schematic view of a trench-gate transistor in a second direction in an alternative embodiment;

fig. 14 is a schematic diagram showing a perspective structure of a trench gate transistor in another alternative embodiment;

FIG. 15 is a schematic view of a projection along the second direction in FIG. 14;

FIG. 16 is a schematic view of the structure of section A-A of FIG. 14;

FIG. 17 is a schematic view of the structure of section B-B of FIG. 14;

FIG. 18 is a schematic perspective view in section taken along section C-C of FIG. 14;

FIG. 19 is a schematic view showing a projection of a trench-gate transistor along a second direction according to still another alternative embodiment of the present application;

FIG. 20 is a schematic view of a trench-gate transistor according to another alternative embodiment of the present application;

Fig. 21 is a schematic diagram showing a perspective structure of a trench gate transistor according to still another alternative embodiment of the present application;

FIG. 22 is a schematic view of the structure of section A-A of FIG. 21;

FIG. 23 is a schematic view of the structure of section B-B of FIG. 21;

Fig. 24 is a graph comparing simulation results of C _iss of a trench gate transistor according to an embodiment of the present application and a trench gate transistor according to a related art.

Reference numerals illustrate:

100. A substrate; 110. a layer of semiconductor material; 111. a first surface; 112. a second surface; 113. a drift region; 114. a JFET region; 120. a gate trench; 121. a sidewall; 122. a bottom wall; 130. a gate dielectric layer; 131. a first medium section; 132. a second medium section; 133. a third medium section; 134. a fourth medium section; 140. a gate; 141. a first gate portion; 142. a second gate portion; 150. a first electric field shielding structure; 157. a P column structure; 158. a P-type shielding layer; 160. a body region; 161. a channel region; 170. a second electric field shielding structure; 180. a third electric field shielding structure; 190. a first electric field shielding structure contact region; 200. a source contact region; 210. an interlayer dielectric layer; 220. a conductive layer; 230. a current diffusion layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures; for example, the device in the figures is flipped.

The trench gate transistor faces the reliability problem of the gate dielectric layer, because the bottom of the gate trench is exposed to the high electric field region in the drift region when the device is in the blocking state, so that the portion of the gate dielectric layer at the bottom of the gate trench is subjected to the high-intensity electric field, and thus degradation of insulation performance and even early breakdown easily occur, and the stability and the service life of the device in long-term operation are reduced. Particularly for a silicon carbide (SiC) -based trench gate transistor, the critical breakdown field strength of the silicon carbide is far greater than that of silicon, so that the gate dielectric layer can bear a higher electric field, and the degradation of insulating property and even early breakdown are more likely to occur.

Fig. 1 to 5 show a trench gate transistor structure in the related art. As shown, the trench gate transistor includes: a substrate 100; a layer of semiconductor material 110 located on the substrate 100; a gate trench 120 extending from the first surface 111 of the semiconductor material layer 110 to the inside; a gate dielectric layer 130 and a gate 140 within the gate trench 120. To protect the gate dielectric layer 130, a plurality of P pillar (P pilar) structures 157 are disposed at intervals in a direction intersecting the gate trench 120. The presence of the P-pillar structures 157 occupies the location where the channel region would otherwise be formed, with the body region 160 disposed between adjacent P-pillar structures 157. This way, not only can the gate dielectric layer 130 be prevented from being broken down under the action of a high electric field, but also the trench density can be greatly increased, thereby reducing the on-resistance of the device. However, as the channel density increases, the input capacitance C _iss of the device also increases, which increases the switching loss of the device.

Fig. 6 shows another trench gate transistor structure in the related art. As shown, to protect gate dielectric layer 130, a half-trench structure is formed. Specifically, the body region 160 is disposed only at one side of the gate trench 120, thereby forming a channel region; and a P-type shield layer 158 is disposed on the other side of the gate trench 120, the P-type shield layer 158 also being partially under the gate trench 120, thereby protecting the gate dielectric layer 130 from breakdown. During device operation, the other side of the gate trench 120 does not participate in channel conduction, but because the thickness of the gate dielectric layer 130 is thinner on the other side, i.e., the side adjacent to the P-type shielding layer 158, a larger gate-source capacitance C _gs is easily formed, thereby forming a larger input capacitance C _iss.

Based on this, an embodiment of the present application provides a trench gate transistor, including: a layer of semiconductor material comprising a first surface and a second surface opposite each other; a gate trench extending from the first surface of the semiconductor material layer to an interior of the semiconductor material layer, the gate trench including sidewalls and a bottom wall; the gate dielectric layer is positioned in the gate groove and comprises a first dielectric part and a second dielectric part which cover the side wall of the gate groove; the first electric field shielding structure is positioned outside the grid groove and is adjacent to the first medium part; the body region is positioned outside the gate trench and adjacent to the second dielectric part, and the part, close to the gate trench, of the body region is used for forming a channel region; wherein the thickness of the first medium part is greater than the thickness of the second medium part.

As can be appreciated, the capacitance c=εs/d, where ε is the dielectric constant of the medium between the plates, S is the plate area, and d is the distance between the plates; for the parasitic capacitance of the trench gate transistor, the gate dielectric layer is the inter-plate dielectric, and the capacitance C can be obviously reduced by increasing the thickness of the gate dielectric layer (i.e. increasing d). The thickness of the gate dielectric layer also determines the distance between the gate and the channel region, and if the overall thickness of the gate dielectric layer is increased, the conduction performance of the device is definitely affected. The embodiment of the application aims at the trench gate transistor provided with the electric field shielding structure, wherein the electric field shielding structure is adjacent to a part of the gate dielectric layer, and the part cannot form a channel region (namely a non-channel region), so that the reduction of the input capacitance is realized by increasing the thickness of the gate dielectric layer adjacent to the non-channel region, the switching loss of a device is avoided, and the conduction performance of the device is not influenced.

In the embodiment of the application, the trench gate transistor is specifically, for example, a SiC MOSFET. The 4H-SiC has large forbidden bandwidth, high critical breakdown electric field and high saturated electron drift speed, and is an ideal material for manufacturing high-voltage MOSFET. Of course, the present application does not exclude the case that the trench gate transistor is another possible type of transistor.

For ease of understanding, a trench gate transistor according to an embodiment of the present application is described in further detail below with reference to fig. 7 to 11.

As shown, the trench gate transistor includes:

the layer of semiconductor material 110 includes a first surface 111 and a second surface 112 opposite each other. The first surface 111 is specifically an operation surface during a process of forming the gate trench 120, and may be referred to as an upper surface.

In the case where the flatness of the first surface 111 and the second surface 112 is ignored, a direction perpendicular to the first surface 111 and the second surface 112 of the semiconductor material layer 110 is defined as a thickness direction of the semiconductor material layer 110, or a thickness direction of the device.

The trench gate transistor may also include a substrate 100. The layer of semiconductor material 110 may be an epitaxial layer grown on the substrate 100. The substrate 100 may be the base of a transistor, which is the carrier to which subsequent material layers are added. The thickness direction of the device is also the stacking direction of the layers of materials deposited on the substrate 100 and thus may also be referred to as the height direction or depth direction of the device, which is shown in the figure as the "second direction". Defining two first and third directions intersecting each other on a plane in which the first surface 111 of the semiconductor material layer 110 is located; the first direction and the third direction are, for example, two directions perpendicular to each other.

In some embodiments, the layer of semiconductor material 110 comprises an epitaxial layer of silicon carbide.

The semiconductor material layer 110 has a first conductivity type. The first conductivity type may be N-type or P-type.

In some embodiments, the first conductivity type is N-type. The semiconductor material layer 110 is an N-type semiconductor material layer. The substrate 100 is an N-type semiconductor substrate.

A gate trench 120 extending from the first surface 111 of the semiconductor material layer 110 to the interior of the semiconductor material layer 110, the gate trench 120 comprising sidewalls 121 and a bottom wall 122.

Illustratively, the gate trench 120 may be formed by a photolithographic process. Specifically, a mask material is deposited on the semiconductor material layer 110, and then a predetermined formation position of the gate trench 120 is defined in the mask material through a photolithography process, thereby forming a patterned mask layer. Next, the semiconductor material layer 110 is etched using the patterned mask layer as a mask until the gate trench 120 is formed. This process is well known to those skilled in the art and will not be described in detail here.

A gate dielectric layer 130 is located within the gate trench 120 and includes a first dielectric portion 131 and a second dielectric portion 132 that cover sidewalls 121 of the gate trench 120.

In an actual device, the gate dielectric layer 130 may cover the sidewalls 121 and the bottom wall 122 of the gate trench 120. The gate dielectric layer 130 may be an oxide layer and thus may also be referred to as a gate oxide layer; specifically, for example, a silicon dioxide layer. In the actual preparation process, the gate oxide layer can be formed through an oxidation process, a deposition process, or a process of oxidizing and then depositing.

The first electric field shielding structure 150 is located outside the gate trench 120 and abuts the first dielectric portion 131. The first electric field shielding structure 150 may play a role of attracting an electric field to some extent and alleviating a problem of electric field concentration at the bottom of the gate dielectric layer 130.

The first electric field shielding structure 150 may be formed by a doping process, specifically, an ion implantation process, for example. Illustratively, the first electric field shielding structure 150 may have a second conductivity type, which is different from the first conductivity type. In other words, the first electric field shielding structure 150 is different from the semiconductor material layer 110 in conductivity type; in this way, it may act to attract or deplete a portion of the electric field. In practical applications, the first electric field shielding structure 150 may be P-type. The first electric field shielding structure 150 may also be referred to as a P link structure or a P pilar structure.

As shown in fig. 7, 9 and 11, the first electric field shielding structure 150 may surround both sides and a bottom wall of the gate trench 120. On the plane of the first surface 111 of the semiconductor material layer 110, the projection of the first electric field shielding structure 150 intersects the projection of the gate trench 120; further, the two may intersect vertically.

The number of the first electric field shielding structures 150 may be plural with respect to one gate trench 120; thus, the first electric field shielding structures 150 are all electric field shielding structures corresponding to the gate trench 120. The adjacent first electric field shielding structures 150 may be parallel or non-parallel. Fig. 8 shows a case where two adjacent first electric field shielding structures 150 are parallel; and further, each of the first electric field shielding structures 150 is perpendicular to the gate trench 120, or is perpendicular to the extending direction of the sidewall 121. The extending direction refers to the extending direction of the sidewall 121 on the plane of the first surface 111 of the semiconductor material layer 110.

In other embodiments, two adjacent first electric field shielding structures 150 may be parallel to but not perpendicular to the gate trench 120. The embodiment of the present application is not particularly limited thereto.

Along the extending direction of the sidewall 121, the gate dielectric layer 130 may include at least two first dielectric portions 131 arranged at intervals, and a second dielectric portion 132 located between two adjacent first dielectric portions 131. Referring to fig. 8, as an alternative embodiment, the projection of the gate trench 120 on the first surface 111 of the semiconductor material layer 110 is rectangular, where the width of the rectangle is the line width of the gate trench 120, and the length of the rectangle is the extension length of the gate trench 120. Further, the sidewalls 121 of the gate trench 120 extend along a straight line, and the sidewalls 121 are specifically shown in fig. 8 to extend along a third direction.

Of course, the present application is not limited thereto, and the planar shape of the gate trench 120 (i.e., the shape of the projection on the first surface 111 of the semiconductor material layer 110) may also take other shapes, such as triangle, square, pentagon, hexagon, circle, etc.; as such, the sidewall 121 may not extend along a straight line, and thus the extending direction of the sidewall 121 may not refer to a fixed direction, but may be continuously changed as the sidewall 121 extends. Taking fig. 13 as an example, the planar shape of the gate trench 120 is a hexagon, and the extending direction of the sidewall 121 is the direction along the side of the hexagon. Thus, the first dielectric portion 131 and the second dielectric portion 132 are shown in the figure.

As an alternative embodiment, the first dielectric portions 131 and the second dielectric portions 132 may be alternately arranged along the extension direction of the sidewalls 121 of the gate trench 120. Specifically, along the extending direction, the gate dielectric layer 130 includes a first dielectric portion 131, a second dielectric portion 132, a first dielectric portion 131, and a second dielectric portion 132 … …, where the number of the first dielectric portion 131 and the second dielectric portion 132 is not necessarily equal, for example, one is 1 more than the other.

In the case where the planar shape of the gate trench 120 is a symmetrical shape, the sidewall 121 may include two sides opposite to each other with respect to the symmetry axis, and the distribution of the first dielectric portion 131 and the second dielectric portion 132 at the two sides of the sidewall 121 may be the same.

As shown in fig. 13, two adjacent first electric field shielding structures 150 are not parallel; and further, in particular, the case of intersections. For any two first electric field shielding structures 150 to intersect, the location of the intersection may be located below the gate trench 120; of course, the present application does not exclude the case where it intersects at other locations. At the side wall of the gate trench 120, two adjacent first electric field shielding structures 150 are spaced apart.

A body region 160 located outside the gate trench 120 and adjacent to the second dielectric portion 132, and a portion of the body region 160 adjacent to the gate trench 120 is used to form a channel region 161 (see fig. 8 and 10). As can be appreciated, in the case where the first dielectric portions 131 and the second dielectric portions 132 are alternately arranged, the first electric field shielding structure 150 and the body region 160 are alternately arranged along the extension direction of the sidewall 121, thereby better achieving the protection effect of the gate dielectric layer 130.

The body region 160 may be formed by a doping process, specifically, for example, an ion implantation process. Illustratively, the body region 160 may have a second conductivity type that is different from the first conductivity type. In other words, the body region 160 is not of the same conductivity type as the semiconductor material layer 110. In practical applications, body region 160 may be P-type; body region 160 may also be referred to as a P body region.

Specifically, the ion doping concentration of the body region 160 is smaller than that of the first electric field shielding structure 150.

The second dielectric portion 132 adjoins the body region 160, and during device operation the second dielectric portion 132 adjoins the channel region 161. The second dielectric portion 132 is located between the channel region 161 and the gate 140 of the device. The first dielectric portion 131 is adjacent to the first electric field shielding structure 150 such that the first dielectric portion 131 is adjacent to the non-channel region. Wherein, the thickness of the first medium part 131 is greater than the thickness of the second medium part 132. Therefore, by increasing the thickness of the gate dielectric layer adjacent to the non-channel region, the reduction of the input capacitance is realized, and the increase of the switching loss of the device is avoided; the gate dielectric layer adjacent to the non-channel region may be slightly increased, not increased, or even decreased according to the requirements of the conduction performance of the device, which is not particularly limited in the present application.

Referring specifically to fig. 24, where the dashed line corresponds to an embodiment of the present application, simulation is performed using the structures shown in fig. 7 to 11; the solid line corresponds to the related art, and the simulation is specifically performed using the structures shown in fig. 1 to 5. As shown in fig. 24, the input capacitance C _iss of the structure in the embodiment of the present application is reduced to some extent compared to the input capacitance C _iss of the structure in the related art.

It should be understood that the thickness of the first dielectric portion 131 and the thickness of the second dielectric portion 132 are defined by the formation direction (specifically, for example, the deposition direction) of the gate dielectric layer 130. For example, the gate dielectric layer 130 is formed by a deposition process, and during the deposition process, the gate dielectric layer 130 is gradually thickened, and the dimension in the thickening direction is the thickness. Referring to fig. 9, a gate dielectric layer 130 (referring to a first dielectric portion 131 shown in the drawing) covers sidewalls 121 and a bottom wall 122 of a gate trench 120, and a dimension of the gate dielectric layer 130 in a direction perpendicular to the sidewalls 121 is a thickness thereof for a portion of the gate dielectric layer 130 covering the sidewalls 121 of the gate trench 120; and the gate dielectric layer 130 covers the bottom wall 122 of the gate trench 120, and has a thickness in a direction perpendicular to the bottom wall 122.

As an alternative embodiment, the thickness of the first dielectric portion 131 is greater than the thickness of the second dielectric portion 132 and less than or equal to 1/4 of the line width of the gate trench 120. It should be understood that two sidewalls of the gate trench 120 opposite to each other are typically covered by the first dielectric portion 131, and the sum of thicknesses of the first dielectric portion 131 covering the two sidewalls opposite to each other is 1/2 or less of the line width of the gate trench 120. Thus, the line width of the grid electrode 140 is ensured, and the influence on the conduction performance of the device is avoided.

In addition, the thickness of the second dielectric portion 132 is, for example, between 35nm and 1000nm, which is appropriately set according to actual device conditions. It can be appreciated that when the thickness of the second dielectric portion 132 is 35nm, the thickness of the first dielectric portion 131 is greater than 35nm; when the thickness of the second dielectric portion 132 is 1000nm, the thickness of the first dielectric portion 131 is greater than 1000nm.

The trench-gate transistor further includes a gate 140 positioned within the gate trench 120 and isolated from the sidewalls 121 and bottom wall 122 of the gate trench 120 by a gate dielectric layer 130.

Illustratively, the material of gate 140 includes polysilicon, for example.

As an alternative embodiment, gate 140 includes a first gate portion 141 and a second gate portion 142, first gate portion 141 adjoining first dielectric portion 131 from within gate trench 120, second gate portion 142 adjoining second dielectric portion 132 from within gate trench 120; wherein, the line width of the first gate portion 141 is smaller than that of the second gate portion 142. Thus, the process difficulty is reduced, and the consumption of gate materials is reduced.

Further, the line width of the gate trench 120 does not vary with the line widths of the first and second gate portions 141 and 142. The sum of the line width of the first gate portion 141 and the thickness of the first dielectric portion 131 may be equal to the sum of the line width of the second gate portion 142 and the thickness of the second dielectric portion 132.

The source contact region 200 may be included in a surface layer of the body region 160. The source contact region 200 extends from the first surface 111 of the semiconductor material layer 110 to the interior of the semiconductor material layer 110.

The source contact region 200 has a first conductivity type. The source contact region 200 is of the same conductivity type as the semiconductor material layer 110 and of the opposite conductivity type as the body region 160. The source contact region 200 has a higher ion doping concentration than the semiconductor material layer 110. Illustratively, the source contact region 200 is an n+ doped region; the source contact region 200 is formed by, for example, subjecting the surface layer of the body region 160 to an inversion heavy doping.

Referring to fig. 8 and 10, during operation of the device, a channel region 161 is formed in a portion of the body region 160 adjacent to the gate trench 120. It should be noted that, in fig. 8, for clarity of illustration, the positions of the channel region 161 and the first and second dielectric portions 131 and 132 are schematically marked only on the right side of the gate trench 120 in the drawing, but actually, the channel region 161 and the first and second dielectric portions 131 and 132 are also symmetrically included on the left side of the gate trench 120 in the drawing.

A drift region 113 is located below the channel region 161. In an actual device, the remaining portion of the semiconductor material layer 110 is used to form the drift region of the device.

The first electric field shielding structure contact region 190 may be included in a surface layer of the first electric field shielding structure 150. The first electric field shielding structure contact region 190 extends from the first surface 111 of the semiconductor material layer 110 to the inside of the semiconductor material layer 110; the first electric field shielding structure contact region 190 is specifically located above portions of the first electric field shielding structure 150 that are distributed on both sides of the gate trench 120.

The first electric field shielding structure contact region 190 is electrically connected to both the first electric field shielding structure 150 and the source contact region 200, and the first electric field shielding structure 150 is electrically connected to the source contact region 200 through the first electric field shielding structure contact region 190, thereby being commonly connected to the ground potential.

The first electric field shielding structure contact region 190 has a second conductivity type, which is different from the first conductivity type. In other words, the first electric field shielding structure contact region 190 is opposite to the conductivity type of the semiconductor material layer 110, and is the same as the conductivity type of the first electric field shielding structure 150, but has a higher ion doping concentration than the first electric field shielding structure 150. Illustratively, the first electric field shield structure contact region 190 is a p+ doped region; and is formed by heavily doping the surface layer of the first electric field shielding structure 150.

Next, referring to fig. 11, in an embodiment in which the first electric field shielding structure 150 further extends below the gate trench 120, the gate dielectric layer 130 may further include a third dielectric portion 133 and a fourth dielectric portion 134 covering the bottom wall 122 of the gate trench 120; in a direction perpendicular to the first surface 111 of the semiconductor material layer 110 (as in the second direction in the drawing), the projection of the third dielectric portion 133 falls within the range of the projection of the first electric field shielding structure 150, and the projection of the fourth dielectric portion 134 does not coincide with the projection of the first electric field shielding structure 150; wherein the thickness of the third medium portion 133 is greater than the thickness of the fourth medium portion 134.

It will be appreciated that the gate 140 is omitted from fig. 11 for clarity in illustrating the third dielectric portion 133 and the fourth dielectric portion 134.

It should also be appreciated that by the thickness of the third dielectric portion 133 being greater than the thickness of the fourth dielectric portion 134, the gate drain capacitance C _gd is reduced, and the input capacitance C _iss can be further reduced in view of the input capacitance C _iss=C_gs+C_gd.

As an alternative embodiment, the thickness of the third dielectric portion 133 is greater than the thickness of the fourth dielectric portion 134 and less than or equal to 1/2 of the depth of the gate trench 120. In this way, the filling depth of the gate 140 at the position is ensured, and the conduction performance of the device is prevented from being influenced.

The thickness of the fourth dielectric portion 134 is, for example, 35nm to 1000nm, and may be appropriately set according to actual device conditions. It can be appreciated that when the thickness of the fourth dielectric portion 134 is 35nm, the thickness of the third dielectric portion 133 is greater than 35nm; when the thickness of the fourth dielectric portion 134 is 1000nm, the thickness of the third dielectric portion 133 is greater than 1000nm.

Further, in a direction perpendicular to the first surface 111 of the semiconductor material layer 110, the projection of the third dielectric portion 133 may coincide with the projection of the first gate portion 141; further, the projection of the fourth dielectric portion 134 may coincide with the projection of the second gate portion 142.

The depth of the first gate portion 141 may be smaller than the depth of the second gate portion 142. Thus, the process difficulty is reduced, and the consumption of gate materials is reduced. It is understood that in a particular device, the depth of the first gate portion 141 and the second gate portion 142 and the thickness of the third dielectric portion 133 and the fourth dielectric portion 134 each refer to a dimension in a direction perpendicular to the first surface 111 of the semiconductor material layer 110.

Further, the depth of the gate trench 120 does not vary with the thickness of the third and fourth dielectric portions 133 and 134. The sum of the depth of the first gate portion 141 and the thickness of the third dielectric portion 133 may be equal to the sum of the depth of the second gate portion 142 and the thickness of the fourth dielectric portion 134.

Fig. 12 shows a cross-sectional structure of another trench gate transistor according to an embodiment of the present application, and for the same parts of the trench gate transistor as those of the trench gate transistors shown in fig. 7 to 11, the description thereof will not be repeated here. The trench-gate transistor differs from the trench-gate transistor shown in fig. 7 to 11 mainly in that the first electric field shielding structure 150 is arranged at a different position, and the first electric field shielding structure 150 is located at one side of the gate trench 120 in the trench-gate transistor, so that the body region 160 is located at the other side of the gate trench 120. Accordingly, the first dielectric portion 131 and the second dielectric portion 132 cover both sidewalls of the gate trench 120, respectively, which are opposite to each other.

Wherein the thickness of the first dielectric portion 131 adjacent to the first electric field shielding structure 150 is greater than the thickness of the second dielectric portion 132 adjacent to the body region 160. It can be appreciated that the trench gate transistor also achieves a reduction in input capacitance by increasing the thickness of the gate dielectric layer adjacent to the non-channel region, avoids increasing the switching loss of the device, and can be made to have no effect on the turn-on performance of the device.

Referring next to fig. 14 to 18, as shown in the drawings, as an alternative embodiment, the trench gate transistor may further include: the second electric field shielding structures 170 are located below the first electric field shielding structures 150 and extend at least partially below the channel region 161, such that a width W1 of a portion of the drift region 113 located between two adjacent second electric field shielding structures 170 is smaller than a width W2 of the channel region 161 along an extension direction of the sidewalls 121 of the gate trench 120.

As can be appreciated, the present embodiment can set the spacing between two adjacent first electric field shielding structures 150 and the spacing between two adjacent second electric field shielding structures 170, that is, the spacing between two adjacent first electric field shielding structures 150 and the spacing between two adjacent second electric field shielding structures 170 can be independently adjusted by modifying the P-pillar structure 157 in the related art to include the first electric field shielding structure 150 and the second electric field shielding structure 170 located under the first electric field shielding structure 150; specifically, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 is smaller than the width W2 of the channel region 161, so that the width W2 of the channel region 161 can be ensured, and meanwhile, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 can be set smaller, the JFET resistance in the region where the portion is located can be adjusted, the channel resistance is not affected, the saturation current of the device is greatly reduced, and the short circuit performance of the device is optimized; and the protection effect of the gate dielectric layer 130 at the bottom of the gate trench 120 is enhanced by the second electric field shielding structure 170, so that the specific on-resistance R _sp, the protection effect and the short circuit performance are both considered.

Furthermore, since W1 and W2 are widths along the extending direction in the embodiment of the present application, the adjustment of W1 and W2 does not affect the spacing between adjacent gate trenches 120, and thus does not reduce the number of gate trenches 120 arranged per unit area.

The second electric field shielding structure 170 may play a role in attracting an electric field to some extent and alleviating a problem of electric field concentration at the bottom of the gate dielectric layer 130.

The second electric field shielding structure 170 includes, for example, at least a portion having a depth equal to or greater than the depth of the gate trench bottom wall 122.

The second electric field shielding structure 170 may be formed by a doping process, specifically, for example, an ion implantation process. Illustratively, the second electric field shielding structure 170 may have a second conductivity type, which is different from the first conductivity type. In other words, the second electric field shielding structure 170 is different from the semiconductor material layer 110 in conductivity type; in this way, it may act to attract or deplete a portion of the electric field. The second electric field shielding structure 170 is the same conductive type as the first electric field shielding structure 150. In practical applications, the second electric field shielding structure 170 may be P-type.

The second electric field shielding structure 170 is formed in a different doping process than the first electric field shielding structure 150. In actual fabrication, the second electric field shielding structure 170 and the first electric field shielding structure 150 may both be selectively doped; masks are used during the formation of the second electric field shielding structure 170 and the first electric field shielding structure 150, respectively, to define the formation regions of both. The second electric field shielding structure 170 is formed using a different mask than the first electric field shielding structure 150.

As an alternative embodiment, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the first electric field shielding structure 150; thus, the second electric field shielding structure 170 functions to better protect the gate dielectric layer 130.

As an alternative embodiment, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the body region 160. Further, the ion doping concentration of the body region 160 is less than the ion doping concentration of the first electric field shielding structure 150 and less than the ion doping concentration of the second electric field shielding structure 170. Thus, the gate dielectric layer 130 is better protected while the device is effectively operated.

The projection of the first electric field shielding structure 150 onto the first surface 111 of the semiconductor material layer 110 may fall within the projection range of the second electric field shielding structure 170. The planar shape of the second electric field shielding structure 170 (i.e., the projected shape on the first surface 111 of the semiconductor material layer 110) may be the same as the planar shape of the first electric field shielding structure 150, and the boundary of the second electric field shielding structure 170 exceeds the boundary of the first electric field shielding structure 150 only in the extending direction along the sidewall 121. The second electric field shielding structure 170 protrudes from the first electric field shielding structure 150 along the extending direction of the sidewall 121. In a practical device, there is a significant interval between the boundary of the portion of the second electric field shielding structure 170 extending to the lower side of the channel region 161 and the boundary of the first electric field shielding structure 150 thereabove in the extending direction of the sidewall 121.

It should be understood that the present application does not exclude the case that the planar shape of the second electric field shielding structure 170 is different from the planar shape of the first electric field shielding structure 150. In addition, the present application does not exclude the case that the second electric field shielding structure 170 is not completely covered under the first electric field shielding structure 150.

Referring to fig. 14, 16 and 17, as an alternative embodiment, the bottom of the first electric field shielding structure 150 is further away from the first surface 111 of the semiconductor material layer 110 than the bottom of the body region 160, so that a gap D1 exists between the second electric field shielding structure 170 and the body region 160.

Further, in the extending direction, the width W1 of the portion of the drift region 113 located between the adjacent two second electric field shielding structures 170 is smaller than the width W3 of the portion located between the adjacent two first electric field shielding structures 150. It can be appreciated that W3 is substantially equal to W2, both of which are greater than W1, in the case where the boundary of the first electric field shielding structure 150 is substantially constant in the depth direction. In the case where the boundary of the first electric field shielding structures 150 varies in the depth direction, the relationship between the upper half of the first electric field shielding structures 150 and the body region 160 is not that, and the distance between the upper half of two adjacent first electric field shielding structures 150 is equal to the width W2 of the channel region 161, but the lower half of the first electric field shielding structures 150 may extend below the channel region 161, so that W3 may be smaller than W2, and in this case W3 is still larger than W1, to ensure both the specific on-resistance R _sp and the short-circuit performance.

Further, the second electric field shielding structure 170 is spaced from the body region 160 by 0.25 μm to 1.2 μm, i.e., D1 ranges from 0.25 μm to 1.2 μm. It should be noted that, in the case where D1 is less than 0.25 μm, ions doped in the second electric field shielding structure 170 may intrude into the body region 160 due to longitudinal dispersion, resulting in an increase in R _dson; in the case where D1 is greater than 1.2 μm, the difficulty in realizing the process increases.

It should be noted that the present application does not exclude the case where D1 is equal to 0. Specifically, in the semiconductor material layer 110, the bottom of the first electric field shielding structure 150 may be at a depth substantially the same as the bottom of the body region 160, such that the second electric field shielding structure 170 extends at least partially below the channel region 161, and in particular the second electric field shielding structure 170 is at least partially adjacent to the body region 160 below the channel region 161.

As an alternative embodiment, the second electric field shielding structure 170 is adjacent to the bottom of the first electric field shielding structure 150. The second electric field shielding structure 170 forms a conductive connection with the first electric field shielding structure 150 through direct contact.

Further, both the second electric field shielding structure 170 and the first electric field shielding structure 150 are connected to the ground potential. Thus, the shielding effect can be better exerted, so that the effect of weakening the electric field intensity at the bottom of the gate dielectric layer 130 can be better realized.

As an alternative embodiment, the trench-gate transistor further includes: the third electric field shielding structure 180 is located under the gate trench 120 and has an overlapping region with the first electric field shielding structure 150 and/or the second electric field shielding structure 170, and is electrically connected to the first electric field shielding structure 150 and/or the second electric field shielding structure 170 through the overlapping region.

The first electric field shielding structure 150, the second electric field shielding structure 170, and the third electric field shielding structure 180 are electric field shielding structures corresponding to the same gate trench 120.

The third electric field shielding structure 180 may be formed through a doping process, specifically, an ion implantation process, for example. Illustratively, the third electric field shielding structure 180 may have a second conductivity type, which is different from the first conductivity type. In other words, the third electric field shielding structure 180 is different from the semiconductor material layer 110 in conductivity type; in this way, it may act to attract or deplete a portion of the electric field. In practical applications, the third electric field shielding structure 180 may be P-type; the third electric field shielding structure 180 may also be referred to as a P shield structure.

The bottom of the gate dielectric layer 130 is protected by the third electric field shielding structure 180, and the formation of the channel region is not affected, so that the protection effect on the gate dielectric layer 130 can be further enhanced, and the third electric field shielding structure 180 is further arranged on the basis of the first electric field shielding structure 150, so that the effect of shielding the electric field at the bottom of the gate dielectric layer 130 and the influence on the on-resistance of the trench gate transistor are both facilitated.

Further, the third electric field shielding structure 180 is connected to the ground potential through the first electric field shielding structure 150 and/or the second electric field shielding structure 170; thus, the shielding effect can be better exerted, so that the effect of weakening the electric field intensity at the bottom of the gate dielectric layer 130 can be better realized.

Next, please refer to fig. 19 and 20. As an alternative embodiment, the width W1 of the portion of the drift region 113 between the adjacent two second electric field shielding structures 170 increases from the direction closer to the gate trench 120 to the direction farther from the gate trench 120.

In the structure shown in fig. 8 and 15, the spacing between adjacent two second electric field shielding structures 170 is substantially constant, so that W1 remains constant in a direction from near the gate trench 120 to far from the gate trench 120. It will be appreciated that the saturation current of the device of the embodiment shown in figures 19 and 20 is also reduced compared to the related art. In the case where W1 in the structures shown in fig. 8 and 15 is equal to the minimum W1 in the structures shown in fig. 19 and 20, the saturation current of the structures shown in fig. 19 and 20 may be larger than that of the structures shown in fig. 8 and 15, that is, the effect of reducing the saturation current is not as good as that of the structures shown in fig. 8 and 15; but the specific on-resistance R _sp is better than the structures shown in fig. 8 and 15. Thus, by setting W1 to increase from the direction closer to the gate trench 120 to the direction farther from the gate trench 120, the flexibility of adjusting R _sp and the short-circuit performance can be further increased.

Further, referring to fig. 19, in some embodiments, the spacing between the portions of two adjacent second electric field shielding structures 170 under the gate trench 120 is equal.

Further, referring to fig. 20, in other embodiments, the spacing between the portions of the adjacent two second electric field shielding structures 170 located under the gate trench 120 decreases in a direction toward the center of the gate trench 120. It can be appreciated that the embodiment shown in fig. 20 can obtain a larger saturation current and a smaller R _sp in the case where the minimum pitch of the adjacent two second electric-field-shielding structures 170 in the embodiment shown in fig. 20 is equal to the pitch of the portions of the adjacent two second electric-field-shielding structures 170 located below the gate trench 120 in the embodiment shown in fig. 19, as compared to the embodiment shown in fig. 19.

Next, please refer to fig. 14 and 17. As an alternative embodiment, the trench-gate transistor further includes: a current diffusion layer 230 is located in the JFET region 114 below the body region 160, the ion doping concentration of the current diffusion layer 230 being greater than the ion doping concentration of the drift region 113.

It will be appreciated that the electric field shielding structure forms a JFET with the body region 160 while protecting the bottom of the gate dielectric layer 130, and the presence of a parasitic JFET reduces the current density of the device. In this embodiment, by providing the current spreading layer 230 in the JFET region 114, the parasitic resistance of the parasitic JFET can be reduced, thereby improving the conductivity of the device.

The current diffusion layer 230 may be formed by a doping process, specifically, for example, an ion implantation process. Illustratively, the current spreading layer 230 may have a first conductivity type; in other words, the current diffusion layer 230 has the same conductivity type as the semiconductor material layer 110, but the ion doping concentration of the current diffusion layer 230 is greater than that of the semiconductor material layer 110.

Next, please refer to fig. 21 to 24. As an alternative embodiment, the trench-gate transistor further includes: an interlayer dielectric layer 210 located within the gate trench 120 and above the gate 140; the conductive layer 220 is located on the semiconductor material layer 110, and the conductive layer 220 is insulated from the gate 140 by the interlayer dielectric layer 210.

It will be appreciated that the conductive layer 220 is used for conductive connection with the source contact region 200, but needs to be insulated from the gate 140. Referring to fig. 7 to 12 and 14 to 18, if an interlayer dielectric layer 210 is disposed on the semiconductor material layer 110, in order to ensure that the interlayer dielectric layer 210 completely covers the gate electrode 140, the interlayer dielectric layer 210 is generally designed to be slightly larger than the planar size of the gate electrode 140, so that the layout space of the source conductive contact hole is limited. The cell size is difficult to further shrink, and R _sp is difficult to continue to iteratively decrease, limited by the size of the source contact hole. In this embodiment, by disposing the interlayer dielectric layer 210 in the gate trench 120, not only is the photolithography process for defining the position of the interlayer dielectric layer 210 omitted, and a self-aligned structure is realized, but also the source electrode conductive contact hole can be avoided, so that the cell size is further reduced, and the reduction of R _sp is facilitated.

The trench gate transistor may further include: a drain (not shown) is located on the side of the second surface 112 of the semiconductor material layer 110. Specifically, the drain is located on the side of the substrate 100 facing away from the epitaxial layer (semiconductor material layer 110). In an actual device, the drain electrode may specifically be a metal drain electrode.

The technical features of the embodiments of the present application may be combined arbitrarily without any conflict.

It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the individual features of the above embodiments can also be combined arbitrarily to form further embodiments of the application which may not be explicitly described. Therefore, the above examples merely represent several embodiments of the present application and do not limit the scope of protection of the patent of the present application.

Claims

1. A trench-gate transistor, comprising:

2. The trench-gate transistor of claim 1, wherein the first dielectric portions and the second dielectric portions are alternately arranged along an extension direction of a sidewall of the gate trench, the extension direction being a direction in which the sidewall extends on a plane in which the first surface of the semiconductor material layer lies.

3. The trench-gate transistor of claim 1 or 2, wherein the first electric field shielding structure further extends below the gate trench; the gate dielectric layer comprises a third dielectric part and a fourth dielectric part which cover the bottom wall of the gate trench; in a direction perpendicular to the first surface of the semiconductor material layer, the projection of the third dielectric portion falls within the range of the projection of the first electric field shielding structure, and the projection of the fourth dielectric portion is not coincident with the projection of the first electric field shielding structure;

4. The trench-gate transistor of claim 1, further comprising: the grid electrode is positioned in the grid electrode groove and is isolated from the side wall and the bottom wall of the grid electrode groove through the grid dielectric layer; the gate includes a first gate portion adjoining the first dielectric portion from within the gate trench and a second gate portion adjoining the second dielectric portion from within the gate trench;

5. The trench-gate transistor of claim 1, further comprising:

a drift region located below the channel region;

6. The trench-gate transistor of claim 5, wherein a bottom of the first electric field shielding structure is further from the first surface of the semiconductor material layer than a bottom of the body region such that a gap exists between the second electric field shielding structure and the body region;

along the extending direction, the width of a part of the drift region between two adjacent second electric field shielding structures is smaller than the width of a part between two adjacent first electric field shielding structures; and/or the interval between the second electric field shielding structure and the body is 0.25-1.2 μm.

7. The trench-gate transistor of claim 5, wherein the second electric field shielding structure has a greater ion doping concentration than the first electric field shielding structure.

8. The trench-gate transistor of claim 5, wherein a width of a portion of the drift region between adjacent two of the second electric field shielding structures increases from a direction closer to the gate trench to a direction farther from the gate trench.

9. The trench-gate transistor of claim 5, wherein the second electric field shielding structure is adjacent to a bottom of the first electric field shielding structure;

The second electric field shielding structure and the first electric field shielding structure are both connected to a ground potential.

10. The trench-gate transistor of claim 1 or 5, further comprising: