CN1183594C - 带保护电路的半导体器件 - Google Patents

带保护电路的半导体器件 Download PDF

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CN1183594C
CN1183594C CNB981193137A CN98119313A CN1183594C CN 1183594 C CN1183594 C CN 1183594C CN B981193137 A CNB981193137 A CN B981193137A CN 98119313 A CN98119313 A CN 98119313A CN 1183594 C CN1183594 C CN 1183594C
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terminals
lead
circuit
internal circuit
semiconductor device
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CN1211823A (zh
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藤井威男
成田薰
堀口洋子
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Ps4 Russport Co ltd
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NEC Electronics Corp
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Abstract

一种带有保护电路的引线在芯片上(LOC)的或是芯片在引线上(COL)的半导体器件。将非接线端制作得比接线端短，以降低非接线端的电感，或为非接线端与接线端的保护电路取得互不相同的保护能力。将非接线端保护电路的时间常数制作得比接线端保护电路的长。还使接线端的箝位能力比邻近接线端的另一接线端的强。

Description

带保护电路的半导体器件
技术领域
本发明涉及一种带有既不确定为输入/输出又不确定为电压源的非接线端的半导体集成电路。
背景技术
在一般情况下，引线在芯片上(LOC)的半导体器件或芯片在引线上(COL)的半导体器件均提供有与输入电路、输出电路和电压源电路相连接的确定的接线端以及前述的非接线端。这种非接线端特别在门阵列的情况下不可避免地要供自由选择而设置。
此外，LOC或COL的半导体器件均支撑在包含有键连导线的接线端与非接线端的引线架上。因此，接线端与非接线端均伸展至支撑半导体芯片的位置处。
因而，在使用上述引线架的半导体器件封装中非接线端是与接线端相邻近的，其中的非接线端经绝缘膜与在半导体芯片上面或下面伸展的引线相连，它与内部电路没有电连接，而接线端通过与引线键连的金属线与内部电路电连接。
若因静电而在非接线端上加一异常的高电压，则半导体芯片中的绝缘膜就有可能因经引线的放电而遭到静电击穿。
在日本专利61-180470(A)(1986)(参考文献1)中公开了一种防止非接线端中静电击穿的半导体集成电路，其中有一冲击电压放电电路与连接非接线端的引线相连。
在日本专利2-119171(A)(1990)(参考文献2)中还公开了一种防止非接线端中静电击穿的半导体集成电路，其中有一包含一个二极管的保护装置与连线图形连接。
此外，在日本专利6-120426(A)(1994)(参考文献3)中公开了一种带有保护二极管电路的母片半导体集成电路，当在与非接线端邻近的接线端上加一高电压时，这一保护二极管电路能够防止引线架和键连线之间的互感引起高压所造成的非接线端中的静电击穿。
正好相反，在日本专利63-3463(B2)(1988)(参考文献4)中公开了一种不能在焊线中支撑半导体芯片的引线架，其中非接线端引线的边缘与芯片相距得比接线端引线的远。这样的引线架由于边缘部位之间的间距宽，它能提供一些使引线架与半导体芯片定位的余量。
如上所述，在参考文献1、2和3中公开了为避免经静电放电造成非接线端静电击穿的与保护装置电连接的非接线端。然而，尽管防止了非接线端的击穿，但对邻近非接线端的接线端的相关作用未作任何考虑。
此外，尽管参考文献4公开了一种在焊线时引线不支撑芯片而且引线边缘不与芯片相连的引线架，但它并未指出在芯片上连接引线边缘的LOC或COL的半导体器件情况下会出现的任何问题。
按照本发明发明人的实验证实，大体上由于在LOC或COL半导体器件中非接线端引线和接线端引线的电感引起的互感，在与提供有高静电电压的非接线端相邻近的接线端上引发一些电压。由于非接线端较长，由非接线端产生的电感再也无法忽略了。
另外，发现在加于非接线端上的静电电压升高时在接线端上感生的电压很高，而后迅速衰减，这一现象不仅在非接线端中造成击穿，而且还使与接线端相连的内部电路中例如MOSFET的栅绝缘膜击穿。
在接线端中感生的电动力表现得与非接线端上所加的静电电压不同。因而，对于非接线端与接线端需有不同的保护电路。此外，还发现加在非接线端上的静电电压不仅影响邻近的接线端，而且还影响位于接线端对面的其它端。
发明内容
因而，本发明的一项目的是要提供一种半导体器件，特别是LOC或COL半导体器件，它的非接线端得到免受静电击穿的保护，而且，与接线端相连的内部电路也受到保护避免由在非接线端与邻近的接线端之间出现互感而造成的静电击穿。
本发明的另一个目的是要提供一种半导体器件，它能通过控制非接线端上所加静电电压上升时的电压上升抑制互感效应。
本发明的又一项目的是要提供一种半导体器件，它通过减少非接线端与接线端所引起的互感抑制对接线端的影响。
本发明还有的一项目的是要提供一种半导体器件，它能通过提高与非接线端相邻的接线端的保护电路的箝位能力抑制非接线端上所加静电电压产生的影响。
本发明还有的又一项目的是要提供一种半导体器件，它能抑制与一非接线端邻近的多个接线端上所受的影响。
按照本发明，所提供的引线在芯片上的半导体器件，包括：形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，其中所述非接线端设置得邻近所述接线端，并且所述非接线端的引线比所述接线端的引线短；并且所述非接线端的所述引线不到达所述半导体芯片。
按照本发明，所提供的引线在芯片上的半导体器件，包括：形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，其中所述非接线端设置得邻近所述接线端，并且其中用作所述非接线端的材料与用作所述接线端的材料不同，从而所述非接线端与所述接线端之间的互感得到降低。
按照本发明，所提供的引线在芯片上的半导体器件，包括：形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，其中所述非接线端设置得邻近所述接线端，并且其中所述非接线端与第一保护电路相连，所述接线端与第二保护电路相连，并且通过所述第二保护电路与内部电路相连；所述第一保护电路包括用于抑止电压上升的第一电阻，所述第二保护电路包括用于抑止电压上升的第二电阻，并且所述第一电阻的电阻值大于所述第二电阻的电阻值。
按照本发明，所提供的引线在芯片上的半导体器件，包括：形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，其中所述非接线端设置得邻近所述接线端，并且其中所述非接线端与第一保护电路相连，所述接线端与第二保护电路相连，并且通过所述第二保护电路与内部电路相连；在所述非接线端与地之间连接第一电容器，在所述接线端与地之间连接第二电容器，并且第一电容器的电容值与第二电容器的电容值不同。
按照以上所述的本发明，在有非接线端与接线端的LOC半导体器件中抑制了由非接线端感生的电动力对内部电路的作用。
附图说明
图1为本发明半导体器件的非接线端的配置平面图。
图2为非接线端的不同配置的平面图。
图3为本发明另一项实施例中的半导体器件的方框图。
图4为本发明又一项实施例中的半导体器件的方框图。
图5A为本发明还有一项实施例中的半导体器件的电路图。
图5B为图5A中所示箝位电路的电路图。
图6为本发明还有一项实施例中的有一级联箝位电路的半导体器件的方框图。
具体实施方式
参照附图，对本发明的一项最佳实施例进行说明。
如图1中所示本发明一项实施例的LOC半导体器件包括半导体芯片10，以及半导体芯片10上的多个焊点(绘示了它们中的22个焊点)11，多个引线端或引线12(绘示了它们中的22条引线)。排列在半导体芯片10上的焊点11当中的四个焊点11a是备选的焊点，它们不与任何引线12电连接，而在多条引线12当中的四条引线12a不与任何焊点11相连。其余的十八条引线均为接线端12b。
如图1中所示，非接线端12a与任何备选焊点11a无电连接，而接线端12b则与焊点11电连接。非接线端(引线)12a和接线端12b与半导体芯片10一起密封在一树脂封装中。
如图1中所示，非接线端12a与其它的接线端12b相比起来极短。于是，由非接线端12a产生的电感小于由其它接线端12b产生的电感。由于即使有高的静电电压加于非接线端12a时，在接线端12b上感生的电动力实际上也是可以忽略不计的，因而即若在非接线端12a上加有任意的高静电电压，与接线端12b相连的内部电路(图1中未示出)也不致遭受击穿。
图2中所示非接线端12b的不同配置是与图1中所示的不相同的半导体器件。为了满足使用者的各种连接需求，图2中最低处的两个接线端12b有伸向备选焊点11a附近的分支部分。
通过大量改变图1和图2中非接线端12a和接线端12b的电感能够避免非接线端12a上所加高电压对其它引线端的作用。
图3中所示本发明的另一项实施例中的半导体器件包括非接线端12a和接线端12b，它们两者的边缘伸展并焊接在一块半导体芯片上。于是，非接线端12a和接线端12b分别有图3中所示的电感L1和L2。此外，非接线端12a与第一保护电路16相连，而接线端12b则经第二保护电路17与内部电路相连。
第一保护电路16包括电容161、电阻162、以及作为箝位元件的二极管163。而第二保护电路17则包括电阻174，第一箝位电路172和第二箝位电路173，每一箝位电路分别与电阻174的一端相连。第一箝位电路172和第二箝位电路173通常由二极管、双极器件、或MOS晶体管组成。
电容器171代表一寄生电容。
在这里，要使二极管163的箝位能力低于箝位电路172和173的箝位能力，以降低由非接线端12a感生的作用于接线端12b的电动力。此外，电阻162的阻值要大于电阻174的阻值，以降低流入非接线端12a的电流的时间导数。
图4中所示本发明又一项实施例中的半导体器件包括非接线端12a以及接线端12b和12c。每一接线端12b和12c各与一内部电路14相连。同样在此情况下，非接线端12a以及接线端12b和12c具有各自的特定电感。
最好使电容器C3的电容值大于电容器C1而小于电容器C2。在这里，电容器C1、C2和C3代表寄生电容。
在图4所示的半导体器件中，使电容器C2的充电与放电比电容器C3慢。因而，就使得由非接线端12a感生的对接线端12b和12c所起的作用减小。
为此，就要使电容器C2的电容值不同于电容器C3，使由非接线端12a感生的作用于接线端12b和12c的电动力减弱。
图5A中所示本发明还有一项实施例中的半导体器件包括非接线端12a以及接线端12b和12c。按照等效电路的观点接线端12a的末端与电感L1和电容C1相连，而接线端12b则经电感L2与箝位电路20相连，此箝位电路20的箝位能力超过与接线端邻近的其它引线端相连的箝位电路。在该实施例中，通过提高接线端12b对静电放电的抵抗压降低由非接线端12a感生的电动力的作用。
图5A中所示的箝位电路20包括横向的双极型晶体管201、分别与晶体管201的发射极和集电极相连的电阻202和203以及与电阻203相连的电阻204。在这里，晶体管201的箝位能力取决于它的通道长度和宽度。
在箝位电路20中，通过使晶体管201的通道长度缩短以及使通道宽度加宽可以提高箝位能力。这样的一种通道长度与宽度的调节，使得即使在非接线端12a上加有400伏左右的静电电压时也有可能抑制住由非接线端12a感生的效应。
如图5B中所示，第二箝位电路20b和第三箝位电路20c分别包括第二横向双极晶体管201b和第三横向双极晶体管201c，第二横向双极晶体管201b的通道宽度大于第三横向双极晶体管201c。
与其类似，可用MOS晶体管取代上述的横向双极晶体管。
如图6中所示的级联成的多个箝位电路20可用于进一步提高二极管的箝位能力。
图6中所示的箝位电路20包括有在一块半导体基片上分别由杂质扩散区所形成的多个二极管。二极管的箝位能力取决于它的PN结面积并通过加大面积而得到提高。
可以将降低互感的材料用于非接线端12a和接线端12b。
尽管本发明已就其最好模式的实施例进行了表达和说明，但专业技术人员们应能理解到在不超脱本发明的精神和范围的情况下可以在形式和具体内容上对它进行前述以及各式各样其它的改变、省略和补充。

Claims (4)

1.一种引线在芯片上的半导体器件，包括：
形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，
其中所述非接线端设置得邻近所述接线端，并且
所述非接线端的引线比所述接线端的引线短；并且
所述非接线端的所述引线不到达所述半导体芯片。
2.一种引线在芯片上的半导体器件，包括：
形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，
其中所述非接线端设置得邻近所述接线端，并且
其中用作所述非接线端的材料与用作所述接线端的材料不同，从而所述非接线端与所述接线端之间的互感得到降低。
3.一种引线在芯片上的半导体器件，包括：
形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，
其中所述非接线端设置得邻近所述接线端，并且
其中所述非接线端与第一保护电路相连，所述接线端与第二保护电路相连，并且通过所述第二保护电路与内部电路相连；
所述第一保护电路包括用于抑止电压上升的第一电阻，所述第二保护电路包括用于抑止电压上升的第二电阻，并且所述第一电阻的电阻值大于所述第二电阻的电阻值。
4.一种引线在芯片上的半导体器件，包括：
形成在半导体芯片中的内部电路，与所述内部电路不相连的非接线端，和与所述内部电路相连的接线端，
其中所述非接线端设置得邻近所述接线端，并且
其中所述非接线端与第一保护电路相连，所述接线端与第二保护电路相连，并且通过所述第二保护电路与内部电路相连；
在所述非接线端与地之间连接第一电容器，在所述接线端与地之间连接第二电容器，并且第一电容器的电容值与第二电容器的电容值不同。
CNB981193137A 1997-09-12 1998-09-11 带保护电路的半导体器件 Expired - Fee Related CN1183594C (zh)

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