CN118284964A - 采用具有双面嵌入式迹线基板（ets）的封装基板的集成电路（ic）封装件以及相关制造方法 - Google Patents

采用具有双面嵌入式迹线基板（ets）的封装基板的集成电路（ic）封装件以及相关制造方法 Download PDF

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Publication number
CN118284964A
CN118284964A CN202280074053.0A CN202280074053A CN118284964A CN 118284964 A CN118284964 A CN 118284964A CN 202280074053 A CN202280074053 A CN 202280074053A CN 118284964 A CN118284964 A CN 118284964A
Authority
CN
China
Prior art keywords
metal
layer
ets
package
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202280074053.0A
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English (en)
Chinese (zh)
Inventor
卫洪博
J·R·V·鲍特
M·Y·金
K·康
A·帕蒂尔
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN118284964A publication Critical patent/CN118284964A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
CN202280074053.0A 2021-11-22 2022-10-28 采用具有双面嵌入式迹线基板（ets）的封装基板的集成电路（ic）封装件以及相关制造方法 Pending CN118284964A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/456,068 US11791320B2 (en) 2021-11-22 2021-11-22 Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods
US17/456,068 2021-11-22
PCT/US2022/078880 WO2023091851A1 (en) 2021-11-22 2022-10-28 Integrated circuit (ic) packages employing a package substrate with a double side embedded trace substrate (ets), and related fabrication methods

Publications (1)

Publication Number Publication Date
CN118284964A true CN118284964A (zh) 2024-07-02

Family

ID=84387925

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202280074053.0A Pending CN118284964A (zh) 2021-11-22 2022-10-28 采用具有双面嵌入式迹线基板（ets）的封装基板的集成电路（ic）封装件以及相关制造方法

Country Status (7)

Country Link
US (1) US11791320B2 (https=)
EP (1) EP4437586A1 (https=)
JP (1) JP2024541421A (https=)
KR (1) KR20240101796A (https=)
CN (1) CN118284964A (https=)
TW (1) TW202329347A (https=)
WO (1) WO2023091851A1 (https=)

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US12362269B2 (en) 2021-10-18 2025-07-15 Qualcomm Incorporated Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods
US11791320B2 (en) * 2021-11-22 2023-10-17 Qualcomm Incorporated Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods
US12469808B2 (en) * 2022-08-21 2025-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US12500197B2 (en) 2022-12-23 2025-12-16 Deca Technologies Usa, Inc. Encapsulant-defined land grid array (LGA) package and method for making the same
US20250062235A1 (en) * 2023-08-16 2025-02-20 Qualcomm Incorporated Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (ic) packages and fabrication methods
US12593709B2 (en) * 2023-08-17 2026-03-31 Qualcomm Incorporated Substrate(s) for an integrated circuit (IC) package employing a core layer and an adjacent insulation layer(s) with an embedded metal structure(s) positioned from the core layer
US12424450B2 (en) 2023-11-22 2025-09-23 Deca Technologies Usa, Inc. Embedded component interposer or substrate comprising displacement compensation traces (DCTs) and method of making the same
US12500198B2 (en) 2024-03-01 2025-12-16 Deca Technologies Usa, Inc. Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same
US12616038B2 (en) 2024-07-03 2026-04-28 Deca Technologies Usa, Inc. Interconnect substrate and method of making

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US5504992A (en) 1991-11-29 1996-04-09 Hitachi Chemical Company, Ltd. Fabrication process of wiring board
DE19645854A1 (de) 1996-11-07 1998-05-14 Hewlett Packard Co Verfahren zur Herstellung von Leiterplatten
US7205483B2 (en) 2004-03-19 2007-04-17 Matsushita Electric Industrial Co., Ltd. Flexible substrate having interlaminar junctions, and process for producing the same
KR100905566B1 (ko) 2007-04-30 2009-07-02 삼성전기주식회사 회로 전사용 캐리어 부재, 이를 이용한 코어리스인쇄회로기판, 및 이들의 제조방법
TWI349974B (en) 2007-07-06 2011-10-01 Unimicron Technology Corp Structure with embedded circuit
KR101654820B1 (ko) 2008-07-09 2016-09-06 인벤사스 코포레이션 감소된 도전체 공간을 가진 마이크로전자 상호접속 소자, 및 그것을 형성하는 방법
US8288202B2 (en) 2010-11-22 2012-10-16 STATS ChiPAC, Ltd. Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die
US9508681B2 (en) * 2014-12-22 2016-11-29 Google Inc. Stacked semiconductor chip RGBZ sensor
US10085342B2 (en) * 2016-12-13 2018-09-25 Intel Corporation Microelectronic device having an air core inductor
KR102321438B1 (ko) 2017-07-28 2021-11-04 엘지이노텍 주식회사 인쇄회로기판
EP4181196A3 (en) * 2017-12-29 2023-09-13 INTEL Corporation Microelectronic assemblies with communication networks
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US11270991B1 (en) * 2020-09-02 2022-03-08 Qualcomm Incorporated Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods
US11552055B2 (en) * 2020-11-20 2023-01-10 Qualcomm Incorporated Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
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US12062648B2 (en) * 2021-09-24 2024-08-13 Qualcomm Incorporated Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods
US20230114404A1 (en) * 2021-09-30 2023-04-13 Qualcomm Incorporated Embedded trace substrate (ets) with embedded metal traces having multiple thickness for integrated circuit (ic) package height control
US11791320B2 (en) * 2021-11-22 2023-10-17 Qualcomm Incorporated Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

Also Published As

Publication number Publication date
JP2024541421A (ja) 2024-11-08
EP4437586A1 (en) 2024-10-02
WO2023091851A1 (en) 2023-05-25
US11791320B2 (en) 2023-10-17
KR20240101796A (ko) 2024-07-02
TW202329347A (zh) 2023-07-16
US20230163112A1 (en) 2023-05-25

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