CN118248555A - MOSFET power device integrated with heterojunction diode and manufacturing method thereof - Google Patents
MOSFET power device integrated with heterojunction diode and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a MOSFET power device integrated with a heterojunction diode and a manufacturing method thereof, wherein the method comprises the following steps: forming a silicon carbide epitaxial layer on a silicon carbide substrate; forming a communication region in the silicon carbide epitaxial layer; forming a silicon epitaxial layer over the silicon carbide epitaxial layer; forming a well region in the silicon carbide epitaxial layer; forming side walls on two sides of the silicon epitaxial layer, and forming a source region in the well region through the side walls; removing the side wall and part of the silicon epitaxial layer to form a heteroepitaxial layer; forming a gate electrode and a dielectric layer on the silicon carbide epitaxial layer; and forming a source electrode on the surface of the device and forming a drain electrode on the back surface of the silicon carbide substrate. According to the invention, the heteroepitaxial layer is arranged on the gap between the adjacent well regions, so that the protection effect on the gate dielectric is improved, the heterojunction diode is integrated in the silicon carbide MOSFET power device, the third quadrant characteristic of the device is greatly improved, and the switching loss is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) power device integrated with a heterojunction diode and a manufacturing method thereof.
Background
Advances in the power electronics industry have made it increasingly difficult for silicon material devices to meet the increasingly stringent application requirements. Because of the larger forbidden bandwidth, higher electron saturation drift velocity, stronger irradiation resistance, higher breakdown electric field and thermal conductivity, the SiC material has considerable application prospect in the fields of new energy automobiles, rail transit, aerospace systems, military electronic communication systems and the like. The advantages of the material determine the characteristics of low on-resistance, high switching speed, high temperature resistance and the like of a SiC metal oxide field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor), so that the SiC metal oxide field effect Transistor is focused in domestic and foreign scientific research institutions and companies.
The gate dielectric materials of the SiC MOSFET power devices which are commercially produced at present are SiO 2, however, the dielectric constant of the SiC materials is 3 times that of the SiO 2 materials, so that the gate dielectric needs to bear higher electric field strength in the off state, and the devices break down in advance. Improving the reliability of the gate dielectric is a key point of SiC MOSFET research.
In addition, the larger forbidden bandwidth of the SiC material results in the operation at the third quadrant, the body diode of the SiC MOSFET device has higher turn-on voltage, poorer reverse recovery characteristics, higher switching loss, and the body diode conduction causes bipolar degradation. To solve this problem, conventional structures typically use SiC MOSFET devices in parallel with an external diode, but this results in increased cost and reduced device reliability after metal wiring. The schottky barrier diode or the low barrier diode is integrated in the device, so that the problems of increased leakage current, increased cell size, increased manufacturing difficulty and the like are caused.
Disclosure of Invention
Aiming at the defects of the SiC MOSFET power device, the invention provides the MOSFET power device integrated with the heterojunction diode and the manufacturing method thereof, and the heterojunction diode is integrated in the SiC MOSFET device through the contact of the heteroepitaxial layer and the communicating region and the heteroepitaxial layer by forming the heteroepitaxial layer on the silicon carbide epitaxial layer, so that the bipolar degradation effect is avoided under the third quadrant working condition, and the starting voltage and the switching loss of the device are effectively reduced.
A method of fabricating a heterojunction diode integrated MOSFET power device comprising the steps of:
STEP1, forming a silicon carbide epitaxial layer on a silicon carbide substrate;
STEP 2, forming a communication region in the silicon carbide epitaxial layer;
STEP3, forming a silicon epitaxial layer covering the communication region on the silicon carbide epitaxial layer;
STEP4, forming photoresist on the silicon epitaxial layer, wherein the photoresist is positioned on the projection of the communication area;
STEP5, etching the silicon epitaxial layer according to the photoresist to form a patterned silicon epitaxial layer;
STEP6, forming a well region in the silicon carbide epitaxial layer through the patterned silicon epitaxial layer, wherein the depth of the well region is larger than that of the communication region, the well region wraps the bottom corners at two sides of the communication region, and the patterned silicon epitaxial layer is used as the well region to be injected into the epitaxial layer;
STEP7, forming side walls on two sides of the well region implanted epitaxial layer, forming a source region in the well region according to the side walls, and taking the top of the well region implanted epitaxial layer as the source region implanted epitaxial layer;
STEP8, removing the side wall and the source region, injecting the epitaxial layer, and forming a heteroepitaxial layer;
STEP9, forming a first dielectric layer, a second dielectric layer, a first gate electrode and a second gate electrode wrapped by the first dielectric layer and the second dielectric layer on two sides of the heteroepitaxial layer, on part of the communication region, on part of the well region and on part of the source region;
STEP10, source electrode is formed on both sides and upper side of the first dielectric layer, both sides and upper side of the second dielectric layer, and upper side of the heteroepitaxial layer, and drain electrode is formed on bottom of the SiC substrate.
A heterojunction diode-integrated MOSFET power device manufactured by a method of manufacturing a heterojunction diode-integrated MOSFET power device as described above, comprising
A drain electrode;
a silicon carbide substrate over the drain electrode;
A silicon carbide epitaxial layer over the silicon carbide substrate;
A communication region in the silicon carbide epitaxial layer;
a heteroepitaxial layer over the communication region;
the well region is arranged in the silicon carbide epitaxial layer and is self-aligned with the heteroepitaxial layer, and the well region wraps the bottom corners at two sides of the communication region;
a source region among the well regions;
The first dielectric layer and the second dielectric layer are arranged on two sides of the heteroepitaxial layer, on part of the communication region, on part of the well region and on part of the source region;
A first gate electrode surrounded by a first dielectric layer; a second gate electrode surrounded by a second dielectric layer;
source electrodes are formed on the two sides and the upper side of the first dielectric layer, on the two sides and the upper side of the second dielectric layer and on the heteroepitaxial layer.
The invention adopts the technical scheme and has the following beneficial effects:
According to the invention, the heteroepitaxial layer is formed on the silicon carbide epitaxial layer, and the patterned silicon epitaxial layer in the manufacturing method process, so that the self alignment of the heteroepitaxial layer and the well region is realized, the heteroepitaxial layer is contacted with the communication region, the heterojunction diode is integrated in the silicon carbide MOSFET device, and under the third quadrant working condition, the bipolar degradation effect is avoided, and the starting voltage and the switching loss of the device are effectively reduced.
According to the invention, by designing the heteroepitaxial layer, the dielectric layers, namely the first dielectric layer and the second dielectric layer, are prevented from being arranged on the gaps between the adjacent well regions, so that the protection effect of the well regions on the gate dielectric is remarkably improved, the peak electric field born by the gate dielectric in the off state is effectively reduced, and the reliability of the device is further improved.
Drawings
Fig. 1 is a process flow diagram of a method of fabricating a heterojunction diode integrated silicon carbide MOSFET power device.
Fig. 2 to 12 are specific flowcharts of a method for manufacturing a silicon carbide MOSFET power device integrated with a heterojunction diode according to embodiment 1.
Reference numerals illustrate: 1. a drain electrode; 2. a silicon carbide substrate; 3. a silicon carbide epitaxial layer; 4. a well region; 5. a source region; 6. a communication region; 7-1, a first gate electrode; 7-2, a second gate electrode; 8-1, a first dielectric layer; 8-2, a second dielectric layer; 9. a heteroepitaxial layer; 9-1, a silicon epitaxial layer; 9-2, implanting an epitaxial layer into the well region; 9-3, injecting an epitaxial layer into the source region; 10. a source electrode; 101. a side wall; 102. and (3) photoresist.
Detailed Description
The invention is further described below in connection with examples which are given solely for the purpose of illustration and are not to be construed as limitations on the scope of the claims, as other alternatives will occur to those skilled in the art and are within the scope of the claims.
Furthermore, in the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
The method for manufacturing the heterojunction diode-integrated MOSFET power device according to the embodiment is shown in FIG. 1, and the method is described below with reference to specific process steps of FIGS. 2-12. The invention comprises the following steps:
STEP1, forming a silicon carbide epitaxial layer 3 on a silicon carbide substrate 2; as shown in fig. 2 and 3, a silicon carbide epitaxial layer 3 is formed on a silicon carbide substrate 2 through epitaxial growth, the material of the silicon carbide substrate 2 can be 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC, the doping type of the silicon carbide substrate 2 can be N type or P type, the thickness of the substrate is 10 mu m-1000 mu m, and the doping concentration is 1e18cm -3~5e19cm-3; the silicon carbide epitaxial layer 3 is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC, the thickness range is5 mu m-200 mu m, the doping type of the silicon carbide epitaxial layer 3 is N type or P type, and the doping concentration of the silicon carbide epitaxial layer 3 is 1e14cm -3~ 5e16cm-3;
STEP 2, forming a communication region 6 in the silicon carbide epitaxial layer 3; as shown in fig. 4, a communication region 6 is formed in the silicon carbide epitaxial layer 3 through a photoetching process, an etching process and an ion implantation process, the doping type of the communication region 6 is N type or P type, the doping concentration of the communication region 6 is 1e17cm -3~5e17cm-3, the depth range of the communication region 6 is 0.2-0.6 mu m, the width range is 0.8-5 mu m, and the doping concentration is 1e17cm -3~5e17cm-3; the top of the communication region 6 is flush with the top of the silicon carbide epitaxial layer 3;
STEP3, forming a silicon epitaxial layer 9-1 covering the communication region 6 on the silicon carbide epitaxial layer 3; as shown in fig. 5, a silicon epitaxial layer 9-1 is formed on the surface of a silicon carbide epitaxial layer 3 through an epitaxial growth process, the doping type of the silicon epitaxial layer 9-1 is N type or P type, the doping concentration is 1e14cm -3~5e16cm-3, and the thickness range is 1 [ mu ] m-3 [ mu ] m; the width of the silicon epitaxial layer 9-1 is the same as the width of the silicon carbide epitaxial layer 3;
STEP4, forming a photoresist 102 on the silicon epitaxial layer 9-1; as shown in fig. 6, a patterned photoresist 102 is formed above the silicon epitaxial layer 9-1 by a photolithography process, the thickness range of the photoresist 102 is 1 μm to 6 μm, and the photoresist 102 is located above the projection of the communication region 6;
STEP5, etching the silicon epitaxial layer 9-1 according to the photoresist 102 to form a patterned silicon epitaxial layer; as shown in fig. 7, etching the silicon epitaxial layer 9-1 by a dry etching process to form a patterned silicon epitaxial layer, wherein etching gas can be one or a combination of gases such as Cl 2、HBr、HeO2, and the width of the formed patterned silicon epitaxial layer ranges from 0.5 [ mu ] m to 4 [ mu ] m, and then removing the photoresist 102;
STEP6, forming a well region 4 in the silicon carbide epitaxial layer 3 through the patterned silicon epitaxial layer, wherein the depth of the well region 4 is larger than that of the communication region 6, the well region 4 wraps the bottom corners of the two sides of the communication region 6, and the patterned silicon epitaxial layer is used as the well region to be injected into the epitaxial layer 9-2; as shown in fig. 8, a well region 4 is formed in the silicon carbide epitaxial layer 3 by an ion implantation process using the patterned silicon epitaxial layer as a mask, and the patterned silicon epitaxial layer after ion implantation is used as a well region implantation epitaxial layer 9-2; the depth range of the well region 4 is 0.5 mu m-1.5 mu m, the doping type of the well region 4 is P type or N type, the doping concentration is 1e17cm -3~5e17cm-3, meanwhile, the well region injection epitaxial layer 9-2 is formed, the doping concentration of the well region injection epitaxial layer 9-2 is 1e17cm -3~5e17cm-3, and the depth range is1 mu m-3 mu m;
STEP7, forming side walls 101 on two sides of the well region injection epitaxial layer 9-2, forming a source region 5 in the well region 4 according to the side walls 101, and taking the top of the well region injection epitaxial layer 9-2 as a source region injection epitaxial layer 9-3; as shown in fig. 9, forming side walls 101 on two sides of a patterned silicon epitaxial layer through a chemical vapor deposition process and an etching process, wherein the material of the side walls 101 is SiO 2, the width range of the side walls 101 is 0.2-0.6 [ mu ] m, then forming a source region 5 in a well region 4 through an ion implantation process, wherein the depth range of the source region 5 is 0.2-0.5 [ mu ] m, the doping type of the source region is N-type or P-type, the doping concentration is 5e18cm -3~5e20cm-3, meanwhile, a source region implantation epitaxial layer 9-3 is formed, the doping concentration of the source region implantation epitaxial layer 9-3 is 5e18cm -3~5e20cm-3, the depth range is 0.3-1.5 [ mu ] m, and the device is activated and annealed for 2-30 min at the temperature of 1400-2200 ℃;
STEP8, removing the side wall 101 and injecting the epitaxial layer 9-3 into the source region to form a heteroepitaxial layer 9; as shown in fig. 10, the side wall 101 is removed by a dry etching process, etching gas is one or more of gases such as CF 4、CHF3 and Ar, then the source region is removed by the dry etching process, the epitaxial layer 9-3 is injected into the source region, the etching gas is one or more of gases such as Cl 2、HBr、HeO2, and after etching is completed, a heteroepitaxial layer 9 is formed, the depth range of the heteroepitaxial layer 9 is 0.3-1.5 mu m, and the width of the heteroepitaxial layer 9 is smaller than the width of the communication region 6; the doping type of the heteroepitaxial layer is the same as that of the well region, and the doping concentration of the heteroepitaxial layer is 1e17cm -3~5e17cm-3;
STEP9, forming a first dielectric layer 8-1, a second dielectric layer 8-2, a first gate electrode 7-1 and a second gate electrode 7-2 wrapped by the first dielectric layer 8-1 and the second dielectric layer 8-2 on two sides of the heteroepitaxial layer 9, on part of the communication region 6, on part of the well region 4 and on part of the source region 5; as shown in FIG. 11, a part of dielectric layer is formed by a chemical vapor deposition process, a photoetching process and an etching process, the material of the part of dielectric layer is SiO 2, the quality of the dielectric layer is improved by a high-temperature annealing process, the annealing gas can be one or a combination of a plurality of gases such as NO, N 2O、H2、NH3 and the like, and the annealing temperature is 900-1300 ℃. Forming a gate electrode by a chemical vapor deposition process, a photoetching process and an etching process, wherein the gate electrode comprises a first gate electrode 7-1 and a second gate electrode 7-2, the gate electrode material is made of polysilicon, polysilicon injection is performed, activation annealing is performed, and a rest dielectric layer is formed by the chemical vapor deposition process, the photoetching process and the etching process, wherein the rest dielectric layer is made of Si 3N4, so that a dielectric layer comprising a first dielectric layer 8-1 and a second dielectric layer 8-2 is obtained; in this step, the first gate electrode 7-1 and the second gate electrode 7-2 may be formed by atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, or sputtering. The materials of the first gate electrode 7-1 and the second gate electrode 7-2 may be polysilicon, amorphous silicon or amorphous silicon, and the doping impurities may be Al, N, P, B or the like.
STEP10, forming source electrode 10 on both sides and upper side of the first dielectric layer 8-1, both sides and upper side of the second dielectric layer 8-2, and upper side of the heteroepitaxial layer 9, and forming drain electrode 1 on the bottom of silicon carbide substrate 2; as shown in fig. 12, metal is evaporated on the front surface of the device, and the metal is selected from Ti or Al alloy, and then annealed at 300-1100 ℃ to form source ohmic contacts. A drain ohmic contact is formed in the bottom layer of the silicon carbide substrate 2 in the same manner. A source electrode 10 is formed on the source ohmic contact surface, and a drain electrode 1 is formed on the drain ohmic contact surface. In the step, metal can be formed by evaporation, sputtering or electroplating, and then ohmic contact is formed by annealing at 300-1100 ℃.
In the invention, the doping types of the silicon carbide substrate 2, the silicon carbide epitaxial layer 3, the source region 5 and the communication region 6 are the same, and the doping types of the well region 4 and the heteroepitaxial layer 9 are the same. The doping type of the well region 4 etc. is the second type if the doping type of the silicon carbide substrate 2 etc. is the first type, and the doping type of the well region 4 etc. is the first type if the doping type of the silicon carbide substrate 2 etc. is the second type. The first type is N-type or P-type, and the second type is P-type or N-type.
According to the invention, a communication region, a well region and a source region are sequentially formed through an ion implantation process, and after all ion implantation processes are finished, annealing is performed for 2 min-30 min at the temperature of 1400-2200 ℃.
In some other embodiments of the present invention, the STEP9 forms a dielectric layer by a thermal oxidation process or a chemical vapor deposition process, and the material of the dielectric layer may be SiO 2、Si3N4、Al2O3 or the like. The quality of the gate dielectric layer can be improved through a high-temperature annealing process, the annealing gas can be one or more of gases such as NO, N 2O、H2、NH3 and the like, and the annealing temperature is 900-1300 ℃.
The metal material of the source metal and the drain metal may be one or more of Al, ti, ag, ni, pt, cu or other metals.
The embodiment also discloses a MOSFET power device integrated with the heterojunction diode, comprising:
A drain electrode 1;
a silicon carbide substrate 2 over the drain electrode 1;
A silicon carbide epitaxial layer 3 on top of the silicon carbide substrate 2;
A communication region 6 in the silicon carbide epitaxial layer 3;
a heteroepitaxial layer 9 over the communication region 6;
Well regions 4 in the silicon carbide epitaxial layer 3 and self-aligned with the heteroepitaxial layer 9, the well regions 4 wrapping the bottom corners of both sides of the communication region 6;
Source regions 5 among the well regions 4;
A first dielectric layer 8-1 and a second dielectric layer 8-2 on both sides of the heteroepitaxial layer 9, on part of the communication region 6, on part of the well region 4 and on part of the source region 5;
A first gate electrode 7-1 surrounded by the first dielectric layer 8-1; a second gate electrode 7-2 surrounded by a second dielectric layer 8-2;
source electrodes 10 are formed on both sides and over the first dielectric layer 8-1, on both sides and over the second dielectric layer 8-2, and over the heteroepitaxial layer 9.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.
Claims (10)
1. A method of fabricating a heterojunction diode integrated MOSFET power device comprising the steps of:
STEP1, forming a silicon carbide epitaxial layer on a silicon carbide substrate;
STEP 2, forming a communication region in the silicon carbide epitaxial layer;
STEP3, forming a silicon epitaxial layer covering the communication region on the silicon carbide epitaxial layer;
STEP4, forming photoresist on the silicon epitaxial layer, wherein the photoresist is positioned on the projection of the communication area;
STEP5, etching the silicon epitaxial layer according to the photoresist to form a patterned silicon epitaxial layer;
STEP6, forming a well region in the silicon carbide epitaxial layer through the patterned silicon epitaxial layer, wherein the depth of the well region is larger than that of the communication region, the well region wraps the bottom corners at two sides of the communication region, and the patterned silicon epitaxial layer is used as the well region to be injected into the epitaxial layer;
STEP7, forming side walls on two sides of the well region implanted epitaxial layer, forming a source region in the well region according to the side walls, and taking the top of the well region implanted epitaxial layer as the source region implanted epitaxial layer;
STEP8, removing the side wall and the source region, injecting the epitaxial layer, and forming a heteroepitaxial layer;
STEP9, forming a first dielectric layer, a second dielectric layer, a first gate electrode and a second gate electrode wrapped by the first dielectric layer and the second dielectric layer on two sides of the heteroepitaxial layer, on part of the communication region, on part of the well region and on part of the source region;
STEP10, source electrode is formed on both sides and upper side of the first dielectric layer, both sides and upper side of the second dielectric layer, and upper side of the heteroepitaxial layer, and drain electrode is formed on bottom of the SiC substrate.
2. The method for manufacturing the heterojunction diode integrated MOSFET power device according to claim 1, wherein in STEP3, the doping type of the silicon epitaxial layer is N type or P type, the doping concentration is 1e14cm -3~5e16cm-3, and the thickness range is 1 [ mu ] m-3 [ mu ] m; the width of the silicon epitaxial layer is the same as that of the silicon carbide epitaxial layer; the width range of the patterned silicon epitaxial layer in STEP5 is 0.5 mu m-4 mu m.
3. The manufacturing method of the heterojunction diode integrated MOSFET power device according to claim 1, wherein the depth range of the well region is 0.5-1.5 mu m, and the depth range of the source region is 0.2-0.5 mu m.
4. The method for manufacturing the heterojunction diode integrated MOSFET power device according to claim 1, wherein the depth range of the heteroepitaxial layer is 0.3 [ mu ] m-1.5 [ mu ] m, and the width of the heteroepitaxial layer is smaller than the width of the communication region; the doping type of the heteroepitaxial layer is the same as that of the well region, and the doping concentration of the heteroepitaxial layer is 1e17cm -3~5e17cm-3.
5. The method for manufacturing the MOSFET power device integrated with the heterojunction diode according to claim 1, wherein the communication area, the well area and the source area are sequentially formed through an ion implantation process, and annealing is performed for 2 min-30 min at the temperature of 1400 ℃ -2200 ℃ after all the ion implantation processes are finished.
6. The method for manufacturing the heterojunction diode integrated MOSFET power device according to claim 1, wherein the doping concentration of the well region injection epitaxial layer is 1e17cm -3~5e17cm-3, and the depth range is 1 [ mu ] m-3 [ mu ] m.
7. The method for manufacturing the heterojunction diode integrated MOSFET power device according to claim 1, wherein the doping concentration of the source region implanted epitaxial layer is 5e18cm -3~5e20cm-3, and the depth range is 0.3 [ mu ] m to 1.5 [ mu ] m.
8. The method of manufacturing a heterojunction diode-integrated MOSFET power device of claim 1, wherein the material of the first gate electrode and the second gate electrode is polysilicon, amorphous silicon or amorphous silicon, and the doping impurity is Al, N, P or B element.
9. The method of claim 1, wherein the metal material of the source electrode and the drain electrode is one or more of Al, ti, ag, ni, pt, cu.
10. A heterojunction diode-integrated MOSFET power device manufactured by a method of manufacturing a heterojunction diode-integrated MOSFET power device as claimed in any one of claims 1 to 9, comprising
A drain electrode;
a silicon carbide substrate over the drain electrode;
A silicon carbide epitaxial layer over the silicon carbide substrate;
A communication region in the silicon carbide epitaxial layer;
a heteroepitaxial layer over the communication region;
the well region is arranged in the silicon carbide epitaxial layer and is self-aligned with the heteroepitaxial layer, and the well region wraps the bottom corners at two sides of the communication region;
a source region among the well regions;
The first dielectric layer and the second dielectric layer are arranged on two sides of the heteroepitaxial layer, on part of the communication region, on part of the well region and on part of the source region;
A first gate electrode surrounded by a first dielectric layer; a second gate electrode surrounded by a second dielectric layer;
source electrodes are formed on the two sides and the upper side of the first dielectric layer, on the two sides and the upper side of the second dielectric layer and on the heteroepitaxial layer.
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