CN118231472A - Groove gate super junction device capable of reducing input capacitance and preparation method thereof - Google Patents
Groove gate super junction device capable of reducing input capacitance and preparation method thereof Download PDFInfo
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a trench gate superjunction device for reducing input capacitance, which comprises a superjunction structure charge balance region and a body region positioned at the top of the superjunction structure charge balance region, wherein the superjunction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed, a trench gate is arranged in the body region at the top of the first conductive type columns, an active region is arranged at one side of the trench gate, which is close to the second conductive type columns, and the active region is positioned in the body region in the first conductive type columns; the source region is connected to the source metal through a source contact hole. According to the trench gate superjunction device for reducing the input capacitance, the input capacitance of the superjunction MOSFET device is reduced by changing the position of the source region and the connection relation between the source region and the trench gate, and the starting speed of the MOSFET device is improved.
Description
Technical Field
The invention relates to the field of preparation of superjunction devices, in particular to a trench gate superjunction device for reducing input capacitance and a preparation method thereof.
Background
Compared with a conventional high-voltage MOSFET device, the super-junction structure not only can maintain high withstand voltage, but also can reduce on resistance by increasing doping concentration of a drift region, and can realize smaller chip area, faster switching speed and higher power conversion efficiency by inserting the P-type columns in the longitudinal drift region.
As shown in fig. 1, the layout top view of the trench gate superjunction device is shown, the charge flow area is 200, and the termination area is 300; the charge flow region 200 includes a super junction structure formed by a plurality of groups of N-type pillars 101 and P-type pillars 100 arranged alternately, wherein the N-type pillars 101 and the P-type pillars 100 are both elongated structures. During operation of the device, N-type column 101 provides a conduction path when conducting, and P-type column 100 is depleted from N-type column 101 to withstand high withstand voltages when the device is reverse biased.
In the switching process of the super device, due to the change of the depletion layer, the gate-source capacitance Cgs and the gate-drain capacitance Cgd can change along with the change of the applied voltage, and dv/dt (the rate of change of the drain voltage along with time) can be influenced by the gate-drain capacitance Cgd and the gate-source capacitance Cgs, so that the electromagnetic interference (Electromagnetic Interference) is greatly changed, and the switching characteristic of the device is influenced.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the problems in the related art. Therefore, one of the purposes of the present invention is to provide a trench gate superjunction device for reducing the input capacitance, which reduces the input capacitance of the superjunction MOSFET device and increases the turn-on speed of the MOSFET device by changing the position of the source region and the connection relationship between the source region and the trench gate.
In order to achieve the above purpose, the present application adopts the following technical scheme: the trench gate superjunction device for reducing the input capacitance comprises a superjunction structure charge balance region, wherein the superjunction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed, the tops of the first conductive type columns are provided with trench gates, one side, close to the second conductive type columns, of each trench gate is provided with a body region, and the tops of the body regions are provided with active regions; the source region is connected to the source metal through a source contact hole.
Further, the bottom of the charge balance region of the super junction structure is sequentially connected with a first conductive type buffer layer and a first conductive type substrate, and the doping concentration of the first conductive type buffer layer is smaller than that of the first conductive type substrate.
Further, a total thickness of the super junction structure charge balance region and the first conductivity type buffer layer is less than 55 microns.
Further, in a direction in which the first conductive type pillars and the second conductive type pillars are alternately arranged, a width of the first conductive type pillars is larger than a width of the second conductive type pillars; and the doping concentration of the first conductivity type column is smaller than the doping concentration of the second conductivity type column.
Further, the trench gate comprises a gate dielectric layer and a gate electrode, a filling groove is formed in the top of the first conductive type column, and the gate dielectric layer and the gate electrode are sequentially filled in the filling groove.
Further, the bottom of the filling groove is lower than the bottom of the body region.
Further, an isolation layer is arranged on the top of the charge balance region of the super junction structure, the source metal is located on the top of the isolation layer, and the source contact hole penetrates through the isolation layer and extends to the inside of the charge balance region of the super junction structure.
Further, the source contact hole is located in the first conductive type column, the source contact hole is located at one side, far away from the trench gate, of the source region, the doping concentration of the bottom of the source contact hole is larger than that of the source region, and the source metal is connected with the source region through the source contact hole.
Further, the source contact hole is further located in the second conductive type column, the source contact hole is located in the center of the second conductive type column, and the doping concentration of the bottom of the source contact hole is greater than that of the body region.
The application also provides a preparation method of the trench gate superjunction device for reducing the input capacitance, which comprises the following steps:
Forming a super junction structure charge balance region on the surface of the first conductive type substrate, wherein the super junction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed;
forming a body region on one side of the trench gate in the first conductive type column through an ion implantation push-well process;
etching the top of the first conductive type column to form a filling groove, and filling a groove gate in the filling groove;
Doping the heavily doped region of the first conductivity type in the body region by a polysilicon self-alignment process to form a source region; the source region is positioned in the body region in the first conductive type column, and the source region is positioned near one side of the second conductive type column;
Etching a source electrode contact hole in the top of the charge balance region and the body region of the super junction structure;
filling source metal, wherein the source region is connected to the source metal through a source contact hole;
And forming a drain electrode on the back surface of the first conductive type substrate.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: the application discloses a trench gate superjunction device for reducing input capacitance, which comprises a superjunction structure charge balance region, wherein the superjunction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed, the top of each first conductive type column is provided with a trench gate, one side, close to the second conductive type column, of each trench gate is provided with a body region, and the top of each body region is provided with an active region; the source region is connected to the source metal through a source contact hole; according to the application, the body region is arranged on one side of the trench gate, and the source region is arranged on the top of the body region, so that the first conductive type column and the first conductive type column are reduced in size, the doping concentration is increased, and the on-resistance of the device is more advantageous. Meanwhile, under the condition of reducing the actual channel density by adjusting the integral region and the source region injection region, the application ensures that the on-resistance of the device is increased by not more than 5 percent (the on-resistance of the superjunction device mainly comprises a source region resistance, a channel resistance, a drift region resistance and a substrate resistance, wherein the drift region resistance accounts for about 95 percent), the input capacitance is reduced by at least about 33 percent, the gate-source capacitance is reduced by about one time, and the balance is well realized between the on-resistance and the input capacitance, thereby improving the switching speed of the superjunction device, reducing the switching loss of the superjunction device and improving the frequency of the device.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
In the accompanying drawings:
FIG. 1 is a schematic top view of a P-type pillar layout in a super junction MOSFET device layout of the present application;
Fig. 2 is a schematic cross-sectional view of a trench gate superjunction MOSFET device of the comparative example, taken along the direction of the charge flow region AA' of fig. 1;
FIG. 3 is a schematic cross-sectional view of a superjunction MOSFET device structure of the present application;
fig. 4 is a comparison of Ci ss curves of superjunction MOSFET devices in this example and comparative example;
FIG. 5 is a graph showing comparison of Coss curves of superjunction MOSFET devices in the present example and comparative example
FIG. 6 is a graph showing the comparison of the Crss curves of the superjunction MOSFET devices of the present example and the comparative example
Fig. 7 is a graph comparing Cgs curves of superjunction MOSFET devices in this example and comparative example.
Reference numerals: 1. a first conductivity type substrate; 2. a first conductive type buffer layer; 3. a second conductivity type pillar; 4. a first conductivity type pillar; 5. a body region; 6. a source region; 7. a second doped region; 8. a gate dielectric layer; 9. a gate; 10. a source contact hole; 11. a source metal; 12. an isolation layer; 13. a drain electrode; 100. a P-type column; 200. an N-type column; 300. a termination region.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings. In the following description, it should be understood that the directions or positional relationships indicated by "front", "rear", "upper", "lower", "left", "right", "longitudinal", "transverse", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail", etc. are configured and operated in specific directions based on the directions or positional relationships shown in the drawings, and are merely for convenience of describing the present invention, not to indicate that the mechanism or element referred to must have specific directions, and thus should not be construed as limiting the present invention.
It should also be noted that unless explicitly stated or limited otherwise, terms such as "mounted," "connected," "secured," "disposed," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. When an element is referred to as being "on" or "under" another element, it can be "directly" or "indirectly" on the other element or one or more intervening elements may also be present. The terms "first," "second," "third," and the like are used merely for convenience in describing the present invention and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, whereby features defining "first," "second," "third," etc. may explicitly or implicitly include one or more such features. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, mechanisms, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Example 1
Referring to fig. 1 and 3, the present application provides a trench gate superjunction device for reducing input capacitance, which includes a superjunction structure charge balance region, the superjunction structure charge balance region includes first conductive type pillars 4 and second conductive type pillars 3 alternately distributed, wherein a trench gate is disposed in a body region 5 on top of the first conductive type pillars 4, a body region 5 is disposed on one side of the trench gate near the second conductive type pillars 3, an active region 6 is disposed on top of the body region 5, and the source region 6 is connected to a source metal 11 through a source contact hole 10.
The on-resistance of the superjunction device mainly comprises a source region 6 resistor, a channel resistor, a drift region resistor and a substrate resistor, wherein the drift region resistor occupies about 95%, and the channel resistor occupies smaller area. The application reduces the actual channel density by adjusting the injection region positions of the integral region 5 and the source region 6, which can lead to the increase of the channel resistance. Because the channel resistance occupies smaller area in the on-resistance of the device, the application can ensure that the increase of the on-resistance is less than or equal to 5 percent compared with the increase of the comparative example.
However, due to the fact that the actual channel density is reduced, compared with a device structure in a comparative example, the input capacitance of the super junction device is reduced by at least 33%, the gate-source capacitance is reduced by one time, and the balance between the on-resistance and the input capacitance is well achieved, so that the switching speed of the super junction device is improved, the switching loss of the super junction device is reduced, and the frequency of the device is improved.
Meanwhile, the body region 5 and the source region 6 are arranged on one side of the trench gate, so that the first conductive type column 4 and the first conductive type column are reduced in size, the doping concentration is increased, and the on-resistance of the device is more advantageous.
The other side of the trench gate does not have a body region, i.e., the application optimizes the capacitive performance parameters by reducing the contact of the gate with the body region. That is, the problem to be solved by the present application is how to reduce the input capacitance of the trench gate device, and further, the present application achieves the relationship between the balanced on-resistance and the capacitance by changing the injection region of the body source region and the connection relationship between the body source region and the trench gate.
Example 2
Referring to fig. 1 and 3, the present application provides a trench gate superjunction device for reducing input capacitance, which includes a superjunction structure charge balance region, the superjunction structure charge balance region includes first conductive type pillars 4 and second conductive type pillars 3 alternately distributed, wherein a trench gate is disposed in a body region 5 on top of the first conductive type pillars 4, a body region 5 is disposed on one side of the trench gate near the second conductive type pillars 3, an active region 6 is disposed on top of the body region 5, and the source region 6 is connected to a source metal 11 through a source contact hole 10.
Specifically, the bottom of the charge balance region of the super junction structure is sequentially connected with the first conductive type buffer layer 2 and the first conductive type substrate 1, and the doping concentration of the first conductive type buffer layer 2 is smaller than that of the first conductive type substrate 1.
The application epitaxially grows a first conductive type buffer layer 2 on the surface of a first conductive type substrate 1, and then epitaxially grows on the surface of the first conductive type buffer layer 2. When the trench gate superjunction device is an N-type device, the first conductivity type is N-type and the second conductivity type is P-type. Or when the trench gate superjunction device is a P-type device, the first conductivity type is P-type and the second conductivity type is N-type. Thus, in a specific embodiment of the application the substrate is comprised of an As or P dopant of the first conductivity type and has a resistivity of between 0.001ohm cm and 0.003ohm cm.
Wherein the total thickness of the super junction structure charge balance region and the first conductivity type buffer layer 2 is less than 55 micrometers, and the minimum value of the total thickness is determined by the trench depth and the etching machine capability.
The super junction structure charge balance region includes first conductivity type pillars 4 and second conductivity type pillars 3 alternately distributed. The first conductive type columns 4 and the second conductive type columns 3 are alternately distributed to form a super junction structure charge balance region. The charge balance area of the super junction structure comprises a plurality of cell structures which are arranged in parallel, each cell structure is composed of a first conductive type column 4 and a second conductive type column 3, the first conductive type column 4 and the second conductive type column 3 are in charge balance, and the cell structures are sequentially arranged to form the complete charge balance area of the super junction structure.
The body region 5 is formed on one side of the trench gate at the top of the first conductive type column 4 in the present application, and the upper surface of the body region 5 is flush with the upper surface of the first conductive type column 4. Specifically, a body region 5 of the second conductivity type can be locally formed on the surface of the first conductivity type column 4 through a mask plate and an ion implantation push-well process. Since the body region is formed before the trench gate, but before the body region is formed, the overall structure of the trench gate device of the present application is known, that is, the position of the trench gate is known, at this time, we can ensure that the body region is formed only on one side of the trench gate during the implantation process by designing the position and size of the via hole in the mask. As shown in fig. 3, the second conductivity type pillars and portions of the two first conductivity type pillars between the two trench gates are body region free.
The trench gate is arranged in the first conductive type column 4 only, the trench gate comprises a gate dielectric layer 8 and a gate 9, a filling groove is arranged at the top of the first conductive type column 4, the gate dielectric layer 8 and the gate 9 are sequentially filled in the groove, that is to say, the gate dielectric layer 8 is in contact with the body region 5, and the gate 9 is positioned in the gate dielectric layer 8. The trench gate may extend through the body region 5 into the first conductivity type pillar 4 under the body region 5 in the present application, i.e., the depth of the trench gate in the first conductivity type pillar 4 is greater than the junction depth of the body region 5 after the body region 5 is implanted into the push well. And the gates 9 in all the cells of the present application may be connected to each other.
The dielectric layer of the grid electrode 9 is composed of an oxide layer, and the thickness of the oxide layer can be adjusted according to requirements.
The present application provides the source region 6 only on one side of the trench gate, where one side refers to the side of the trench gate that is closer to or farther from the second conductivity type pillar 3 in the same cellular structure. To simplify the process, as shown in fig. 3, the cell in the charge balance region of the superjunction structure may be divided into two halves, and the cell on the left side is provided with a trench gate on the side away from the second conductivity type pillar 3, i.e., on the left side inside the first conductivity type pillar 4. The right-hand cell places the trench gate on the side close to the second conductivity type pillar 3, i.e. on the right-hand side inside the first conductivity type pillar 4. In this way, in the present application, the source region 6 in the cell located at the left side of the center of the charge balance region of the superjunction structure is disposed at the left side of the trench gate, and the source region 6 in the cell located at the right side of the center of the charge balance region of the superjunction structure is disposed at the right side of the trench gate, so that the process steps for forming the source region 6 can be simplified.
In other embodiments, it is only necessary to ensure that the trench gate is disposed only in the first conductivity type pillar 4 in each unit cell, and the source region 6 is disposed only at one side of the trench gate, and the specific location of the source region 6 may not be limited. While the second conductivity type pillars 3 are not provided with the source regions 6 inside in the present application.
The source region 6 is only arranged on one side of the first conductive type column 4, and a channel formed by the body region 5 and the source region 6 is not included between two adjacent trench gate structures.
The top of the super junction structure charge balance region is provided with an isolation layer 12, the source metal 11 is located at the top of the isolation layer 12, the source contact hole 10 penetrates through the isolation layer 12 and extends to the inside of the super junction structure charge balance region, and the etching depth of the source contact hole 10 on the upper surfaces of the epitaxial layers of the first conductive type column 4 and the second conductive type column 3 is greater than 3000A. The source contact hole 10 may be located only inside the first conductive type column 4 in the present application, or may be located inside both the first conductive type column 4 and the second conductive type column 3.
When the source contact hole 10 is located in the first conductive type column 4, the source contact hole 10 is located at a side of the source region 6 away from the trench gate, the doping concentration of the bottom of the source contact hole 10 is greater than that of the source region 6, and the source metal 11 is connected with the source region 6 through the source contact hole 10. The source contact hole 10 located in the first conductive type pillar 4 is located at an edge position of the first conductive type pillar 4, that is, at a position where the second conductive type pillar 3 and the first conductive type pillar 4 meet, and the source region 6 is located between the source contact hole 10 and the trench gate. Only one source contact hole 10 is provided in each first conductive type pillar 4. The junction depth of the source region 6 after the implantation of the push-well is smaller than the depth of the source contact hole 10 etched in the first conductivity type pillar 4.
When the source contact hole 10 is further located in the second conductive type pillar 3, the source contact hole 10 is located at a center position of the second conductive type pillar 3, and a doping concentration of a bottom of the source contact hole 10 is greater than a doping concentration of the body region 5. Each second conductive-type pillar 3 is provided with only one source contact hole 10 at a central position, and the size of the source contact hole 10 located in the second conductive-type pillar 3 may be equal to or larger than the size of the source contact hole 10 in the first conductive-type pillar 4. The source contact holes 10 on the second conductivity type pillars 3 can optimize the electric field intensity of the device, and optimize the current dispersion and thus the concentration when the device is operated.
Since the trench gate, the source region 6 and the source contact hole 10 are required to be arranged in the first conductive type column 4 and only the source contact hole 10 is required to be arranged in the second conductive type column 3 in the application, the width of the first conductive type column 4 is larger than the width of the second conductive type column 3 in the direction in which the first conductive type column 4 and the second conductive type column 3 are alternately distributed; and the doping concentration of the first conductivity type pillars 4 is smaller than the doping concentration of the second conductivity type pillars 3. The first conductivity type pillars 4 and the second conductivity type pillars 3 in the cells have different widths, and the first conductivity type pillars 4 and the second conductivity type pillars 3 can be further reduced in size while maintaining the charge balance of the first conductivity type pillars 4 and the second conductivity type pillars 3. Due to the fact that the density of a channel is reduced, the cell step is 2 times of that of a conventional trench gate superjunction MOSFET device, the size of the cell can be reduced, and the size of the superjunction device is further reduced.
The super junction device further comprises a drain electrode 13, wherein the drain electrode 13 is positioned on the bottom surface of the first conductive type substrate 1 and consists of a first conductive type heavily doped region on the back surface of the first conductive type epitaxial layer.
FIG. 1 is a schematic top view of a P-type pillar layout in a trench gate superjunction MOSFET device layout in an embodiment of the present invention; the middle area of the layout is a charge flow area 200, the terminal area 300300 is arranged around the charge flow area, and the charge flow area 200 comprises a super-junction MOSFET structure formed by a plurality of P columns and N columns which are alternately arranged; each P column and each N column form a super junction structure; in the charge flow region 200, the superjunction device includes a plurality of cell structures. The P-pillars and N-pillars are the above first conductivity type pillars 4 and second conductivity type pillars 3.
The application also provides a preparation method of the trench gate superjunction device for reducing the input capacitance, which comprises the following steps:
S1: a super junction structure charge balance region including first conductivity type pillars 4 and second conductivity type pillars 3 alternately distributed is formed on the surface of the first conductivity type substrate 1.
The method specifically comprises the following steps:
Forming a first conductive type heavily doped silicon substrate, and forming a first conductive type buffer layer 2 on the first conductive type heavily doped silicon substrate;
Forming a first conductive type epitaxial layer, and defining an etching region of the second conductive type column 3 on the first conductive type silicon epitaxial layer through a photoetching process; etching the second conductive type column 3 area on the first conductive type silicon epitaxial layer; the specific etching process can adopt dry etching, and an etching area in the epitaxial layer has a trapezoid shape with a larger upper part and a smaller lower part. And after the etching process, adopting a sacrificial oxidation process to treat the surface of the etching area.
Performing second conductivity type source doping on the bottom of the second conductivity type column 3 region after deep trench etching on the second conductivity type column 3 region to form a second conductivity type column 3;
And after deep trench etching injection is performed on the region of the second conductive type column 3, filling a silicon medium doped with the second conductive type to form a super junction structure charge balance region formed by the first conductive type column 4 and the second conductive type column 3.
After the second conductivity type doped silicon medium is filled, the hard mask on the surface of the epitaxial layer is removed, and then the planarization treatment of the epitaxial layer is carried out by adopting a chemical mechanical polishing process.
S2: forming a body region 5 on the surface of the first conductive type column 4 locally through a mask plate and an ion implantation push-well process; the body region 5 is of a second conductivity type 5.
Since the body region is formed before the trench gate, but before the body region is formed, the overall structure of the trench gate device of the present application is known, that is, the position of the trench gate is known, at this time, we can ensure that the body region is formed only on one side of the trench gate during the implantation process by designing the position and size of the via hole in the mask. As shown in fig. 3, the second conductivity type pillars and portions of the two first conductivity type pillars between the two trench gates are body region free.
S3: a filling trench is etched on top of the first conductivity type column 4, and a trench gate is filled in the filling trench.
Specifically, a filling groove is formed at the top of the first conductive type column 4 in the charge balance region of the super junction structure through a photoetching process, and a gate dielectric layer 8 is formed on the side wall and the bottom of the filling groove; the filling grooves are filled with the grid electrode 9, and the grid electrode 9 is a dielectric layer of the first conductivity type. The gate dielectric layer 8 is formed by a thermal oxidation process, and the thickness of the oxide layer can be adjusted according to requirements.
S4: doping a heavily doped region of the first conductivity type in the body region 5 by a polysilicon self-alignment process to form a source region 6; the source region 6 is located within the body region 5 in the first conductivity type pillar 4 and the source region 6 is located adjacent one side of the second conductivity type pillar 3. Wherein a source region 6 is formed by doping a heavily doped region of the first conductivity type in a body region 5 of the second conductivity type by a polysilicon self-aligned process for forming a channel.
S5: and etching the top of the charge balance region and the body region 5 of the super junction structure to form a source electrode contact hole 10.
Firstly, depositing an isolation layer 12 on the top of a charge balance region of the super junction structure;
The source contact hole 10 is located in both the first conductivity type pillar 4 and the second conductivity type pillar 3. And the source contact hole 10 is located at the edge of the first conductive type pillar 4 and at the center of the second conductive type pillar 3.
After the source contact hole 10 is formed, a second doped region 7 is formed at the bottom of the source contact hole 10 by adopting an ion implantation push-pull well process, the doping type of the second doped region 7 is the same as that of the body region 5, and the doping concentration of the second doped region 7 is greater than that of the body region 5. The second doped region 7 can further enhance the reliability of the device, and the second doped region 7 ensures that the device can withstand the maximum avalanche energy when the device gate is pulsed.
S6: filling a source metal 11, wherein the source region 6 is connected to the source metal 11 through a source contact hole 10;
s7: and thinning the back surface of the first conductive type heavily doped silicon substrate to form a drain electrode 13.
The dimensions and concentration of the first conductivity type pillars 4 and the second conductivity type pillars 3 of the trench gate device of the present application can be further reduced by half compared to the prior art, and the concentration can be further increased, thereby more optimizing the on-resistance of the device.
The source electrode contact hole 10 on the second conductive type column 3 can optimize the electric field intensity of the device, and the current is dispersed and not concentrated when the device works.
Under the condition that a photomask is not required to be additionally increased, the trench gate device provided by the invention ensures that the on-resistance of the device is increased by not more than 5% under the condition that the actual channel density is reduced by adjusting the injection areas of the body area 5 and the source area 6 (the on-resistance of the super junction device mainly comprises the resistance of the source area 6, the channel resistance, the drift area resistance and the substrate resistance, wherein the drift area resistance accounts for about 95%), the input capacitance is reduced by at least about 33%, the gate-source capacitance is reduced by about one time, and the balance is well achieved between the on-resistance and the input capacitance, so that the switching speed of the super junction device is improved, the switching loss of the super junction device is reduced, and the frequency of the device is improved.
Comparative example
The comparative example differs from example 1 in that: as shown in fig. 2, the body region 5 and the source region 6 are simultaneously disposed at two sides of the trench gate, and two source contact holes 10 are disposed in each cell structure, and the two source contact holes 10 are respectively located at one side of the source region 6 away from the trench gate, that is, the two source contact holes 10 are located at the junction position of the first conductive type column 4 and the second conductive type column 3 in the cell. As shown in fig. 2, the body region is integrally formed on the upper surfaces of the first conductivity type pillars 4 and the second conductivity type pillars 3.
The difference between embodiment 2 and the comparative example is that in embodiment 1, no channel is formed between the two trench gates, wherein the body region 5 is not in contact with the body region 5 between the side close to the trench gate, which is not in contact with the body region 5, and the top side of the second conductivity type pillar 3, and the structure of the non-source contact hole 10 is only provided on the upper surface of the second conductivity type pillar 3.
Fig. 4-7 are graphs comparing the Ciss/Coss/Crss/Cgs curves of the trench gate superjunction MOSFET device of the comparative example and the superjunction MOSFET device of example 2. Crss is the gate-drain capacitance Cgd, input capacitance ciss=cgd (gate-drain capacitance) +cgs (gate-source capacitance), and output capacitance coss=cgd (gate-drain capacitance) +cds (source-drain capacitance). The abscissa of fig. 4-7 represents the voltage applied to the source and drain of the MOSFET device.
Assuming that the first conductivity type pillars and the second conductivity type pillars in example 1 have a one-to-one correspondence in concentration and dimension, the body doping concentration and the source doping concentration are the same, wherein 500, 600, 700, 800 are respectively the Ciss/Coss/Crss/Cgs curves of the trench gate structure in comparative example, and 501, 601, 701, 801 are respectively the Ciss/Coss/Crss/Cgs curves of the trench gate structure in example 2, it can be understood that the capacitance value of Ciss of the curve 501 is smaller than that of the trench gate structure curve 500 in comparative example with an increase in voltage, and the decrease percentage is 33.
The capacitance value of Coss of curve 601 is comparable to that of the trench gate structure curve 600 in the comparative example as the voltage increases.
The capacitance value of Crss of curve 701 decreases and then tends to agree with the capacitance value of Crss of trench gate structure curve 700 in the comparative example as the voltage increases.
The capacitance value of Cgs of curve 801 increases with voltage much less than that of the trench gate structure curve 800 in the comparative example, which decreases by about a factor of two.
From the above, the structure in embodiment 1 of the present invention can reduce the capacitance value of the input capacitor Ciss, thereby adjusting the switching speed of the device, reducing the switching loss of the device, and increasing the frequency of the device.
The application reduces the actual channel density by adjusting the positions of the integral region and the source region injection region, and can lead to the increase of the channel resistance. However, since the channel resistance occupies a relatively small area in the on-resistance of the device, the application can ensure that the increase of the on-resistance is less than or equal to 5% compared with the increase of the comparative example.
However, due to the fact that the actual channel density is reduced, compared with a device structure in a comparative example, the input capacitance of the super junction device is reduced by at least 33%, the gate-source capacitance is reduced by one time, and the balance between the on-resistance and the input capacitance is well achieved, so that the switching speed of the super junction device is improved, the switching loss of the super junction device is reduced, and the frequency of the device is improved.
It is to be understood that the above examples only represent preferred embodiments of the present invention, which are described in more detail and are not to be construed as limiting the scope of the invention; it should be noted that, for a person skilled in the art, the above technical features can be freely combined, and several variations and modifications can be made without departing from the scope of the invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. The trench gate superjunction device for reducing the input capacitance is characterized by comprising a superjunction structure charge balance region, wherein the superjunction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed, the tops of the first conductive type columns are provided with trench gates, one side, close to the second conductive type columns, of each trench gate is provided with a body region, and the tops of the body regions are provided with active regions; the source region is connected to the source metal through a source contact hole.
2. The trench gate superjunction device for reducing input capacitance of claim 1, wherein the bottom of the charge balance region of the superjunction structure is sequentially connected with a first conductivity type buffer layer and a first conductivity type substrate, and the doping concentration of the first conductivity type buffer layer is smaller than the doping concentration of the first conductivity type substrate.
3. The trench-gate superjunction device for reducing input capacitance of claim 2, wherein the total thickness of said superjunction structure charge balance region and said first conductivity type buffer layer is less than 55 microns.
4. The trench-gate superjunction device for reducing input capacitance of claim 1, wherein the width of said first conductivity type pillars is greater than the width of said second conductivity type pillars in the direction in which the first conductivity type pillars and second conductivity type pillars are alternately arranged; and the doping concentration of the first conductivity type column is smaller than the doping concentration of the second conductivity type column.
5. The trench gate superjunction device for reducing input capacitance of claim 1, wherein the trench gate comprises a gate dielectric layer and a gate electrode, a filling groove is arranged at the top of the first conductive type column, and the filling groove is filled with the gate dielectric layer and the gate electrode in sequence.
6. The trench-gate superjunction device for reducing input capacitance of claim 5, wherein the bottom of said filled recess is lower than the bottom of said body region.
7. The trench-gate superjunction device for reducing input capacitance of claim 1, wherein an isolation layer is provided on top of the superjunction structure charge balance region, the source metal is located on top of the isolation layer, and the source contact hole penetrates through the isolation layer and extends into the superjunction structure charge balance region.
8. The trench-gate superjunction device for reducing input capacitance of claim 7, wherein said source contact is in a column of first conductivity type, and said source contact is on a side of said source region remote from the trench gate, wherein the doping concentration at the bottom of said source contact is greater than the doping concentration of the source region, and wherein said source metal is connected to the source region through the source contact.
9. The trench-gate superjunction device for reducing input capacitance of claim 8, wherein said source contact is further located within a second conductivity type pillar, and said source contact is located at a center of said second conductivity type pillar, and wherein a doping concentration at a bottom of said source contact is greater than a doping concentration of said body region.
10. The preparation method of the trench gate superjunction device for reducing the input capacitance is characterized by comprising the following steps of:
Forming a super junction structure charge balance region on the surface of the first conductive type substrate, wherein the super junction structure charge balance region comprises first conductive type columns and second conductive type columns which are alternately distributed;
forming a body region on one side of the trench gate in the first conductive type column through an ion implantation push-well process;
etching the top of the first conductive type column to form a filling groove, and filling a groove gate in the filling groove;
Doping the heavily doped region of the first conductivity type in the body region by a polysilicon self-alignment process to form a source region; the source region is positioned in the body region in the first conductive type column, and the source region is positioned near one side of the second conductive type column;
Etching a source electrode contact hole in the top of the charge balance region and the body region of the super junction structure;
filling source metal, wherein the source region is connected to the source metal through a source contact hole;
And forming a drain electrode on the back surface of the first conductive type substrate.
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