CN116995089A - Super-junction carrier storage type IGBT device and manufacturing method thereof - Google Patents
Super-junction carrier storage type IGBT device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a super junction carrier storage type IGBT device, which comprises: the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer are sequentially overlapped. Forming a super junction structure in the second N-type epitaxial layer; the N-type pillars serve as carrier storage layers. A body region is formed in a top region of the third N-type epitaxial layer and has a spacing from the P-type pillar. The super junction structure is a buried layer structure inserted into the drift region so as to realize independent arrangement of the thickness and the longitudinal position of the carrier storage layer; the thickness and longitudinal position of the carrier storage layer are set according to the current capability required when the IGBT device is turned on in the forward direction. And in the reverse bias process, the super junction structure is used for exhausting the carrier storage layer so as to improve the first withstand voltage of the carrier storage layer. The invention discloses a manufacturing method of a super-junction carrier storage type IGBT device. The invention can improve the forward current conducting capability of the device, can independently adjust the reverse voltage withstanding capability and the forward current conducting capability of the device, and can also reduce the process cost.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and in particular, to a Super Junction (SJ) Carrier Storage (CS) insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) device. The invention also relates to a manufacturing method of the super-junction carrier storage type IGBT device.
Background
IGBTs are voltage controlled MOS and bipolar composite devices that have the main advantages of both bipolar junction power transistors and power MOSFETs: the IGBT becomes one of important switching components for controlling and converting the energy of the power electronic system, and the performance of the IGBT directly influences the conversion efficiency, volume and weight of the power electronic system.
The IGBT structure is very similar to the VDMOS structure, and an N+ doped drain region is changed into a P+ doped collector region on the basis of the VDMOS structure, and holes can be injected into a drift region by the collector region, so that conductivity modulation can be realized on the drift region, the on-state voltage drop of the device can be reduced, and the current density of the device can be improved.
And setting a super-junction structure in a drift region of the IGBT device to obtain a super-junction IGBT (SJ-IGBT) device. The SJ-IGBT utilizes the SJ and IGBT process capability, combines the characteristics of two devices, can greatly improve the forward conduction performance of the devices and greatly increase the power density of the devices.
As shown in fig. 1, the structure of the prior art super-junction IGBT device is schematically shown; the prior first super junction IGBT device comprises:
The super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns 209, and one N-type column and one adjacent P-type column 209 form a corresponding super junction unit.
The super junction structure is formed in a first N-type epitaxial layer 202, a P-type doped collector region 201 is formed at the bottom of the first N-type epitaxial layer 202, and the back surface of the collector region 201 is connected with a collector consisting of a back metal layer.
The P-type pillars 209 are composed of a P-type epitaxial layer filled in super junction trenches formed in the first N-type epitaxial layer 202, and the N-type pillars are composed of the first N-type epitaxial layer 202 between the P-type pillars 209.
The first N-type epitaxial layer 202 is formed on a surface of a semiconductor substrate (not shown). The semiconductor substrate is removed in a backside thinning process and is not shown in fig. 1.
The bottom of the P-type pillars 209 and the top surface of the collector region 201 have a spacing.
A top N-type epitaxial layer 208 is formed on top of the superjunction structure.
In the device cell region 201a, a device cell structure of an IGBT device formed by connecting a plurality of the device cell structures in parallel is formed in the top N-type epitaxial layer 208 of the top region of each of the superjunction cells.
The device cell structure includes:
a P-doped body region 206, the body region 206 being formed in a surface region of the top N-type epitaxial layer 208.
A trench gate, which is composed of a gate dielectric layer 204 and a gate conductive material layer 205 filled in a gate trench 203, the gate trench 203 is located in a top region of the N-type pillar and the gate trench 203 passes through the body region 206.
The surface of the body region 206 covered by the trench gate sides is used to form a channel; the drift region is comprised of the first N-type epitaxial layer 202 and the top N-type epitaxial layer 208 at the bottom of the body region 206.
An emitter region 207 consisting of an n+ region is formed on the surface of the body region 206 at the side of the trench gate.
A first contact hole 211 is formed at the top of the emitter region 207, the bottom of the first contact hole 211 simultaneously contacts the emitter region 207 and the body region 206, and the top of the first contact hole 211 is connected to an emitter composed of a front metal layer 212.
An N-doped electric field stop layer 214 is formed in the first N-type epitaxial layer 202 on the front surface of the collector region 201, the doping concentration of the electric field stop layer 214 is greater than that of the first N-type epitaxial layer 202, and a space is provided between the top surface of the electric field stop layer 214 and the bottom surface of the P-type pillar 209.
The trench gate also extends into a gate lead-out region 201b, in which gate lead-out region 201b a second contact hole (not shown) is formed on top of the gate conductive material layer 205, the top of which is connected to a gate electrode composed of a front side metal layer 212.
A passivation layer 213 is further formed on the surface of the front metal layer 212.
The first contact hole 211 and the second contact hole pass through the interlayer film 210.
Typically, the collector region 201 is formed by a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 202 after the back surface of the semiconductor substrate is thinned.
As shown in fig. 2, the structure of the conventional second super-junction IGBT device is schematically shown; the existing second super-junction IGBT device comprises:
the super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns 309, and one N-type column and one adjacent P-type column 309 form a corresponding super junction unit.
The super junction structure is formed in a first N-type epitaxial layer 302, a P-type doped collector region 301 is formed at the bottom of the first N-type epitaxial layer 302, and the back surface of the collector region 301 is connected with a collector consisting of a back metal layer.
The P-type pillars 309 are composed of a P-type epitaxial layer filled in super junction trenches formed in the first N-type epitaxial layer 302, and the N-type pillars are composed of the first N-type epitaxial layer 302 between the P-type pillars 309.
The first N-type epitaxial layer 302 is formed on a surface of a semiconductor substrate (not shown). The semiconductor substrate is removed in a backside thinning process and is not shown in fig. 2.
The bottom of the P-type pillars 309 and the top surface of the collector region 301 have a spacing.
In the device unit area, a device unit structure of an IGBT device is formed in the top area of each super-junction unit, and the IGBT device is formed by connecting a plurality of device unit structures in parallel.
The device cell structure includes:
a P-doped body region 306, the body region 306 being formed in the top region of the superjunction cell, i.e. in the top regions of the N-type and P-type pillars 309.
The trench gate is composed of a gate dielectric layer 304 and a gate conductive material layer 305 filled in the gate trench 303. The gate trench 303 is located in the top region of the N-type pillar and the gate trench 303 passes through the body region 306.
The surface of the body region 306 covered by the trench gate sides is used to form a channel; the drift region is comprised of the first N-type epitaxial layer 302 at the bottom of the body region 306.
Two of the gate trenches 303 are formed in the top region of the same N-type pillar.
An emitter region 307 consisting of an n+ region is formed on the surface of the body region 306 at the second side of the trench gate.
A first contact hole 311 is formed at the top of the emitter region 307, the bottom of the first contact hole 311 simultaneously contacts the emitter region 307 and the body region 306, and the top of the first contact hole 311 is connected to an emitter composed of a front metal layer 312.
The body region 306 at the bottom of the first contact hole 311 is also formed with a body extraction region 308 composed of a p+ region.
As can be seen from fig. 2, the P-type pillar 309 is located outside the first side of the trench gate, and the conductive path between the P-type pillar 309 and the second side of the trench gate, the emitter region 307, the first contact hole 311 and the emitter electrode is broken by the trench gate, since the first side and the second side of the trench gate are electrically isolated.
An N-doped electric field stop layer 314 is formed in the first N-type epitaxial layer 302 on the front surface of the collector region 301, the doping concentration of the electric field stop layer 314 is greater than that of the first N-type epitaxial layer 302, and a space is provided between the top surface of the electric field stop layer 314 and the bottom surface of the P-type column 309.
A passivation layer 313 is also formed on the surface of the front side metal layer 312.
The first contact hole 311 and the second contact hole pass through the interlayer film 310.
Typically, the collector region 301 is formed by a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 302 after the back surface of the semiconductor substrate is thinned.
The existing super-junction IGBT device can improve the withstand voltage of the drift region by introducing the super-junction structure, so that the N-type doping concentration of the drift region can be improved, but in practice, the forward current-conducting capacity of the device cannot be improved due to the improvement of the N-type doping concentration of the drift region, so that the forward performance of the device is limited.
As shown in fig. 3, the structure of the existing carrier storage type IGBT device is schematically shown; the existing carrier storage type IGBT device includes:
a first N-type epitaxial layer 402 is formed on a surface of a semiconductor substrate (not shown). A collector region 401 doped with P-type is formed at the bottom of the first N-type epitaxial layer 402, and the back surface of the collector region 401 is connected with a collector consisting of a back metal layer. Typically, the collector region 401 is formed by a P-doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 402 after the back surface of the semiconductor substrate is thinned. The semiconductor substrate is removed in the back side thinning process and is not shown in fig. 4.
In the device cell region 401a, a device cell structure of an IGBT device is formed on the surface of the first N-type epitaxial layer 402, and the IGBT device is formed by connecting a plurality of the device cell structures in parallel.
The device cell structure includes:
a P-doped body region 406, the body region 406 being formed in a surface region of the first N-type epitaxial layer 402.
An N-doped carrier storage layer 409 is further formed in the first N-type epitaxial layer 402 at the bottom of the body region 406, where the doping concentration of the carrier storage layer 409 is greater than the doping concentration of the first N-type epitaxial layer 402.
The first N-type epitaxial layer 402 at the bottom of the carrier storage layer 409 constitutes a drift region.
A trench gate, which is composed of a gate dielectric layer 404 and a gate conductive material layer 405 filled in a gate trench 403, the gate trench 403 being located in a top region of the N-type pillar and the gate trench 403 passing through the body region 406.
The surface of the body region 406 covered by the trench gate sides is used to form a channel.
An emitter region 407 consisting of an n+ region is formed on the surface of the body region 406 at the side of the trench gate.
A first contact hole 411 penetrating the interlayer film 410 is formed at the top of the emission region 407, the bottom of the first contact hole 411 simultaneously contacts the emission region 407 and the body region 406, and the top of the first contact hole 411 is connected to an emitter composed of a front metal layer 412.
The body region 406 at the bottom of the first contact hole 411 is also formed with a body extraction region 408 composed of a p+ region.
An N-doped electric field stop layer 414 is formed in the first N-type epitaxial layer 402 on the front surface of the collector region 401, the doping concentration of the electric field stop layer 414 is greater than that of the first N-type epitaxial layer 402, and a space is provided between the top surface of the electric field stop layer 414 and the bottom surface of the P-type pillar 409.
A passivation layer 413 is further formed on the surface of the front metal layer 412.
The first contact hole 411 and the second contact hole pass through the interlayer film 410.
In fig. 3, the doping concentration of the carrier storage layer 409 is greater than that of the first N-type epitaxial layer 402, so that the hole carrier concentration in the whole drift region can be increased after the carrier storage layer 409 is disposed, and finally the forward conductivity of the device can be improved.
As shown in fig. 4, the structure of the existing super-junction carrier storage type IGBT device is schematic; fig. 4 is fig. 5B disclosed in the previous application No. CN202310383628.3 by the applicant, in fig. 4, a carrier storage layer 109 is formed in the top region of the first N-type semiconductor layer 102, and the N-type doping concentration of the carrier storage layer 109 is greater than that of the first N-type semiconductor layer 102. The carrier storage layer 109 is located only in the device cell region. A plurality of P-type pillars 115 are formed in the carrier storage layer 109, the carrier storage layer 109 between the P-type pillars 115 forms an N-type pillar, the P-type pillars 115 and the N-type pillars are alternately arranged to form a superjunction structure, and one N-type pillar and an adjacent P-type pillar 115 form a corresponding superjunction unit.
The thickness of the superjunction structure is determined by the thickness of the carrier storage layer 109, and the thickness of the carrier storage layer 109 is set according to the current capability required when the IGBT device is turned on in the forward direction.
The device unit structure of the IGBT device comprises: a P-doped body region 106, a gate structure, and an N + doped emitter region 107.
The body region 106 is formed in a surface region of the N-type pillar.
The surface of the body region 106 covered by the gate structure serves as a channel region.
The emitter region 107 is formed on the surface of the body region 106.
The N-type pillars at the bottom of the body region 106 constitute a carrier storage layer 109.
The gate structure adopts a trench gate, the trench gate is composed of a gate dielectric layer 104 and a gate conductive material layer 105 filled in a gate trench 103, the gate trench 103 is located in a top region of the N-type pillar, the gate trench 103 passes through the body region 106 and a bottom surface of the gate trench 103 is located in the carrier storage layer.
The top of the emitter region 107 is connected to an emitter consisting of a front side metal layer 112 through a first contact hole 111 passing through an interlayer film 110. A passivation layer 113 is further covered on the surface of the front metal layer 112.
The bottom of the first contact hole 111 also contacts the body region 106. The body region 106 at the bottom of the first contact hole 111 is further formed with a body extraction region 108 composed of a p+ region on the surface thereof.
An electrical isolation structure is provided between the P-type pillar 115 and the body region 106, which electrically isolates the P-type pillar 115 from the emitter via the body region 106. The electric isolation structure is realized by adopting the trench gate.
Two trench gates are formed in the top region of the N-type pillar, the emitter region 107 being self-aligned to the surface of the body region 106 formed between the second sides of the two trench gates; the P-type pillars 115, the body region 106 between the P-type pillars 115 to the first side of the trench gate, are electrically isolated by the body region 106 between the trench gate and the second sides of both the trench gates.
A p+ doped collector region 101 is formed on the back surface of the first N-type semiconductor layer 102.
The first N-type semiconductor layer 102 at the bottom of the carrier storage layer 109 serves as a drift region.
When the IGBT device is reverse biased, the superjunction structure is configured to deplete the carrier storage layer 109 to raise a first withstand voltage of the carrier storage layer 109, and a total withstand voltage of the IGBT device is a sum of the first withstand voltage of the carrier storage layer 109 and a second withstand voltage of the drift region, so that a thickness of the superjunction structure and the total withstand voltage of the IGBT device are independent.
An N-doped electric field stop layer 114 is formed in the first N-type semiconductor layer 102 on the front surface of the collector region 101, and the doping concentration of the electric field stop layer 114 is greater than that of the first N-type semiconductor layer 102.
In the structure shown in fig. 4, compared with the structure shown in fig. 2, the superjunction structure is provided only in the carrier storage layer, so that the thickness of the superjunction structure can be reduced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the super-junction carrier storage type IGBT device, which can avoid adverse effects on the forward current conducting capacity of the device when the super-junction structure is adopted to improve the withstand voltage of the device, so that the forward current conducting capacity of the device can be improved to the maximum extent by utilizing the super-junction structure, the reverse withstand voltage and the forward current conducting capacity of the device can be independently regulated, and the process cost can be reduced. The invention further provides a manufacturing method of the super-junction carrier storage type IGBT device.
In order to solve the above technical problems, the super-junction carrier storage type IGBT device provided by the present invention includes: the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer are sequentially overlapped.
And forming a plurality of P-type columns in the second N-type epitaxial layer, forming N-type columns by the second N-type epitaxial layer between the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure.
The doping concentration of the N-type column is greater than that of the first N-type epitaxial layer at the bottom and the doping concentration of the N-type column is greater than that of the third N-type epitaxial layer at the top; the N-type column serves as a carrier storage layer.
And a collector region doped with P type is formed at the bottom of the first N-type epitaxial layer.
The front structure of the device unit structure of the IGBT device comprises: a P-doped body region, a gate structure, and an n+ doped emitter region.
The body region is formed in the top region of the third N-type epitaxial layer, the surface of the body region covered by the gate structure is used for forming a channel, and the emitter region is formed on the surface of the body region and is self-aligned with the gate structure.
And the third N-type epitaxial layer, the N-type column and the first N-type epitaxial layer which are positioned in the body region and the collector region form a drift region.
And a space is arranged between the body region and the P-type column, so that the P-type column is in a floating structure.
The super junction structure is a buried layer structure inserted into the drift region, and the buried layer structure is utilized to realize independent arrangement of the thickness and the longitudinal position of the carrier storage layer; the thickness and longitudinal position of the carrier storage layer are set according to the current capability required by the forward conduction of the IGBT device.
When the IGBT device is reversely biased, the super junction structure is used for exhausting the carrier storage layer to improve the first withstand voltage of the carrier storage layer, the sum of the withstand voltages of the first N-type epitaxial layer and the third N-type epitaxial layer in the drift region is a second withstand voltage, and the total withstand voltage of the IGBT device is the sum of the first withstand voltage and the second withstand voltage, so that the thickness of the super junction structure and the total withstand voltage of the IGBT device are independent.
A further improvement is that the range of values of the longitudinal position of the carrier storage layer includes 5-40 microns below the top surface of the drift region.
The further improvement is that the P-type column is composed of a P-type ion implantation region implanted into the second N-type epitaxial layer; or, the P-type column is composed of a P-type epitaxial layer filled in a superjunction trench formed in the second N-type epitaxial layer.
The further improvement is that the gate structure adopts a trench gate, the trench gate consists of a gate dielectric layer and a gate conductive material layer which are filled in a gate trench, and the gate trench penetrates through the body region; and the side surface of the trench gate covers the body region.
In a further improvement, an n+ doped field stop layer is formed on the back surface of the first N-type epitaxial layer, and the top surface of the collector region is in contact with the bottom surface of the field stop layer.
A further improvement is that a collector consisting of a backside metal layer is formed on the backside of the collector region.
The top of the emitting region is connected to an emitter consisting of a front metal layer through a contact hole, and the contact hole at the top of the emitting region is also in contact with the body region.
The top of the gate structure is connected to a gate electrode composed of a front metal layer through a contact hole.
In a further improvement, a body extraction region consisting of a P+ region is also formed on the surface of the body region at the bottom of the contact hole at the top of the emission region.
In order to solve the technical problems, the manufacturing method of the super-junction carrier storage type IGBT device provided by the invention comprises the following steps:
forming a second N-type epitaxial layer on the top surface of the first N-type epitaxial layer, wherein the doping concentration of the second N-type epitaxial layer is larger than that of the first N-type epitaxial layer, the second N-type epitaxial layer is used as a carrier storage layer, and the longitudinal position and the thickness of the carrier storage layer are set according to the current capability required by forward conduction of the IGBT device;
Forming a plurality of P-type columns in the second N-type epitaxial layer, forming N-type columns by the second N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure;
forming a third N-type epitaxial layer on the surface of the second N-type epitaxial layer formed with the super junction structure, enabling the super junction structure to be a buried layer structure, and independently setting the thickness and the longitudinal position of the carrier storage layer by utilizing the buried layer structure; the doping concentration of the third N-type epitaxial layer is smaller than that of the second N-type epitaxial layer.
Step four, performing a front process to form a front structure of each device unit structure of the IGBT device, wherein the front structure comprises:
a P-doped body region is formed in a top region of the third N-type epitaxial layer.
And forming a gate structure, wherein the surface of the body region covered by the gate structure is used for forming a channel.
And forming an N+ doped emission region on the surface of the body region, wherein the emission region and the gate structure are self-aligned.
Step five, carrying out a back process, which comprises the following steps:
and performing a back thinning process, wherein the thickness of the first N-type epitaxial layer is thinned after the back thinning process.
And performing P-type back ion implantation to form a collector region on the back of the thinned first N-type epitaxial layer.
And the third N-type epitaxial layer, the N-type column and the first N-type epitaxial layer which are positioned in the body region and the collector region form a drift region.
And a space is arranged between the body region and the P-type column, so that the P-type column is in a floating structure.
When the IGBT device is reversely biased, the super junction structure is used for exhausting the carrier storage layer to improve the first withstand voltage of the carrier storage layer, the sum of the withstand voltages of the first N-type epitaxial layer and the third N-type epitaxial layer in the drift region is a second withstand voltage, and the total withstand voltage of the IGBT device is the sum of the first withstand voltage and the second withstand voltage, so that the thickness of the super junction structure and the total withstand voltage of the IGBT device are independent.
A further improvement is that the range of values of the longitudinal position of the carrier storage layer includes 5-40 microns below the top surface of the drift region.
In the second step, a photoetching definition and P-type ion implantation process is adopted to form the P-type column in the second N-type epitaxial layer.
Or in the second step, a super-junction groove is formed in the second N-type epitaxial layer by adopting a photoetching definition etching process, and then a P-type epitaxial layer is filled in the super-junction groove to form the P-type column.
In a fourth step, the gate structure adopts a trench gate, and the forming step includes:
forming a gate trench, the gate trench passing through the body region; and the side surface of the trench gate covers the body region.
And forming a gate dielectric layer on the inner side surface of the gate trench.
And filling a gate conductive material layer in the gate trench.
In a further improvement, in the fifth step, the method further includes:
performing N+ back ion implantation after the back thinning process to form a field stop layer on the back of the thinned first N-type epitaxial layer; a top surface of the collector region is in contact with a bottom surface of the field stop layer.
In a further improvement, in the fourth step, the front-side process further includes:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form an emitter and a grid.
The top of the emitting region is connected to an emitter consisting of a front metal layer through a contact hole, and the contact hole at the top of the emitting region is also in contact with the body region; the top of the gate structure is connected to a gate electrode composed of a front metal layer through a contact hole.
In a further improvement, the forming process of the contact hole comprises the following steps:
Forming an opening of the contact hole;
p+ ion implantation is carried out at the bottom of the opening of the contact hole at the top of the emission region, and a body leading-out region is formed;
and filling a metal layer in the opening of the contact hole.
In a further improvement, in the fifth step, the method further includes:
and forming a back metal layer on the back surface of the collector region, and forming a collector by the back metal layer.
Unlike the existing structure that adopts the superjunction structure to improve the reverse withstand voltage of the IGBT device and thus improve the doping concentration of the drift region to improve the forward current conduction capability of the device, aiming at the defect that when the superjunction structure in the existing structure is adopted to improve the N-type doping concentration of the drift region, the whole drift region is actually used as a carrier storage layer at the same time, so that the hole carrier concentration of the drift region is reduced and the forward current conduction capability of the device cannot be further improved;
meanwhile, unlike the top surface of the epitaxial layer corresponding to the drift region, which is extended all the way to the top surface of the epitaxial layer corresponding to the drift region, the super junction structure is provided with the buried layer structure, so that the position of the super junction structure in the drift region can be independently adjusted, namely independent of the top surface of the epitaxial layer corresponding to the drift region, the thickness and the longitudinal position of the carrier storage layer can be independently adjusted, when the longitudinal position of the carrier storage layer is set, the thickness setting of the carrier storage layer is not influenced, and the longitudinal position and the thickness of the carrier storage layer can be simultaneously set according to the requirement of improving the hole carrier concentration in the drift region, and meanwhile, the longitudinal position and the thickness optimization of the carrier storage layer can be realized, so that the forward current conducting capacity of the device is further improved.
The invention can also reduce the process cost because:
after the position of the carrier storage layer is determined, according to the existing process of the superjunction structure, the superjunction structure needs to be extended from the position of the carrier storage layer to the top surface of the epitaxial layer corresponding to the drift region, so that the thickness of the superjunction structure is obviously greatly increased; in the invention, after the longitudinal position of the carrier storage layer is determined, the thickness of the carrier storage layer at the selected position can be determined at the same time, so that the thickness of the carrier storage layer cannot be changed due to the change of the position, and the thickness of the superjunction structure cannot be increased after the position of the carrier storage layer is deeper; those skilled in the art know that the thicker the super junction structure is, the higher the manufacturing cost is, so the thickness of the super junction structure can be reduced, and the process cost can be reduced.
In addition, the reverse total voltage resistance of the device can be regulated by setting the thickness and doping concentration of the drift region in the first N-type epitaxial layer and the third N-type epitaxial layer on the basis of the first voltage resistance of the super-junction structure, and finally, the second voltage resistance of the drift region in the first N-type epitaxial layer and the third N-type epitaxial layer and the first voltage resistance of the super-junction structure can meet the requirement of the reverse total voltage resistance of the device; therefore, the invention can improve the voltage-resistant capability of the device at the same time, and improve the forward current conduction capability of the device at the same time, and can easily obtain the optimal forward current conduction capability of the device; in addition, the second withstand voltage is easy to meet because the N-type doping concentration of the drift region is very light, and the concentrations of the first N-type epitaxial layer and the third N-type epitaxial layer can be set completely according to the conventional arrangement of the voltage class corresponding to the conventional IGBT.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic structural diagram of a conventional first superjunction IGBT device;
fig. 2 is a schematic structural diagram of a second conventional superjunction IGBT device;
fig. 3 is a schematic structural diagram of a conventional carrier storage type IGBT device;
fig. 4 is a schematic structural diagram of a conventional super junction carrier storage type IGBT device;
fig. 5 is an energy band diagram of a conventional superjunction carrier storage type IGBT device;
fig. 6 is a hole concentration distribution curve in a drift region when the super junction structure positions of the existing super junction carrier storage type IGBT device are different;
fig. 7 is a schematic structural diagram of an superjunction carrier storage type IGBT device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a super junction carrier storage type IGBT device according to an embodiment of the present invention after forming a third N type epitaxial layer;
fig. 9 is a simulation diagram of transfer characteristic curves of the superjunction carrier storage type IGBT device according to the embodiment of the present invention and the device shown in fig. 4.
Detailed Description
In describing in detail the superjunction carrier storage type IGBT device according to the embodiment of the present invention, the principle of increasing carrier concentration and the problems of the conventional superjunction carrier storage type IGBT device shown in fig. 4 are described as follows:
As shown in fig. 5, the energy band diagram of the existing super junction carrier storage type IGBT device; the energy band diagram includes 3 regions, where region 501 corresponds to the energy band of channel region 106 in fig. 4, region 502 corresponds to the energy band of n+ doped carrier storage layer 109, region 503 corresponds to the energy band of first N-type epitaxial layer 102 at the bottom of carrier storage layer 109, and the fermi level E of the 3 regions when the device is not energized F Is leveled, and the conduction band bottom E is due to the higher doping concentration of the carrier storage layer 109 C Will be closer to fermi level E F Valence band apex E V Distance fermi level E F Farther away; therefore, in the direction from region 503 to 502, valence band peak E V And a conduction band bottom E C Are concave but for holes the valence band peak E V The recessing forms a barrier to holes, thereby enabling blocking of holes, which increases the hole concentration in region 503, thereby increasing the forward conductivity of the device.
In FIG. 5, valence band roofE V The height of the potential barrier formed by the recess is determined by the doping concentration of the carrier storage layer 109, and the position and the height of the potential barrier are very important, and when the thickness reaches a certain value, the meaning of thickening the carrier storage layer 109 again becomes smaller.
As shown in fig. 6, the hole concentration distribution curve in the drift region is obtained when the super junction structure of the existing super junction carrier storage type IGBT device is different in position; the superjunction structure location refers to the bottom location of the superjunction structure, which corresponds to the location at the potential barrier to holes in FIG. 5, i.e., the valence band ceiling E in virtual coil 504 V The right side of the recess. The curves of fig. 6 are simulation curves showing the hole concentration distribution corresponding to a plurality of different barrier positions, and the 7 hole concentration peak positions corresponding to the marks 505a, 505b to 505g correspond to the 7 barrier positions, and it is known that the arrangement of the barrier positions is very critical to the current lifting effect.
However, as shown in fig. 4, the barrier position corresponds to the bottom surface position of the carrier storage layer 109, and since the top surface position of the carrier storage layer 109 is fixed, i.e., is level with the top surface of the first N-type semiconductor layer 102, the thickness of the entire carrier storage layer 109 is adjusted after adjusting the bottom surface of the carrier storage layer 109; when the thickness of the carrier storage layer 109 is fixed, the bottom surface position of the carrier storage layer 109 cannot be adjusted, which cannot adjust the on-current capability of the device by adjusting the barrier position.
In addition, when the bottom surface of the carrier storage layer 109 is deeper, the thickness of the carrier storage layer 109 is also increased, which increases the thickness of the superjunction structure, and since the thicker the superjunction structure is, the higher the manufacturing cost is, and therefore, the manufacturing cost is increased.
The embodiment of the invention provides a super-junction carrier storage type IGBT device:
fig. 7 is a schematic structural diagram of an IGBT device according to an embodiment of the present invention; the super-junction carrier storage type IGBT device of the embodiment of the invention comprises: the first N-type epitaxial layer 1a, the second N-type epitaxial layer 1b, and the third N-type epitaxial layer 1c are stacked in this order.
A plurality of P-type columns 2 are formed in the second N-type epitaxial layer 1b, N-type columns are formed by the second N-type epitaxial layer 1b between the P-type columns 2, and super junction structures are formed by alternately arranging the P-type columns 2 and the N-type columns.
In the embodiment of the present invention, the P-type column 2 is formed by a P-type ion implantation region implanted into the second N-type epitaxial layer 1 b. In other embodiments can also be: the P-type column 2 is composed of a P-type epitaxial layer filled in a superjunction trench formed in the second N-type epitaxial layer 1 b.
The doping concentration of the N-type column is greater than that of the first N-type epitaxial layer 1a at the bottom and the doping concentration of the N-type column is greater than that of the third N-type epitaxial layer 1c at the top; the N-type column serves as a carrier storage layer.
A collector region 13 doped with P-type is formed at the bottom of the first N-type epitaxial layer 1 a.
The front structure of the device unit structure of the IGBT device comprises: a P-doped body region 3, a gate structure and an N + doped emitter region 6.
The body region 3 is formed in the top region of the third N-type epitaxial layer 1c, the surface of the body region 3 covered by the gate structure is used to form a channel, and the emitter region 6 is formed on the surface of the body region 3 and is self-aligned with the gate structure.
The third N-type epitaxial layer 1c, the N-type pillars and the first N-type epitaxial layer 1a located in the body region 3 and the collector region 13 constitute a drift region.
The body region 3 and the P-type column 2 are spaced apart and the P-type column 2 is in an floating structure.
In the embodiment of the invention, the gate structure adopts a trench gate, the trench gate consists of a gate dielectric layer 4 and a gate conductive material layer 5 which are filled in a gate trench, and the gate trench passes through the body region 3; the trench gate sides cover the body region 3. In some embodiments, the gate dielectric layer 4 includes a gate oxide layer; the gate conductive material layer 5 comprises a polysilicon gate.
In fig. 3, the emitter region 6 is not provided between the trench gates on top of the P-type pillars 2, thereby further ensuring electrical isolation between the body region 3 and the P-type pillars 2. However, since there is a space between the body region 3 and the P-type pillar 2, in other modified embodiments, the emitter region 6 can also be provided between the trench gates on top of the P-type pillar 2.
The super junction structure is a buried layer structure inserted into the drift region, and the buried layer structure is utilized to realize independent arrangement of the thickness and the longitudinal position of the carrier storage layer; the thickness and longitudinal position of the carrier storage layer are set according to the current capability required by the forward conduction of the IGBT device.
In the present application, the longitudinal position of the carrier storage layer corresponds to the bottom surface position of the carrier storage layer, which corresponds to the blocking surface position corresponding to the hole barrier. In the embodiment of the application, the longitudinal position range of the carrier storage layer comprises 5-40 micrometers below the top surface of the drift region. In the conventional structure corresponding to fig. 4, after the longitudinal position of the carrier storage layer is determined, the thickness of the carrier storage layer is determined, that is, the distance from the longitudinal position of the carrier storage layer to the top surface of the entire epitaxial layer. In the embodiment of the application, the thickness of the carrier storage layer can be further reduced according to the requirement of forward current conduction, so that the forward current conduction capability of the device can be improved, and the process cost can be further reduced.
When the IGBT device is reverse biased, the superjunction structure is configured to deplete the carrier storage layer to raise a first withstand voltage of the carrier storage layer, a sum of withstand voltages of the first N-type epitaxial layer 1a and the third N-type epitaxial layer 1c in the drift region is a second withstand voltage, and a total withstand voltage of the IGBT device is a sum of the first withstand voltage and the second withstand voltage, so that a thickness of the superjunction structure and the total withstand voltage of the IGBT device are independent.
In the embodiment of the present invention, an n+ doped field stop layer 12 is formed on the back surface of the first N-type epitaxial layer 1a, and the top surface of the collector region 13 is in contact with the bottom surface of the field stop layer 12.
A collector composed of a back metal layer is formed on the back surface of the collector region 13.
The top of the emitter region 6 is connected to an emitter consisting of a front metal layer 10 through a contact hole 9 through an interlayer film 8, the contact hole 9 at the top of the emitter region 6 also being in contact with the body region 3. The surface of the body region 3 at the bottom of the contact hole 9 at the top of the emitter region 6 is also formed with a body extraction region 7 composed of a p+ region.
The top of the gate structure is connected to a gate electrode consisting of a front side metal layer 10 through a contact hole 9.
Unlike the prior art that the super junction structure is adopted to improve the reverse withstand voltage of the IGBT device and the doping concentration of the drift region is improved to improve the forward current conduction capability of the device, aiming at the defect that the whole drift region is used as a carrier storage layer at the same time when the N-type doping concentration of the drift region is improved by adopting the super junction structure in the prior art, the hole carrier concentration of the drift region is reduced and the forward current conduction capability of the device cannot be further improved;
meanwhile, unlike the top surface of the epitaxial layer corresponding to the drift region, which is extended all the way to the top surface of the epitaxial layer corresponding to the drift region, the super-junction structure is provided with the buried layer structure, so that the position of the super-junction structure in the drift region can be independently adjusted, namely independent of the top surface of the epitaxial layer corresponding to the drift region, the thickness and the longitudinal position of the carrier storage layer can be independently adjusted, and when the longitudinal position of the carrier storage layer is set, the thickness setting of the carrier storage layer is not influenced, so that the longitudinal position and the thickness of the carrier storage layer can be simultaneously set according to the requirement of improving the hole carrier concentration in the drift region, and the longitudinal position and the thickness of the carrier storage layer are simultaneously optimized, thereby further improving the forward current conducting capability of the device.
The embodiment of the invention can also reduce the process cost because:
after the position of the carrier storage layer is determined, according to the existing process of the superjunction structure, the superjunction structure needs to be extended from the position of the carrier storage layer to the top surface of the epitaxial layer corresponding to the drift region, so that the thickness of the superjunction structure is obviously greatly increased; in the invention, after the longitudinal position of the carrier storage layer is determined, the thickness of the carrier storage layer at the selected position can be determined at the same time, so that the thickness of the carrier storage layer cannot be changed due to the change of the position, and the thickness of the superjunction structure cannot be increased after the position of the carrier storage layer is deeper; those skilled in the art will appreciate that the thicker the superjunction structure, the higher the manufacturing cost, so that the thickness of the superjunction structure can be reduced and the process cost can be reduced.
In addition, the reverse total voltage resistance of the device can be adjusted by setting the thicknesses and doping concentrations of the drift regions in the first N-type epitaxial layer and the third N-type epitaxial layer on the basis of the first voltage resistance of the super-junction structure, and finally the second voltage resistance of the drift regions in the first N-type epitaxial layer and the third N-type epitaxial layer and the first voltage resistance of the super-junction structure can meet the requirement of the reverse total voltage resistance of the device; therefore, the embodiment of the invention can simultaneously improve the voltage-resistant capability of the device, simultaneously improve the forward current conduction capability of the device and easily obtain the optimal forward current conduction capability of the device; in addition, the second withstand voltage is easy to meet because the N-type doping concentration of the drift region is very light, and the concentrations of the first N-type epitaxial layer and the third N-type epitaxial layer can be set completely according to the conventional arrangement of the voltage class corresponding to the conventional IGBT.
The manufacturing method of the super junction carrier storage type IGBT device comprises the following steps:
as shown in fig. 8, a schematic structural diagram of the super junction carrier storage type IGBT device according to the embodiment of the invention after forming the third N-type epitaxial layer 1 c; the manufacturing method of the super junction carrier storage type IGBT device comprises the following steps:
step one, a second N-type epitaxial layer 1b is formed on the top surface of the first N-type epitaxial layer 1a, the doping concentration of the second N-type epitaxial layer 1b is greater than that of the first N-type epitaxial layer 1a, the second N-type epitaxial layer 1b is used as a carrier storage layer, and the longitudinal position and thickness of the carrier storage layer are set according to the current capability required by forward conduction of the IGBT device.
In the method of the embodiment of the invention, the longitudinal position range of the carrier storage layer comprises 5 micrometers-40 micrometers below the top surface of the drift region formed later.
And secondly, forming a plurality of P-type columns 2 in the second N-type epitaxial layer 1b, forming N-type columns by the second N-type epitaxial layer 1b among the P-type columns 2, and alternately arranging the P-type columns 2 and the N-type columns to form a super junction structure.
In the method of the embodiment of the invention, the P-type column 2 is formed in the second N-type epitaxial layer 1b by adopting a photoetching definition and P-type ion implantation process. Other embodiments of the method can also be: the P-type column 2 is formed by forming a superjunction trench in the second N-type epitaxial layer 1b by using a photolithography-defined etching process, and then filling a P-type epitaxial layer in the superjunction trench.
Forming a third N-type epitaxial layer 1c on the surface of the second N-type epitaxial layer 1b with the super junction structure, so that the super junction structure is a buried layer structure, and the buried layer structure is utilized to realize independent arrangement of the thickness and the longitudinal position of the carrier storage layer; the doping concentration of the third N-type epitaxial layer 1c is smaller than the doping concentration of the second N-type epitaxial layer 1 b.
Step four, as shown in fig. 7, performing a front side process to form a front side structure of each device unit structure of the IGBT device, including:
a P-doped body region 3 is formed in the top region of the third N-type epitaxial layer 1 c.
A gate structure is formed and the surface of the body region 3 covered by the gate structure is used to form a channel.
An n+ doped emitter region 6 is formed on the surface of the body region 3, the emitter region 6 and the gate structure being self-aligned.
In the method of the embodiment of the invention, the gate structure adopts a trench gate, and the forming steps comprise:
forming a gate trench, which passes through the body region 3; the trench gate sides cover the body region 3.
And forming a gate dielectric layer 4 on the inner side surface of the gate trench. In some embodiments, the gate dielectric layer 4 is a gate oxide layer.
A layer of gate conductive material 5 is filled in the gate trench. In some example methods, the gate conductive material layer 5 is a polysilicon gate.
The front side process further comprises:
an interlayer film 8, a contact hole 9 and a front metal layer 10 are formed, and the front metal layer 10 is patterned to form an emitter and a gate.
The top of the emitter region 6 is connected to an emitter consisting of a front metal layer 10 through a contact hole 9, the contact hole 9 at the top of the emitter region 6 also being in contact with the body region 3; the top of the gate structure is connected to a gate electrode consisting of a front side metal layer 10 through a contact hole 9.
The process for forming the contact hole 9 comprises the following steps:
forming an opening of the contact hole 9;
p+ ion implantation is carried out at the bottom of the opening of the contact hole 9 at the top of the emitter region 6 and a body extraction region 7 is formed;
And filling a metal layer in the opening of the contact hole 9.
Step five, carrying out a back process, which comprises the following steps:
and performing a back thinning process, wherein the thickness of the first N-type epitaxial layer 1a is thinned after the back thinning process.
And performing P-type back ion implantation to form a collector region 13 on the back surface of the thinned first N-type epitaxial layer 1 a.
The third N-type epitaxial layer 1c, the N-type pillars and the first N-type epitaxial layer 1a located in the body region 3 and the collector region 13 constitute a drift region.
The body region 3 and the P-type column 2 are spaced apart and the P-type column 2 is in an floating structure.
When the IGBT device is reverse biased, the superjunction structure is configured to deplete the carrier storage layer to raise a first withstand voltage of the carrier storage layer, a sum of withstand voltages of the first N-type epitaxial layer 1a and the third N-type epitaxial layer 1c in the drift region is a second withstand voltage, and a total withstand voltage of the IGBT device is a sum of the first withstand voltage and the second withstand voltage, so that a thickness of the superjunction structure and the total withstand voltage of the IGBT device are independent.
In the method of the embodiment of the present invention, in step five, further includes:
performing n+ back ion implantation after the back thinning process to form a field stop layer 12 on the back of the thinned first N-type epitaxial layer 1 a; the top surface of the collector region 13 is in contact with the bottom surface of the field stop layer 12.
Thereafter, the method further comprises:
a back metal layer is formed on the back surface of the collector region 13, and a collector is formed by the back metal layer.
As shown in fig. 9, a simulation diagram of transfer characteristic curves of the superjunction carrier storage IGBT device according to the embodiment of the present invention and the device shown in fig. 4 is shown, in fig. 9, the abscissa voltage is Vge, that is, the gate emitter voltage, the ordinate is Ic, that is, the collector current, curve 601 is the transfer characteristic curve of the device shown in fig. 4, and curve 602 is the transfer characteristic curve of the superjunction carrier storage IGBT device according to the embodiment of the present invention. In the device corresponding to the curve 601, the thickness of the superjunction structure is 15 micrometers; whereas in curve 602 the longitudinal position of the carrier storage layer, i.e. the bottom surface of the superjunction structure, is 15 microns from the top surface position of the drift, the thickness of the superjunction structure is 5 microns. It can be seen that the curves 601 and 602 have little difference, so that the super-junction carrier storage type IGBT device of the embodiment of the invention can also obtain a good forward conduction effect; however, the superjunction structure of the embodiment of the invention has thinner thickness and lower cost.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A superjunction carrier storage type IGBT device, comprising: the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer are sequentially overlapped;
forming a plurality of P-type columns in the second N-type epitaxial layer, forming N-type columns by the second N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure;
the doping concentration of the N-type column is greater than that of the first N-type epitaxial layer at the bottom and the doping concentration of the N-type column is greater than that of the third N-type epitaxial layer at the top; the N-type column is used as a carrier storage layer;
a collector region doped with P type is formed at the bottom of the first N-type epitaxial layer;
the front structure of the device unit structure of the IGBT device comprises: a P-doped body region, a gate structure, and an n+ doped emitter region;
the body region is formed in the top region of the third N-type epitaxial layer, the surface of the body region covered by the gate structure is used for forming a channel, and the emission region is formed on the surface of the body region and is self-aligned with the gate structure;
the third N-type epitaxial layer, the N-type column and the first N-type epitaxial layer which are positioned in the body region and the collector region form a drift region;
A space is arranged between the body region and the P-type column, and the P-type column is in a floating structure;
the super junction structure is a buried layer structure inserted into the drift region, the buried layer structure is utilized to realize independent arrangement of the thickness and the longitudinal position of the carrier storage layer, and the thickness and the longitudinal position of the carrier storage layer are arranged according to the current capability required by forward conduction of the IGBT device;
when the IGBT device is reversely biased, the super junction structure is used for exhausting the carrier storage layer to improve the first withstand voltage of the carrier storage layer, the sum of the withstand voltages of the first N-type epitaxial layer and the third N-type epitaxial layer in the drift region is a second withstand voltage, and the total withstand voltage of the IGBT device is the sum of the first withstand voltage and the second withstand voltage, so that the thickness of the super junction structure and the total withstand voltage of the IGBT device are independent.
2. The superjunction carrier storage IGBT device of claim 1 wherein: the longitudinal position of the carrier storage layer is in a range of 5-40 microns below the top surface of the drift region.
3. The superjunction carrier storage IGBT device of claim 1 wherein: the P-type column is formed by a P-type ion implantation region implanted into the second N-type epitaxial layer; or, the P-type column is composed of a P-type epitaxial layer filled in a superjunction trench formed in the second N-type epitaxial layer.
4. The superjunction carrier storage IGBT device of claim 1 wherein: the gate structure adopts a trench gate, the trench gate consists of a gate dielectric layer and a gate conductive material layer which are filled in a gate trench, and the gate trench penetrates through the body region; and the side surface of the trench gate covers the body region.
5. The superjunction carrier storage IGBT device of claim 1 wherein: and an N+ doped field stop layer is formed on the back surface of the first N-type epitaxial layer, and the top surface of the collector region is in contact with the bottom surface of the field stop layer.
6. The superjunction carrier storage IGBT device of claim 1 wherein: a collector electrode formed by a back metal layer is formed on the back surface of the collector region;
the top of the emitting region is connected to an emitter consisting of a front metal layer through a contact hole, and the contact hole at the top of the emitting region is also in contact with the body region;
the top of the gate structure is connected to a gate electrode composed of a front metal layer through a contact hole.
7. The superjunction carrier storage IGBT device of claim 1 wherein: and a body extraction region consisting of a P+ region is formed on the surface of the body region at the bottom of the contact hole at the top of the emission region.
8. The manufacturing method of the super-junction carrier storage type IGBT device is characterized by comprising the following steps of:
forming a second N-type epitaxial layer on the top surface of the first N-type epitaxial layer, wherein the doping concentration of the second N-type epitaxial layer is larger than that of the first N-type epitaxial layer, the second N-type epitaxial layer is used as a carrier storage layer, and the longitudinal position and the thickness of the carrier storage layer are set according to the current capability required by forward conduction of the IGBT device;
forming a plurality of P-type columns in the second N-type epitaxial layer, forming N-type columns by the second N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure;
forming a third N-type epitaxial layer on the surface of the second N-type epitaxial layer formed with the super junction structure, enabling the super junction structure to be a buried layer structure, and independently setting the thickness and the longitudinal position of the carrier storage layer by utilizing the buried layer structure; the doping concentration of the third N-type epitaxial layer is smaller than that of the second N-type epitaxial layer;
step four, performing a front process to form a front structure of each device unit structure of the IGBT device, wherein the front structure comprises:
Forming a P-type doped body region in a top region of the third N-type epitaxial layer;
forming a gate structure, wherein the surface of the body region covered by the gate structure is used for forming a channel;
forming an N+ doped emission region on the surface of the body region, wherein the emission region and the gate structure are self-aligned;
step five, carrying out a back process, which comprises the following steps:
performing a back thinning process, wherein the thickness of the first N-type epitaxial layer is thinned after the back thinning process;
performing P-type back ion implantation to form a collector region on the back of the thinned first N-type epitaxial layer;
the third N-type epitaxial layer, the N-type column and the first N-type epitaxial layer which are positioned in the body region and the collector region form a drift region;
a space is arranged between the body region and the P-type column, and the P-type column is in a floating structure;
when the IGBT device is reversely biased, the super junction structure is used for exhausting the carrier storage layer to improve the first withstand voltage of the carrier storage layer, the sum of the withstand voltages of the first N-type epitaxial layer and the third N-type epitaxial layer in the drift region is a second withstand voltage, and the total withstand voltage of the IGBT device is the sum of the first withstand voltage and the second withstand voltage, so that the thickness of the super junction structure and the total withstand voltage of the IGBT device are independent.
9. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 8, wherein: the longitudinal position of the carrier storage layer is in a range of 5-40 microns below the top surface of the drift region.
10. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 8, wherein:
step two, forming the P-type column in the second N-type epitaxial layer by adopting a photoetching definition and P-type ion implantation process;
or in the second step, a super-junction groove is formed in the second N-type epitaxial layer by adopting a photoetching definition etching process, and then a P-type epitaxial layer is filled in the super-junction groove to form the P-type column.
11. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 8, wherein: in the fourth step, the gate structure adopts a trench gate, and the forming step includes:
forming a gate trench, the gate trench passing through the body region; the side surface of the trench gate covers the body region;
forming a gate dielectric layer on the inner side surface of the gate trench;
and filling a gate conductive material layer in the gate trench.
12. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 8, wherein: in the fifth step, further comprising:
Performing N+ back ion implantation after the back thinning process to form a field stop layer on the back of the thinned first N-type epitaxial layer; a top surface of the collector region is in contact with a bottom surface of the field stop layer.
13. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 8, wherein: in the fourth step, the front side process further includes:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form an emitter and a grid;
the top of the emitting region is connected to an emitter consisting of a front metal layer through a contact hole, and the contact hole at the top of the emitting region is also in contact with the body region; the top of the gate structure is connected to a gate electrode composed of a front metal layer through a contact hole.
14. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 13, wherein: the forming process of the contact hole comprises the following steps:
forming an opening of the contact hole;
p+ ion implantation is carried out at the bottom of the opening of the contact hole at the top of the emission region, and a body leading-out region is formed;
and filling a metal layer in the opening of the contact hole.
15. The method for manufacturing the super-junction carrier storage type IGBT device according to claim 13, wherein: in the fifth step, further comprising:
And forming a back metal layer on the back surface of the collector region, and forming a collector by the back metal layer.
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