CN118198213A - Epitaxial wafer of red light Micro light-emitting diode and manufacturing method thereof - Google Patents
Epitaxial wafer of red light Micro light-emitting diode and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
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- 238000000034 method Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
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- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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Abstract
The invention relates to the technical field of light-emitting diodes, and discloses an epitaxial wafer of a red light Micro light-emitting diode and a manufacturing method thereof, wherein the epitaxial wafer comprises a substrate, a buffer layer, an N-type layer, a quantum well structure and a P-type layer, and the buffer layer, the N-type layer, the quantum well structure and the P-type layer are sequentially deposited on the substrate; the quantum well structure comprises an undoped first preset quantum well barrier layer, a plurality of quantum wells and an undoped second preset quantum well barrier layer, wherein the quantum wells are sequentially deposited on the first preset quantum well barrier layer, the second preset quantum well barrier layer is deposited on the quantum well positioned on the upper layer, the first preset quantum well barrier layer is deposited on the N-type layer, and the P-type layer is deposited on the second preset quantum well barrier layer. The epitaxial wafer can increase the concentration of the carriers, so that more carriers can be injected into the quantum well, and the concentration of the carriers in the quantum well is increased, thereby improving the luminous efficiency of the light-emitting diode.
Description
Technical Field
The disclosure relates to the technical field of light emitting diodes, in particular to an epitaxial wafer of a red light Micro light emitting diode and a manufacturing method thereof.
Background
With the development of display technology, micro LEDs (Micro light emitting diodes) are increasingly widely applied, and have the advantages of high brightness, wide color gamut, high reliability and the like, and are easy to realize flexibility, transparency, free splicing, sensing integration and the like.
In the related art, the concentration of carrier aggregation in a quantum well of an epitaxial wafer of a Micro LED is limited, and the luminous efficiency of the formed Micro LED can be influenced.
Disclosure of Invention
An object of the present disclosure is to provide an epitaxial wafer of a red light Micro light emitting diode and a method for manufacturing the same, so as to solve the above-mentioned problems in the related art.
In order to achieve the above objective, an aspect of the present disclosure provides an epitaxial wafer of a red light Micro light emitting diode, including a substrate, a buffer layer, an N-type layer, a quantum well structure, and a P-type layer, where the buffer layer, the N-type layer, the quantum well structure, and the P-type layer are sequentially deposited on the substrate;
the quantum well structure comprises an undoped first preset quantum well barrier layer, a plurality of quantum wells and an undoped second preset quantum well barrier layer, wherein the quantum wells are sequentially deposited on the first preset quantum well barrier layer, the second preset quantum well barrier layer is deposited on the quantum well positioned on the upper layer, the first preset quantum well barrier layer is deposited on the N-type layer, and the P-type layer is deposited on the second preset quantum well barrier layer.
Optionally, the first preset quantum well barrier layer and the second preset quantum well barrier layer each include a preset quantum well layer and a preset quantum barrier layer, and the preset quantum well layer is deposited on the preset quantum barrier layer;
wherein the composition content of the preset quantum well layer is (Al xGa1-X)0.5In0.5 P,0.6< x <0.7;
the component content of the preset quantum barrier layer is (Al yGa1-y)0.5In0.5 P,0.1< y <0.15;
the thicknesses of the preset quantum well layer and the preset quantum barrier layer are 40A-80A.
Optionally, the N-type layer comprises a GaInP corrosion stop layer, an N-GaAs ohmic contact layer, an N-AlInP limiting layer and an N- (Al xGa1-x) InP waveguide layer which are deposited in sequence;
the thickness of the n-GaAs ohmic contact layer is 500A-800A, and the doping concentration is more than 5E18;
the thickness of the n-AlInP limiting layer is 2000A-3000A;
The thickness of the n- (Al xGa1-x) InP waveguide layer is 400A-800A,0.55< x <0.65.
Optionally, a superlattice layer is further deposited between the n-GaAs ohmic contact layer and the n-AlInP confining layer, the superlattice layer being provided as a 10-25 pair superlattice modulation doped layer.
Optionally, the superlattice layer includes a first layer and a second layer;
the first layer is provided as an n- (Al zGa1-z) InP layer, wherein 0.25< Z <0.35;
The second layer is provided as an n- (Al αGa1-α) InP layer, wherein 0.42< alpha <0.55;
the thickness of the first layer and the second layer is 150A-280A.
Optionally, the quantum well is configured as a component superlattice, the quantum well including a quantum well layer and a quantum barrier layer, the quantum well layer being deposited on the quantum barrier layer;
The component content of the quantum well layer is (Al xGa1-X)0.5In0.5 P, wherein 0.6< x <0.7;
The quantum barrier layer has a composition content of (Al yGa1-y)0.5In0.5 P, wherein 0.1< y <0.15;
the thicknesses of the quantum well layer and the quantum barrier layer are 30A-50A.
Optionally, the number of the quantum wells is 2-4, and the values of X in the quantum well layers and Y in the quantum barrier layers of the plurality of quantum wells are gradually reduced or increased from bottom to top.
Optionally, the P-type layer comprises a P- (Al xGa1-x) InP waveguide layer, a P-AlInP limiting layer, a P- (Al xGa1-x)yIn1-y P transition layer, a P-GaP layer and a P-GaP ohmic contact layer which are sequentially deposited;
The thickness of the p- (Al xGa1-x) InP waveguide layer is 400A-600A, wherein x is 0.55< 0.65;
The thickness of the p-AlInP limiting layer is 4000A-6000A;
The thickness of the P- (Al xGa1-x)yIn1-y P transition layer is 50A-200A, wherein 0.15< x <0.25,0.65< y <0.75;
The thickness of the p-GaP layer is 6000A-7000A;
The doping concentration of the p-GaP layer is 3 x 10 18cm-3-9*1018cm-3;
The thickness of the p-GaP ohmic contact layer is 50A-500A;
The p-GaP ohmic contact layer is doped with magnesium or carbon, and the doping concentration is 3 x 10 19cm-3-6*1019cm-3.
Optionally, an electron confinement layer is further deposited between the p- (Al xGa1-x) InP waveguide layer and the p-AlInP confinement layer, and the thickness of the electron confinement layer is 200A-500A;
the electron limiting layer comprises a first limiting layer and a second limiting layer, wherein the component content of the first limiting layer is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y < 0.65);
the component content of the second limiting layer is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y < 0.65).
The second aspect of the present disclosure also provides a method for manufacturing an epitaxial wafer of a red light Micro light emitting diode, including:
Taking a substrate;
Sequentially depositing a buffer layer, an N-type layer, a quantum well structure and a P-type layer on the surface of the substrate;
wherein the deposition is carried out in an environment having a temperature of 700 ℃ to 750 ℃ and a pressure of 50mbar to 60 mbar.
Compared with the prior art, the invention has the beneficial effects that:
According to the technical scheme, the first preset quantum well barrier layer and the second preset quantum well barrier layer are respectively arranged on the upper surface and the lower surface of the quantum well MQWs, and can increase the concentration of the carriers, so that more carriers can be injected into the quantum well MQWs, the concentration of the carriers in the quantum well MQWs is improved, and the luminous efficiency of the Micro light-emitting diode is improved.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
Fig. 1 is a schematic structural view of an epitaxial wafer according to one embodiment of the present disclosure;
fig. 2 is a flow chart illustrating a method of manufacturing an epitaxial wafer according to an embodiment of the present disclosure.
Reference numerals illustrate: 10. a substrate;
20. A buffer layer;
30. an N-type layer, 31, a GaInP corrosion stop layer, 32, an N-GaAs ohmic contact layer, 33, an N-AlInP confinement layer, 34, an N- (Al xGa1-x) InP waveguide layer;
40. The quantum well structure 41, the first preset quantum well barrier layer 42, the quantum well 421, the quantum well layer 422, the quantum barrier layer 43, the second preset quantum well barrier layer 44, the preset quantum well layer 45 and the preset quantum barrier layer;
50. A P-type layer, 51, a P- (Al xGa1-x) InP waveguide layer, 52, a P-AlInP confinement layer, 53, a P- (Al xGa1-x)yIn1-y P transition layer, 54, a P-GaP layer, 55, a P-GaP ohmic contact layer;
60. A superlattice layer 61, a first layer 62, a second layer;
70. An electron confinement layer 71, a first confinement layer 72, a second confinement layer.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
In the present disclosure, unless otherwise indicated, the use of the orientation terms such as "upper" and "lower" are generally defined with respect to the orientation of the drawing figures, and "inner" and "outer" refer to the interior and exterior of the associated components. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present disclosure, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, directly connected, indirectly connected through an intermediary, or communicating between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
As shown in fig. 1, an aspect of the present disclosure provides an epitaxial wafer of a red light Micro light emitting diode, which includes a substrate 10, a buffer layer 20, an N-type layer 30, a quantum well structure 40, and a P-type layer 50, wherein the buffer layer 20, the N-type layer 30, the quantum well structure 40, and the P-type layer 50 are sequentially deposited on the substrate 10.
The quantum well structure 40 includes an undoped first preset quantum well barrier layer 41, a plurality of quantum wells 42, and an undoped second preset quantum well barrier layer 43, the plurality of quantum wells 42 are sequentially deposited on the first preset quantum well barrier layer 41, the second preset quantum well barrier layer 43 is deposited on the quantum well 42 positioned on the upper layer, the first preset quantum well barrier layer 41 is deposited on the N-type layer 30, and the P-type layer 50 is deposited on the second preset quantum well barrier layer 43.
Wherein the quantum well 42 is between a first pre-set quantum well barrier layer 41 and a second pre-set quantum well barrier layer 43.
In the above technical solution, by disposing the first preset quantum well barrier layer 41 and the second preset quantum well barrier layer 43 on the upper surface and the lower surface of the quantum well 42, the first preset quantum well barrier layer 41 and the second preset quantum well barrier layer 43 can increase the concentration of the carriers, so that more carriers can be injected into the quantum well 42, and the concentration of the carriers in the quantum well 42 is increased, thereby improving the light emitting efficiency of the Micro light emitting diode formed.
Optionally, in one embodiment of the present disclosure, the first and second preset quantum well barrier layers 41 and 43 each include a preset quantum well layer 44 and a preset quantum barrier layer 45, and the preset quantum well layer 44 is deposited on the preset quantum barrier layer 45.
That is, the preset quantum barrier layer 45 of the first preset quantum well barrier layer 41 is deposited on the N-type layer 30, and the quantum well 42 is deposited on the preset quantum well layer 44 of the first preset quantum well barrier layer 41. The pre-set quantum barrier layer 45 of the second pre-set quantum well barrier layer 43 is deposited on the quantum well 42, and the pre-set quantum well layer 44 of the second pre-set quantum well barrier layer 43 is deposited on the pre-set quantum barrier layer 45 of the second pre-set quantum well barrier layer 43.
The composition of the preset quantum well layer 44 is (Al xGa1-X)0.5In0.5 P,0.6< x <0.7. The composition of the preset quantum barrier layer 45 is (Al yGa1-y)0.5In0.5 P,0.1< y <0.15. The thicknesses of the preset quantum well layer 44 and the preset quantum barrier layer 45 are 40A-80A. It should be noted that the thicknesses of the preset quantum well layer 44 and the preset quantum barrier layer 45 may be the same or different.
Optionally, in one embodiment of the present disclosure, the N-type layer 30 includes a GaInP etch stop layer 31, an N-GaAs ohmic contact layer 32, an N-AlInP confining layer 33, and an N- (Al xGa1-x) InP waveguide layer 34, deposited in that order.
It will be appreciated that the GaInP etch stop layer 31 is deposited on the buffer layer 20 and the pre-set quantum barrier layer 45 of the first pre-set quantum well barrier layer 41 is deposited on the n- (Al xGa1-x) InP waveguide layer 34.
The n-GaAs ohmic contact layer 32 has a thickness of 500A-800A and a doping concentration of >5E18. The n-AlInP confinement layer 33 has a thickness of 2000A to 3000A. The thickness of the n- (Al xGa1-x) InP waveguide layer 34 is 400A-800A,0.55< x <0.65.
Optionally, in one embodiment of the present disclosure, a superlattice layer 60 is also deposited between the n-GaAs ohmic contact layer 32 and the n-AlInP confining layer 33, the superlattice layer 60 being provided as a 10-25 pair superlattice modulated doped layer. By the arrangement, the doping of the N-type layer 30 can be reduced while the carrier concentration is not reduced, the loss of carriers in a thermal state is reduced, the optical efficiency in the thermal state is enhanced, and the cold-hot ratio is improved.
It will be appreciated that the superlattice layer 60 is deposited on the n-GaAs ohmic contact layer 32, and the n-AlInP confining layer 33 is deposited on the superlattice layer 60.
Alternatively, in one embodiment of the present disclosure, the superlattice layer 60 includes a first layer 61 and a second layer 62, and the second layer 62 may be deposited on the first layer 61.
The first layer 61 is provided as an n- (Al zGa1-z) InP layer, where 0.25< Z <0.35. The second layer 62 is provided as an n- (Al αGa1-α) InP layer, where 0.42< alpha <0.55. The thickness of both first layer 61 and second layer 62 is 150A-280A. The thicknesses of the first layer 61 and the second layer 62 may be the same or different.
Alternatively, in one embodiment of the present disclosure, quantum well 42 is provided as a compositional superlattice, quantum well 42 includes a quantum well layer 421 and a quantum barrier layer 422, and quantum well layer 421 is deposited on quantum barrier layer 422.
Wherein the quantum well layers 421 and the quantum barrier layers 422 of the plurality of quantum wells 42 are sequentially and alternately deposited, that is, the quantum well layers 421 are deposited on the quantum barrier layers 422 of one quantum well 42, and the quantum barrier layers 422 of the other quantum well 42 are deposited on the quantum well layers 421 of the previous quantum well 42. The lowermost quantum barrier layer 422 is deposited on the preset quantum well layer 44 of the first preset quantum well barrier layer 41, and the preset quantum barrier layer 45 of the second preset quantum well barrier layer 43 is deposited on the uppermost quantum well layer 421.
The composition of the quantum well layer 421 is (Al xGa1-X)0.5In0.5 P, wherein 0.6< x <0.7. The composition of the quantum barrier layer 422 is (Al yGa1-y)0.5In0.5 P, wherein 0.1< y <0.15. The thicknesses of the quantum well layer 421 and the quantum barrier layer 422 are 30A-50A. It should be noted that the thicknesses of the quantum well layer 421 and the quantum barrier layer 422 may be the same or different.
Alternatively, in one embodiment of the present disclosure, the number of quantum wells 42 is 2-4, and the value of X in the quantum well layer 421 and the value of Y in the quantum barrier layer 422 of the plurality of quantum wells 42 are each gradually decreased or increased from bottom to top. By performing linear gradual change on the value of X in the quantum well layer 421 and the value of Y in the quantum barrier layer 422, the fermi level is also changed, so that a quasi-dynamic level is formed, carrier directional beam approximate and recombination are facilitated, and the consistency of wavelength and light efficiency is improved.
In some examples, the value of X in the quantum well layer 421 and the value of Y in the quantum barrier layer 422 of the quantum well 42 located below may be less than the value of X in the quantum well layer 421 and the value of Y in the quantum barrier layer 422 of the quantum well 42 located above in the plurality of quantum wells 42.
In other examples, the number of X in the quantum well layer 421 and the number of Y in the quantum barrier layer 422 of the quantum well 42 located below may be greater than the number of X in the quantum well layer 421 and the number of Y in the quantum barrier layer 422 of the quantum well 42 located above in the plurality of quantum wells 42.
Alternatively, in one embodiment of the present disclosure, the P-type layer 50 includes a P- (Al xGa1-x) InP waveguide layer 51, a P-AlInP confinement layer 52, a P- (Al xGa1-x)yIn1-y P transition layer 53, a P-GaP layer 54, and a P-GaP ohmic contact layer 55, which are deposited in that order.
Wherein a p- (Al xGa1-x) InP waveguide layer 51 is deposited on the pre-set quantum well layer 44 of the second pre-set quantum well barrier layer 43.
The thickness of the p- (Al xGa1-x) InP waveguide layer 51 is 400A-600A, where 0.55< x <0.65. The thickness of the p-AlInP confinement layer 52 is 4000A-6000A. The thickness of the P- (Al xGa1-x)yIn1-y P) transition layer 53 is 50A-200A, wherein 0.15< x <0.25,0.65< y <0.75. The thickness of the P-GaP layer 54 is 6000A-7000A, the doping concentration of the P-GaP layer 54 is 3 x 10 18cm-3-9*1018cm-3. The thickness of the P-GaP ohmic contact layer 55 is 50A-500A, the P-GaP ohmic contact layer 55 is doped with magnesium or carbon, and the doping concentration is 3 x 10 19cm-3-6*1019cm-3.
Optionally, in one embodiment of the present disclosure, an electron confinement layer 70 is further deposited between the p- (Al xGa1-x) InP waveguide layer 51 and the p-AlInP confinement layer 52, the electron confinement layer 70 having a thickness of 200A-500A.
The electron confinement layer 70 includes a first confinement layer 71 and a second confinement layer 72, the second confinement layer 72 is deposited on the first confinement layer 71, the composition content of the first confinement layer 71 is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y <0.65. The composition content of the second confinement layer 72 is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y <0.65. By providing the electron confinement layer 70, confinement of electron leakage in a thermal state can be achieved, the strain control layer is non-radiative recombination, and injection efficiency is improved.
Alternatively, the substrate 10 may be a GaAs substrate, and the buffer layer 20 may be a GaAs buffer layer 20.
As shown in fig. 2, the second aspect of the present disclosure further provides a method for manufacturing an epitaxial wafer of a red light Micro light emitting diode, including:
S201, taking a substrate 10.
S202, sequentially depositing a buffer layer 20, an N-type layer 30, a quantum well structure 40 and a P-type layer 50 on the surface of the substrate 10.
Wherein the deposition is carried out in an environment having a temperature of 700 ℃ to 750 ℃ and a pressure of 50mbar to 60 mbar. Wherein the doping layer concentration is 1×10 18cm-3-5*1018cm-3.
In some examples, buffer layer 20, gaInP etch stop layer 31, n-GaAs ohmic contact layer 32, superlattice layer 60, n-AlInP confinement layer 33, n- (Al xGa1-x) InP waveguide layer 34, first preset quantum well barrier layer 41, plurality of quantum wells 42, second preset quantum well barrier layer 43, P- (Al xGa1-x) InP waveguide layer 51, electron confinement layer 70, P-AlInP confinement layer 52, P- (Al xGa1-x)yIn1-y P transition layer 53, P-GaP layer 54, and P-GaP ohmic contact layer 55 are deposited in that order on the surface of substrate 10.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the embodiments described above, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.
In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.
Claims (10)
1. The epitaxial wafer of the red light Micro light-emitting diode is characterized by comprising a substrate (10), a buffer layer (20), an N-type layer (30), a quantum well structure (40) and a P-type layer (50), wherein the buffer layer (20), the N-type layer (30), the quantum well structure (40) and the P-type layer (50) are sequentially deposited on the substrate (10);
The quantum well structure (40) comprises an undoped first preset quantum well barrier layer (41), a plurality of quantum wells (42) and an undoped second preset quantum well barrier layer (43), wherein the quantum wells (42) are sequentially deposited on the first preset quantum well barrier layer (41), the second preset quantum well barrier layer (43) is deposited on the quantum well (42) positioned on the upper layer, the first preset quantum well barrier layer (41) is deposited on the N-type layer (30), and the P-type layer (50) is deposited on the second preset quantum well barrier layer (43).
2. The epitaxial wafer of a red light Micro light emitting diode according to claim 1, wherein the first preset quantum well barrier layer (41) and the second preset quantum well barrier layer (43) each comprise a preset quantum well layer (44) and a preset quantum barrier layer (45), the preset quantum well layer (44) being deposited on the preset quantum barrier layer (45);
Wherein the composition content of the preset quantum well layer (44) is (Al xGa1-X)0.5In0.5 P,0.6< x <0.7;
The component content of the preset quantum barrier layer (45) is (Al yGa1-y)0.5In0.5 P,0.1< y <0.15;
The thicknesses of the preset quantum well layer (44) and the preset quantum barrier layer (45) are 40A-80A.
3. The epitaxial wafer of the red light Micro light emitting diode according to claim 1, wherein the N-type layer (30) comprises a GaInP etch stop layer (31), an N-GaAs ohmic contact layer (32), an N-AlInP confinement layer (33) and an N- (AlxGa 1-x) InP waveguide layer (34) deposited in that order;
the thickness of the n-GaAs ohmic contact layer (32) is 500A-800A, and the doping concentration is more than 5E18;
The thickness of the n-AlInP limiting layer (33) is 2000A-3000A;
the thickness of the n- (AlxGa 1-x) InP waveguide layer (34) is 400A-800A,0.55< x <0.65.
4. The epitaxial wafer of a red light Micro light emitting diode according to claim 3, characterized in that a superlattice layer (60) is further deposited between the n-GaAs ohmic contact layer (32) and the n-AlInP confining layer (33), the superlattice layer (60) being provided as a 10-25 pair superlattice modulation doped layer.
5. The epitaxial wafer of a red light Micro light emitting diode according to claim 4, characterized in that the superlattice layer (60) comprises a first layer (61) and a second layer (62);
The first layer (61) is provided as an n- (Al zGa1-z) InP layer, wherein 0.25< Z <0.35;
the second layer (62) is provided as an n- (Al αGa1-α) InP layer, wherein 0.42< alpha <0.55;
The thickness of the first layer (61) and the second layer (62) is 150A-280A.
6. The epitaxial wafer of a red light Micro light emitting diode according to claim 1, characterized in that the quantum well (42) is provided as a component superlattice, the quantum well (42) comprising a quantum well layer (421) and a quantum barrier layer (422), the quantum well layer (421) being deposited on the quantum barrier layer (422);
the quantum well layer (421) has a composition content of (Al xGa1-X)0.5In0.5 P, wherein 0.6< x <0.7;
the quantum barrier layer (422) has a composition content of (Al yGa1-y)0.5In0.5 P, wherein 0.1< y <0.15;
The thicknesses of the quantum well layer (421) and the quantum barrier layer (422) are 30A-50A.
7. The epitaxial wafer of the red light Micro light emitting diode according to claim 6, wherein the number of the quantum wells (42) is 2-4, and the value of X in the quantum well layer (421) and the value of Y in the quantum barrier layer (422) of the plurality of the quantum wells (42) are gradually reduced or increased from bottom to top.
8. The epitaxial wafer of a red light Micro light emitting diode according to any one of claims 1 to 7, wherein the P-type layer (50) comprises a P- (AlxGa 1-x) InP waveguide layer (51), a P-AlInP confinement layer (52), a P- (AlxGa 1-x) yIn-yP transition layer (53), a P-GaP layer (54) and a P-GaP ohmic contact layer (55) deposited in that order;
The thickness of the p- (Al xGa1-x) InP waveguide layer (51) is 400A-600A, wherein x is 0.55< 0.65;
the thickness of the p-AlInP limiting layer (52) is 4000A-6000A;
The thickness of the P- (Al xGa1-x)yIn1-y P transition layer (53) is 50A-200A, wherein 0.15< x <0.25,0.65< y <0.75;
The thickness of the p-GaP layer (54) is 6000A-7000A;
The doping concentration of the p-GaP layer (54) is 3 x 10 18cm-3-9*1018cm-3;
the thickness of the p-GaP ohmic contact layer (55) is 50A-500A;
the p-GaP ohmic contact layer (55) is doped with magnesium or carbon at a doping concentration of 3 x 10 19cm-3-6*1019cm-3.
9. The epitaxial wafer of a red light Micro light emitting diode according to claim 8, wherein an electron confinement layer (70) is further deposited between the p- (Al xGa1-x) InP waveguide layer (51) and the p-AlInP confinement layer (52), the thickness of the electron confinement layer (70) being 200A-500A;
Wherein the electron confinement layer (70) comprises a first confinement layer (71) and a second confinement layer (72), and the component content of the first confinement layer (71) is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y < 0.65);
The composition content of the second limiting layer (72) is P- (Al xGa1-x)yIn1-y P,0.55< x <0.65;0.55< y < 0.65).
10. The manufacturing method of the epitaxial wafer of the red light Micro light emitting diode is characterized by comprising the following steps of:
Taking a substrate (10);
sequentially depositing a buffer layer (20), an N-type layer (30), a quantum well structure (40) and a P-type layer (50) on the surface of the substrate (10);
wherein the deposition is carried out in an environment having a temperature of 700 ℃ to 750 ℃ and a pressure of 50mbar to 60 mbar.
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