CN118136619A - Half-bridge structure of power module, power module and vehicle - Google Patents

Abstract

The application provides a half-bridge structure of a power module, the power module and a vehicle. The half-bridge structure comprises a substrate and a chip set arranged on the substrate. The substrate is provided with a positive electrode connection region, a negative electrode connection region and an alternating current connection region. The chip set includes bridge chip set and lower bridge chip set, and bridge chip set includes a plurality of parallel connection's bridge chip that goes up down, and bridge chip set includes a plurality of parallel connection's bridge chip down, and a plurality of bridge chip that go up set up respectively symmetry in the anodal opposite both sides of connecting the region, and a plurality of bridge chip down set up respectively symmetry in the opposite both sides of negative electrode connecting the region to, the chip quantity in the two regions of symmetry setting is the same. According to the power module provided by the application, the stray inductance of the module is reduced by shortening the power loop path, the voltage stress of the module in the turn-off process is reduced, and the service life and reliability of the power module are improved.

Description

Half-bridge structure of power module, power module and vehicle

Technical Field

The embodiment of the application relates to the technical field of power electronics, in particular to a half-bridge structure of a power module, the power module and a vehicle.

Background

With the development of power electronics technology, power modules have attracted more and more attention. The power module is a device which combines a plurality of semiconductor chips into a whole according to certain functions and modes, is mainly applied to a power loop of a power electronic system, and is core hardware for realizing electric energy conversion.

Currently, silicon carbide (SiC) power modules are increasingly being used in new energy automotive applications. Compared with an IGBT (Insulate Gate Bipolar Transistor, insulated gate bipolar transistor), a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a faster switching speed and lower switching loss, and therefore, the high-speed switching process becomes sensitive to parasitic parameters, and high-frequency oscillation and voltage overshoot are more likely to occur. Therefore, how to further optimize the power loop noise of existing packaging schemes remains a significant challenge.

Disclosure of Invention

The embodiment of the application aims to provide a power module and a vehicle, which can effectively reduce the noise of a current conversion loop.

One aspect of an embodiment of the present application provides a half-bridge structure of a power module. The half-bridge structure comprises a substrate and a chip set arranged on the substrate. The substrate is provided with a positive electrode connection area, a negative electrode connection area and an alternating current connection area. The chip set comprises an upper bridge chip set and a lower bridge chip set, wherein the upper bridge chip set comprises a plurality of upper bridge chips connected in parallel, and the lower bridge chip set comprises a plurality of lower bridge chips connected in parallel. The upper bridge chips are symmetrically arranged on two opposite sides of the positive electrode connection area respectively, the lower bridge chips are symmetrically arranged on two opposite sides of the negative electrode connection area respectively, and the number of chips in the two symmetrically arranged areas is the same.

Further, the substrate comprises a first substrate and a second substrate arranged on the first substrate, wherein the upper bridge chip set, the lower bridge chip set, the positive electrode connection area and the alternating current connection area are arranged on the first substrate, and the negative electrode connection area is arranged on the second substrate.

Further, the first substrate includes a first upper conductive layer, a first lower conductive layer, and a first intermediate insulating layer between the first upper conductive layer and the first lower conductive layer, the second substrate includes a second upper conductive layer, a second lower conductive layer, and a second intermediate insulating layer between the second upper conductive layer and the second lower conductive layer, the first upper conductive layer includes a first conductive region and a second conductive region spaced apart from each other, wherein the positive electrode connection region is located in the first conductive region, the drains of the upper bridge chips are connected to the first conductive region, the drains of the lower bridge chips are connected to the second conductive region, the second lower conductive layer of the second substrate is connected to the second conductive region of the first substrate, and the negative electrode connection region is located in the second upper conductive layer.

Further, the sources of the upper bridge chips are electrically connected to the second conductive regions through independent upper metal sheets, respectively, and the sources of the lower bridge chips are electrically connected to the second upper conductive layers of the second substrate through independent lower metal sheets, respectively.

Further, the positive electrode connection region and the negative electrode connection region are located in a middle region of the substrate, and the alternating current connection region is disposed near the first end of the substrate.

Further, the substrate is further provided with a plurality of signal connection areas, wherein the plurality of signal connection areas of the upper bridge chip set are distributed on a first side of the first substrate, the plurality of signal connection areas of the lower bridge chip set are on a second side of the first substrate, and the first side is opposite to the second side and is adjacent to the first end.

Further, the half-bridge structure further comprises a plastic package shell, wherein the plastic package shell is used for wrapping the substrate and the chip set, and the positive electrode connection area, the negative electrode connection area, the alternating current connection area and the signal connection area are exposed out of the plastic package shell.

Further, the half-bridge structure further comprises a plurality of signal terminals, and the plurality of signal terminals are respectively and correspondingly connected with the plurality of signal connection areas exposed outside the plastic package shell.

Further, the half-bridge structure further comprises a positive direct current busbar and a negative direct current busbar, the positive direct current busbar is provided with a first connecting portion and a first plane main body portion, the negative direct current busbar is provided with a second connecting portion and a second plane main body portion, the first connecting portion is used for being connected to the positive electrode connecting area, the second connecting portion is used for being connected to the negative electrode connecting area, and the first plane main body portion and the second plane main body portion are mutually overlapped and are arranged at intervals.

Another aspect of an embodiment of the application provides a power module. The power module comprises three half-bridge structures of the power module according to the above embodiments and a heat dissipation substrate, wherein the three half-bridge structures are connected to the heat dissipation substrate.

Another aspect of an embodiment of the application provides a vehicle. The vehicle comprises a power module as described above.

According to the half-bridge structure of the power module, the power module and the vehicle of one or more embodiments of the application, the upper bridge chip set and the lower bridge chip set are symmetrically arranged on the two opposite sides of the positive electrode connection area and the negative electrode connection area, so that parallel current division is realized, and meanwhile, the current conversion path can be greatly shortened, and the noise of the current conversion flow of the power module is reduced.

Drawings

Fig. 1 is a schematic perspective view of a half-bridge structure according to an embodiment of the present application.

Fig. 2 is a side view of the half-bridge structure shown in fig. 1.

Fig. 3 is a top view of the half-bridge structure shown in fig. 1.

Fig. 4 is a partially exploded schematic view of the half-bridge structure shown in fig. 1.

Fig. 5 is a top view of a first substrate according to an embodiment of the application.

Fig. 6 is a schematic top view of an upper bridge chip and a lower bridge chip mounted on a first substrate according to an embodiment of the application.

Fig. 7 is a schematic diagram of one example of a half-bridge commutation path formed in accordance with the present application.

Fig. 8 is a schematic perspective view of a half-bridge structure according to another embodiment of the present application.

Fig. 9 is a schematic perspective view of a half-bridge structure according to yet another embodiment of the present application.

Fig. 10 is a schematic perspective view of a half-bridge structure according to still another embodiment of the present application.

Fig. 11 is a schematic perspective view of a positive dc busbar and a negative dc busbar according to an embodiment of the present application.

Fig. 12 is a schematic diagram of the overall structure of a power module according to an embodiment of the application.

Fig. 13 is a full-bridge circuit topology of a power module according to an embodiment of the application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with aspects of the application as detailed in the accompanying claims.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The application provides a half-bridge structure of a power module. The half-bridge structure of various embodiments of the present application will be described in detail below with reference to the accompanying drawings. The features of the examples and embodiments described below may be combined with each other without conflict.

Fig. 1 to 4 disclose illustrations of a half-bridge structure 100 of a power module according to an embodiment of the present application, wherein fig. 1 is a perspective view of the half-bridge structure 100; FIG. 2 is a side view of the half-bridge structure 100 shown in FIG. 1; FIG. 3 is a top view of the half-bridge structure 100 shown in FIG. 1; fig. 4 is a partially exploded schematic view of the half-bridge structure 100 shown in fig. 1. As shown in fig. 1 to 4, a half-bridge structure 100 according to an embodiment of the present application includes a substrate and a chipset disposed on the substrate. The substrate may include, for example, but is not limited to, a ceramic substrate.

The substrate is provided with a power connection area for connecting the power busbar and a plurality of signal connection areas for connecting a plurality of signal terminals. The power connection areas include a positive connection area dc+ for connecting the positive DC busbar 81, a negative connection area DC-for connecting the negative DC busbar 82, and an AC connection area AC for connecting the AC busbar 83.

The chip sets include an upper bridge chip set 31 and a lower bridge chip set 32. The upper bridge chipset 31 may include a plurality of upper bridge chips 310 connected in parallel, and the lower bridge chipset 32 may include a plurality of lower bridge chips 320 connected in parallel. For example, in the illustrated embodiment, upper bridge chipset 31 includes eight upper bridge chips 310 connected in parallel, and lower bridge chipset 32 includes eight lower bridge chips 320 connected in parallel. Of course, the number of chips included in the upper bridge chip 310 and the lower bridge chip 320 of the present application is not limited to eight as shown in the drawings, and may include any number of chips according to practical application requirements. In one embodiment, upper bridge chips 310 in upper bridge chipset 31 and lower bridge chips 320 in lower bridge chipset 32 may include, for example, but are not limited to, silicon carbide (SiC) chips.

The upper bridge chips 310 in the upper bridge chipset 31 are symmetrically disposed on opposite sides of the positive electrode connection region dc+, the lower bridge chips 320 in the lower bridge chipset 32 are symmetrically disposed on opposite sides of the negative electrode connection region DC-, and the number of chips in the two symmetrically disposed regions is the same. For example, in fig. 3, eight upper bridge chips 310 in the upper bridge chip group 31 are symmetrically disposed on opposite sides of the positive electrode connection region dc+ respectively, and the number of upper bridge chips 310 on opposite sides of the positive electrode connection region dc+ is the same, that is, four upper bridge chips 310 are symmetrically disposed on each of the upper side and the lower side of the positive electrode connection region dc+; eight lower bridge chips 320 in the lower bridge chip set 32 are symmetrically disposed on opposite sides of the anode connection region DC-, respectively, and the number of lower bridge chips 320 on opposite sides of the anode connection region DC-, respectively, is the same, i.e., four lower bridge chips 320 are symmetrically disposed on upper and lower sides of the anode connection region DC-, respectively.

The half-bridge structure 100 of the present application can greatly shorten the commutation path and reduce the noise of the commutating current while realizing parallel shunting by symmetrically disposing the upper bridge chip set 31/the lower bridge chip set 32 on opposite sides of the positive electrode connection region dc+/the negative electrode connection region DC-and the layout manner that the positive electrode connection region dc+ and the negative electrode connection region DC-are located in the middle of the chip.

Referring to fig. 2 and 4 in combination, in some embodiments, the substrate of the present application may include a first substrate 1 and a second substrate 2 disposed on the first substrate 1. The first substrate 1 includes a first upper conductive layer 11, a first lower conductive layer 12, and a first intermediate insulating layer 13 between the first upper conductive layer 11 and the first lower conductive layer 12; the second substrate 2 includes a second upper conductive layer 21, a second lower conductive layer 22, and a second intermediate insulating layer 23 between the second upper conductive layer 21 and the second lower conductive layer 22. The first substrate 1 and the second substrate 2 may include, for example, but not limited to, ceramic substrates. The first upper conductive layer 11 and the first lower conductive layer 12 of the first substrate 1, and the second upper conductive layer 21 and the second lower conductive layer 22 of the second substrate 2 may be copper layers, for example, and the first intermediate insulating layer 13 of the first substrate 1 and the second intermediate insulating layer 23 of the second substrate 2 may be ceramic layers, for example.

Fig. 5 discloses a top view of the first substrate 1 according to an embodiment of the application. As shown in fig. 5 in combination with reference to fig. 4, the upper bridge chip set 31, the lower bridge chip set 32, the positive electrode connection region dc+, the alternating current connection region AC, and the plurality of signal connection regions are provided on the first substrate 1. The first upper conductive layer 11 of the first substrate 1 includes a first conductive region 111 and a second conductive region 112 spaced apart from each other. Wherein the positive electrode connection region dc+ is located in the first conductive region 111 of the first substrate 1.

As shown in fig. 4, the negative electrode connection region DC-is provided on the second substrate 2. Fig. 6 discloses a schematic top view of an upper bridge chip 310 and a lower bridge chip 320 mounted on a first substrate 1 according to an embodiment of the present application. Referring to fig. 6 in combination, the back surfaces of the plurality of upper bridge chips 310 are connected to the first conductive region 111 as the drain d, and the back surfaces of the plurality of lower bridge chips 320 are connected to the second conductive region 112 as the drain d. Alternatively, the back surfaces of the plurality of upper bridge chips 310 and the plurality of lower bridge chips 320 may be sintered to the first conductive region 111 and the second conductive region 112 of the first substrate 1, respectively, through the sintered layers. The negative electrode connection region DC-is located in the second upper conductive layer 21 of the second substrate 2, and the second lower conductive layer 22 of the second substrate 2 is connected to the second conductive region 112 of the first substrate 1. Alternatively, the second lower conductive layer 22 of the second substrate 2 may be soldered to the second conductive region 112 of the first substrate 1 through a soldering/sintering process.

As shown in fig. 1, 3 and 4, the front surfaces of the plurality of upper bridge chips 310 are electrically connected to the second conductive regions 112 as source electrodes s through the plurality of independent upper metal sheets 41, respectively, and the front surfaces of the plurality of lower bridge chips 320 are electrically connected to the second upper conductive layer 21 of the second substrate 2 as source electrodes s through the plurality of independent lower metal sheets 42, respectively. The separate upper metal sheet 41 and the separate lower metal sheet 42 may include, for example, but are not limited to, copper foil or the like. The number of independent upper metal sheets 41 and independent lower metal sheets 42 is equal to the number of upper bridge chips 310 and lower bridge chips 320, respectively. In the illustrated embodiment of the application, the plurality of individual upper metal sheets 41 are eight identical upper copper foils and the plurality of individual lower metal sheets 42 are eight identical lower copper foils. In one embodiment, both ends of the upper copper foil may be electrically connected to the copper layer (i.e., the second conductive region 112) where the front side of the upper bridge chip 310 and the lower bridge chip 320 are located, respectively, by a soldering or sintering process, and both ends of the lower copper foil may be electrically connected to the copper layer (i.e., the second upper conductive layer 21) where the front side of the lower bridge chip 320 and the negative electrode connection region DC-are located, respectively, by a soldering or sintering process.

Fig. 7 discloses a schematic diagram of one example of a half-bridge commutation path formed in accordance with the present application. As shown in fig. 7, the current from the positive electrode connection region dc+ sequentially passes through the first conductive region 111 of the first substrate 1 where the positive electrode connection region dc+ is located, enters the plurality of upper bridge chips 310 connected in parallel, passes through the upper bridge chips 310 as the back surface of the drain d and the upper bridge chips 310 as the front surface of the source s, then flows through the second conductive region 112 of the first substrate 1 by means of the independent upper metal sheet 41, enters the plurality of lower bridge chips 320 connected in parallel, passes through the back surface of the lower bridge chip 320 as the drain d and the front surface of the lower bridge chip 320 as the source s, then flows through the second upper conductive layer 21 of the second substrate 2 by means of the independent lower metal sheet 42, and finally is outputted to the negative electrode connection region DC-through the second upper conductive layer 21 where the negative electrode connection region DC-is located, thereby completing the current conversion. The application can greatly shorten the current conversion path and reduce the noise of the current conversion path.

The half-bridge structure 100 of the present application enables the current of the lower bridge chipset 32 to flow into the second upper conductive layer 21 of the second substrate 2 by means of the independent lower metal sheet 42 by independently disposing the negative electrode connection region DC-on the second substrate 2, so that the region of the second conductive region 112 of the first substrate 1 is more complete, and the second conductive region 112 may have a larger area as shown in fig. 5, so that the path noise can be further reduced; in addition, by adopting such a 3D structure, the structure of the entire half-bridge structure 100 can be made more compact.

Of course, it is understood that the half-bridge structure 100 of the present application is not limited to disposing the positive electrode connection region dc+ and the negative electrode connection region DC-on two substrates (i.e., the first substrate 1 and the second substrate 2), respectively. In other embodiments, the half-bridge structure 100 of the present application may also have the positive electrode connection region dc+ and the negative electrode connection region DC-respectively disposed on the same substrate, which may also have the beneficial technical effects of shortening the current converting path and reducing the noise of the current converting path shown in fig. 5.

With continued reference to fig. 3, the plurality of signal connection regions may include a plurality of signal connection regions 113 of the upper bridge chipset, a plurality of signal connection regions 114 of the lower bridge chipset 32, the plurality of signal connection regions 113, 114 including a plurality of gate signal connection regions 1131, 1141, respectively.

The plurality of parallel-connected upper bridge chips 310 distributed at each side of the positive electrode connection region dc+ constitute upper bridge chip groups, and the upper bridge chip groups distributed at opposite sides of the positive electrode connection region dc+ are independently controlled, respectively. Accordingly, a plurality of parallel-connected lower bridge chips 320 distributed at each side of the negative electrode connection region DC-constitute lower bridge chip groups, and upper bridge chip groups distributed at opposite sides of the negative electrode connection region DC-are independently controlled, respectively.

Wherein, each group of upper bridge chips corresponds to one gate signal connection region 1131, and the gates g of the upper bridge chips 310 in each group of upper bridge chips are connected to the gate signal connection region 1131 through the first upper conductive lines 51. Accordingly, each group of lower bridge chips corresponds to one gate signal connection region 1141, and the gates g of the respective lower bridge chips 320 in each group of lower bridge chips are correspondingly connected to the gate signal connection region 1141 through the first lower conductive lines 52.

In some embodiments, the gate signal connection region 1131 has a plurality of connection drop points 1136, each connection drop point 1136 is correspondingly connected to the gate g of one upper bridge chip 310 through the first upper conductive line 51, and the gate driving noise of each upper bridge chip 310 can be adjusted by adjusting the length of the first upper conductive line 51 and the position of the connection drop point 1136 between the upper bridge chips 310 in each group of upper bridge chips. Accordingly, the gate signal connection region 1141 has a plurality of connection drop points 1146, each connection drop point 1146 is correspondingly connected to the gate g of one lower bridge chip 320 through the first lower conductive line 52, and the gate driving noise of each lower bridge chip 320 can be adjusted by adjusting the length of the first lower conductive line 52 and the position of the connection drop point 1146 between each lower bridge chip 320 in each group of lower bridge chips.

In order to distinguish the positions of the connection landing points 1136 of the first upper conductive lines 51 connecting the respective upper bridge chips 310 on the gate signal connection region 1131 from the positions of the connection landing points 1146 of the first lower conductive lines 52 connecting the respective lower bridge chips 320 on the gate signal connection region 1141, the positions of the plurality of connection landing points 1136 on the gate signal connection region 1131 and the positions of the plurality of connection landing points 1146 on the gate signal connection region 1141 may be determined in advance by simulation, and corresponding marks may be made on the periphery of the landing point positions by, for example, laser light. Thus, during the manufacturing process, it is convenient to properly connect each upper bridge chip 310 to the corresponding connection drop 1136 using the first upper conductive line 51, and to properly connect each lower bridge chip 320 to the corresponding connection drop 1146 using the first lower conductive line 52.

The half-bridge structure 100 of the present application can shorten the path of each gate connection line in each chip group by independently controlling each upper bridge chip group and each lower bridge chip group, thereby reducing the gate driving circuit stray inductance, and can reduce the gate driving circuit stray inductance variability by adjusting the length and connection landing point of the first conductive line (specifically, including the first upper conductive line 51 and the first lower conductive line 52).

With continued reference to fig. 3, the plurality of signal connection regions 113 further includes a plurality of source signal connection regions 1132, and each group of upper bridge chips corresponds to one source signal connection region 1132. Accordingly, the plurality of signal connection regions 114 further includes a plurality of source signal connection regions 1142, and each group of lower bridge chips corresponds to one source signal connection region 1142.

In some embodiments, the sources s of one of the upper bridge chips 310 in each upper bridge chip group are correspondingly connected to the source signal connection region 1132 through the second upper conductive line 53, and the sources s of every adjacent two of the upper bridge chips 310 are connected through the third upper conductive line 55, so that the sources s of the upper bridge chips 310 in each upper bridge chip group are connected to the same source signal connection region 1132. Accordingly, the sources s of one of the lower bridge chips 320 in each lower bridge chip group are correspondingly connected to the source signal connection region 1142 through the second lower conductive lines 54, and the sources s of every adjacent two lower bridge chips 320 are connected through the third lower conductive lines 56, so that the sources s of the lower bridge chips 320 in each lower bridge chip group are connected to the same source signal connection region 1142.

The conductive wires may include, for example, but not limited to, aluminum wires, and the like. The conductive wires may be electrically connected to the corresponding structures through a bonding process.

In some embodiments, the half-bridge structure 100 of the present application may further include a temperature sensitive resistor R, where the temperature sensitive resistor R is disposed on the substrate and may be used to detect the overall chip temperature in the half-bridge structure 100. The temperature sensitive resistor R may comprise, for example, an NTC (Negative Temperature Coefficient ) temperature sensitive resistor. The plurality of signal connection regions 113 further includes signal connection regions 1133, 1134 of the temperature sensitive resistor 4, the temperature sensitive resistor R is connected to the signal connection region 1133, and the temperature sensitive resistor R is further connected to the signal connection region 1134 through the fourth conductive wire 57.

As shown in fig. 3, in some embodiments, temperature sensitive resistor R is located at the center line of positive electrode connection region dc+ and negative electrode connection region DC-.

According to the half-bridge structure 100, the temperature-sensitive resistor R is arranged on the central connecting line of the positive electrode connecting region DC+ and the negative electrode connecting region DC-, so that the temperature-sensitive resistor R is positioned closer to the central axis of the distribution of the upper bridge chip set 31 and the lower bridge chip set 32, and the arrangement mode of the temperature-sensitive resistor R, which is close to the symmetrical central axis of the distribution of the chips, can be beneficial to improving the junction temperature monitoring accuracy.

In some embodiments, the plurality of signal connection regions further includes monitor signal connection regions 1135, 1145 for connecting monitor signal terminals, the monitor signal connection region 1135 may be located at the first conductive region 111, and the monitor signal connection region 1145 may be located at the second conductive region 112.

As shown in fig. 3,4 and 5, the positive electrode connection region dc+ and the negative electrode connection region DC-are located substantially in the middle region of the substrate, and the alternating current connection region AC is disposed near the first end of the substrate.

In the embodiment where the substrates comprise a first substrate 1 and a second substrate 2, the positive connection region dc+ and the negative connection region DC-are located substantially in a middle region of the first substrate 1, the AC connection region AC is located near a first end of the first substrate 1, and the AC connection region AC is located in a second conductive region 112 of the first substrate 1.

In some embodiments, the signal connection regions 113 of the plurality of upper bridge chipsets 31 and the signal connection regions 1133, 1134 of the temperature-sensitive resistor R are distributed on a first side of the first substrate 1, and the signal connection region 114 of the lower bridge chipset 32 is distributed on a second side of the first substrate 1, where the first side is opposite to the second side and is adjacent to the first end.

Fig. 8 discloses a perspective view of a half-bridge structure 100 according to another embodiment of the present application. As shown in fig. 8, in some embodiments, the half-bridge structure 100 of the present application further includes a plastic enclosure 6. The plastic package 6 may be used to encapsulate the substrate and the chipset. After the half-bridge structure 100 is molded, at least a portion of each of the positive electrode connection region dc+, the negative electrode connection region DC-, the alternating current connection region AC, and the signal connection regions 113 and 114 is exposed outside the molded case 6, so that the power busbar and/or the signal terminal can be conveniently mounted from the outside.

In addition, the signal connection area is exposed outside the plastic package shell 6, so that convenience in selecting signal terminals is provided, different signal terminal shapes can be selected according to actual application requirements, and various connection modes are provided.

Fig. 9 discloses a schematic perspective view of a half-bridge structure 100 according to a further embodiment of the application. As shown in fig. 9, in some embodiments, the half-bridge structure 100 of the present application may further include a plurality of signal terminals 71, 72. The plurality of signal terminals 71, 72 are respectively connected to a plurality of signal connection areas 113, 114 exposed outside the plastic package 6.

Fig. 10 discloses a schematic perspective view of a half-bridge structure 100 according to yet another embodiment of the present application. As shown in fig. 10, in some embodiments, the half-bridge structure 100 of the present application may further include a positive dc bus 81, a negative dc bus 82, and an ac bus 83. The positive and negative DC bus bars 81 and 82 may be externally connected to the positive and negative electrode connection regions dc+ and DC-exposed outside the plastic package case 6, and the AC bus bar 83 may be externally connected to the AC connection region AC exposed outside the plastic package case 6.

Fig. 11 discloses a schematic perspective view of a positive dc busbar 81 and a negative dc busbar 82 according to an embodiment of the present application. As shown in fig. 11, in some embodiments, the positive dc busbar 81 has a first connection portion 811 and a first planar body portion 812, and the negative dc busbar 82 has a second connection portion 821 and a second planar body portion 822. The first connection portion 811 is for connection to the positive electrode connection region dc+, the second connection portion 821 is for connection to the negative electrode connection region DC-, the first planar main body portion 812 and the second planar main body portion 822 are overlapped with each other and are disposed at a distance, and an insulating material may be used for the distance region.

According to the half-bridge structure 100, the upper bridge chips 310 in the upper bridge chip set 31 are symmetrically arranged on the opposite sides of the positive electrode connection area DC+ respectively, the lower bridge chips 320 in the lower bridge chip set 32 are symmetrically arranged on the opposite sides of the negative electrode connection area DC-, and the middle layout mode of the positive electrode connection area DC+ and the negative electrode connection area DC-enables the positive direct current busbar 81 and the negative direct current busbar 82 to better realize lamination, so that the positive direct current busbar 81 and the negative direct current busbar 82 realize mutual inductance, and the system-level stray inductance is reduced.

In some embodiments, the first planar body portion 812 and the second planar body portion 822 have opposite first and second sides at the same end. The positive dc busbar 81 further has a first transition portion 813, and the first transition portion 813 connects the first connection portion 811 and the first side of the first planar main body portion 812; the negative dc bus 82 also has a second transition 823, the second transition 823 connecting the second connection 821 to a second side of the second planar body 822. The first transition portion 813 of the positive dc bus 81 and the second transition portion 823 of the negative dc bus 82 have different heights, so that the first planar body portion 812 of the positive dc bus 81 and the second planar body portion 822 of the negative dc bus 82 may be spaced apart from each other, and an insulating material may be used in the spaced apart region.

In some embodiments, the ac busbar 83 extends from a first end of the substrate, and the first planar body portion 812 of the positive dc busbar 81 and the second planar body portion 822 of the negative dc busbar 82 extend from a second end of the substrate, the second end being opposite the first end. That is, as shown in fig. 10, the ac busbar 83 extends from one end of the plastic package 6, and the first planar body portion 812 of the positive dc busbar 81 and the second planar body portion 822 of the negative dc busbar 82 extend from the opposite end of the plastic package 6.

It should be noted that, the product manufacturing end of the half-bridge structure 100 of the present application may only provide a module structure, such as the module structure shown in fig. 8, in which the signal terminals and the power bus bars are not yet mounted after plastic packaging, and the signal terminals and the power bus bars may be mounted again at the application end. Of course, the module structure shown in fig. 9 or fig. 10 may also be provided according to the requirements of the client at the application end, which is not limited herein.

The application also provides a power module 200. Fig. 12 discloses an overall structure of a power module 200 according to an embodiment of the application. As shown in fig. 12, the power module 200 of the present application includes three half-bridge structures 100 and a heat dissipation substrate 9 as described in the above embodiments, and the three half-bridge structures 100 are connected to the heat dissipation substrate 9.

Fig. 13 discloses a full-bridge circuit topology of a power module 200 according to one embodiment of the application. As shown in fig. 13, three chipsets L1, L2, L3 in the three half-bridge structures 100 form a full-bridge circuit. In each chipset, the positive electrode connection region dc+ is electrically connected to the drain d of the upper bridge chip 310, the source s of the upper bridge chip 310 is electrically connected to the drain d of the lower bridge chip 320, the negative electrode connection region DC-is electrically connected to the source s of the lower bridge chip 320, and the AC connection region AC is electrically connected to the source s of the upper bridge chip 310 and the drain d of the lower bridge chip 320, respectively.

The application further provides a vehicle. The vehicle includes a power module 200 as described above.

The power module 200 of the present application may have substantially similar advantageous effects to the half-bridge structure 100 described above by adopting the half-bridge structure 100 and the vehicle having the power module 200 according to the embodiments described above, and thus, will not be described herein.

The half-bridge structure of the power module, the power module and the vehicle provided by the embodiment of the application are described in detail. The half-bridge structure, the power module and the vehicle according to the embodiments of the present application are described herein by applying specific examples, and the description of the above embodiments is only for helping to understand the core idea of the present application, and is not intended to limit the present application. It should be noted that it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the spirit and principles of the application, which should also fall within the scope of the appended claims.

Claims (11)

1. A half-bridge structure of a power module, characterized in that: comprising the following steps:

The device comprises a substrate, wherein a positive electrode connection area, a negative electrode connection area and an alternating current connection area are arranged on the substrate; and

The chip set is arranged on the substrate and comprises an upper bridge chip set and a lower bridge chip set, wherein the upper bridge chip set comprises a plurality of upper bridge chips connected in parallel, and the lower bridge chip set comprises a plurality of lower bridge chips connected in parallel;

The upper bridge chips are symmetrically arranged on two opposite sides of the positive electrode connection area respectively, the lower bridge chips are symmetrically arranged on two opposite sides of the negative electrode connection area respectively, and the number of chips in the two symmetrically arranged areas is the same.

2. The half-bridge structure of a power module of claim 1, wherein: the substrate comprises a first substrate and a second substrate arranged on the first substrate, wherein the upper bridge chip set, the lower bridge chip set, the positive electrode connection area and the alternating current connection area are arranged on the first substrate, and the negative electrode connection area is arranged on the second substrate.

3. The half-bridge structure of the power module of claim 2, wherein: the first substrate comprises a first upper conductive layer, a first lower conductive layer and a first middle insulating layer positioned between the first upper conductive layer and the first lower conductive layer, the second substrate comprises a second upper conductive layer, a second lower conductive layer and a second middle insulating layer positioned between the second upper conductive layer and the second lower conductive layer, the first upper conductive layer comprises a first conductive area and a second conductive area which are mutually separated, wherein the positive electrode connection area is positioned in the first conductive area, the drains of a plurality of upper bridge chips are connected to the first conductive area, the drains of a plurality of lower bridge chips are connected to the second conductive area, the second lower conductive layer of the second substrate is connected to the second conductive area of the first substrate, and the negative electrode connection area is positioned in the second upper conductive layer.

4. A half-bridge structure of a power module as claimed in claim 3, characterized in that: the source electrodes of the upper bridge chips are respectively and electrically connected to the second conductive areas through independent upper metal sheets, and the source electrodes of the lower bridge chips are respectively and electrically connected to the second upper conductive layers of the second substrate through independent lower metal sheets.

5. The half-bridge structure of a power module of any one of claims 1 to 4, wherein: the positive electrode connection region and the negative electrode connection region are located in a middle region of the substrate, and the alternating current connection region is located near a first end of the substrate.

6. The half-bridge structure of a power module of claim 5, wherein: the substrate is further provided with a plurality of signal connection areas, wherein the plurality of signal connection areas of the upper bridge chip set are distributed on the first side edge of the first substrate, the plurality of signal connection areas of the lower bridge chip set are located on the second side edge of the first substrate, and the first side edge is opposite to the second side edge and is adjacent to the first end portion.

7. The half-bridge structure of the power module of claim 6, wherein: further comprises:

A plastic package housing for encasing the substrate and the chipset,

The positive electrode connecting area, the negative electrode connecting area, the alternating current connecting area and the signal connecting area are exposed outside the plastic package shell.

8. The half-bridge structure of the power module of claim 7, wherein: the plastic package further comprises a plurality of signal terminals, and the signal terminals are correspondingly connected to the signal connection areas exposed out of the plastic package shell.

9. The half-bridge structure of a power module of claim 8, wherein: the positive direct current busbar comprises a positive direct current busbar body and a negative direct current busbar body, wherein the positive direct current busbar body is provided with a first connecting portion and a first plane main body portion, the negative direct current busbar body is provided with a second connecting portion and a second plane main body portion, the first connecting portion is used for being connected to the positive electrode connecting area, the second connecting portion is used for being connected to the negative electrode connecting area, and the first plane main body portion and the second plane main body portion are mutually overlapped and are arranged at intervals.

10. A power module, characterized by: half-bridge structure comprising three power modules according to any of claims 1 to 9 and a heat-dissipating substrate, the three half-bridge structures being connected to the heat-dissipating substrate.

11. A vehicle, characterized in that: comprising a power module as claimed in claim 10.