CN118116903A

CN118116903A - Semiconductor structure and forming method thereof

Info

Publication number: CN118116903A
Application number: CN202211520992.1A
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-11-30
Filing date: 2022-11-30
Publication date: 2024-05-31

Abstract

A method of forming a semiconductor structure, wherein the method of forming comprises: providing a substrate; forming a first dielectric layer, a grid structure, a plurality of source-drain doped layers and a plurality of first conductive layers, wherein the source-drain doped layers are respectively positioned in the substrates at two sides of the grid structure, and the first conductive layers are respectively connected with the source-drain doped layers at the same side of the grid structure; forming a second dielectric layer on the first dielectric layer; forming a first conductive plug in the first dielectric layer and the second dielectric layer; forming a third dielectric layer on the second dielectric layer; and forming a second conductive layer in the third dielectric layer, and forming conductive structures in the second dielectric layer and the third dielectric layer, wherein the conductive structures comprise a second conductive plug and a third conductive layer positioned on the second conductive plug. The second conductive plug and the third conductive layer are formed simultaneously, so that the processing steps can be effectively reduced, the process difficulty is reduced, and meanwhile, the electrical connection between the second conductive plug and the third conductive layer is effectively improved, and the electrical performance of the semiconductor structure is further improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened.

To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; the gate structure also transitions from the original polysilicon gate structure to a metal gate structure in which the work function layer is capable of adjusting the threshold voltage of the semiconductor structure.

The semiconductor structure comprises a substrate, a gate structure arranged on the substrate, source and drain doped layers arranged in the substrate at two sides of the gate structure, and source and drain contact plugs arranged on the source and drain doped layers and used for realizing connection between the source and drain doped layers and an external circuit, wherein the quality of the formation of the source and drain contact plugs plays a vital role in the electrical performance of the semiconductor structure.

In addition, to further improve the integration of the semiconductor structure, an active gate Contact plug (Contact Over ACTIVE GATE, COAG) process is introduced. Compared with the traditional gate contact plug positioned above the gate structure of the isolation region, the COAG process can enable the gate contact plug to be positioned above the gate structure of the active region (ACTIVE AREA, AA) so that the integration level of the semiconductor structure is higher.

However, there are still a number of problems in the prior art COAG process.

Disclosure of Invention

The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, so as to reduce the process difficulty and improve the connection performance.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate, the gate structure extending along a first direction, the gate structure including a first region and a second region respectively adjacent to the first region along the first direction; the source-drain doping layers are positioned in the substrate at two sides of the grid structure; the first conductive layers are respectively connected with the source-drain doped layers positioned on the same side of the grid structure; the first dielectric layer is positioned on the substrate and covers the grid structure, the source-drain doping layers and the first conductive layers, and the first dielectric layer exposes the top surface of the first conductive layers; a second dielectric layer on the first dielectric layer; a first conductive plug within the first dielectric layer and the second dielectric layer, the first conductive plug in contact with the first region of the gate structure; a third dielectric layer on the second dielectric layer; a second conductive layer within the third dielectric layer; the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer arranged on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed electrical connection structures, and the second conductive plug is in contact with the first conductive layer.

Optionally, the method further comprises: and the etching stop layer is positioned between the first dielectric layer and the second dielectric layer.

Optionally, the method further comprises: and the lining layer is positioned in the second dielectric layer and covers part of the side wall of the first conductive plug.

Optionally, the material of the first conductive plug includes: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

Optionally, when the first conductive plug is copper, the method further includes: a first barrier layer located on sidewalls and a bottom surface of the first conductive plug.

Optionally, the material of the first barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

Optionally, the material of the second conductive layer includes: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

Optionally, when the material of the second conductive layer is copper, the method further includes: and a second barrier layer positioned on the side wall and the bottom surface of the second conductive layer.

Optionally, the material of the second barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

Optionally, the material of the conductive structure includes: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

Optionally, when the material of the conductive structure is copper, the method further includes: and a third barrier layer positioned on the side wall and the bottom surface of the conductive structure.

Optionally, the material of the third barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

Optionally, the substrate includes: the device comprises a substrate and a plurality of mutually separated fin parts positioned on the substrate, wherein the fin parts extend along a second direction, and the first direction is perpendicular to the second direction.

Optionally, the gate structure spans across a plurality of fin portions, and the plurality of source-drain doped layers are located in the fin portions on two sides of the gate structure.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a first dielectric layer, a gate structure, a plurality of source-drain doped layers and a plurality of first conductive layers, wherein the gate structure is positioned on the substrate, the gate structure extends along a first direction, the gate structure comprises a first region and a second region which is adjacent to the first region respectively along the first direction, the source-drain doped layers are positioned in the substrate at two sides of the gate structure respectively, the first conductive layers are connected with the source-drain doped layers positioned at the same side of the gate structure respectively, the first dielectric layer is positioned on the substrate, the first dielectric layer covers the gate structure, the source-drain doped layers and the first conductive layers, and the first dielectric layer exposes the top surface of the first conductive layer; forming a second dielectric layer on the first dielectric layer; forming a first conductive plug in the first dielectric layer and the second dielectric layer, wherein the first conductive plug is contacted with a first region of the gate structure; forming a third dielectric layer on the second dielectric layer; and forming a second conductive layer in the third dielectric layer, and forming a conductive structure in the second dielectric layer and the third dielectric layer, wherein the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer positioned on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed into an electric connection structure, and the second conductive plug is in contact with the first conductive layer.

Optionally, before forming the second dielectric layer, the method further includes: and forming an etching stop layer on the first dielectric layer, wherein the second dielectric layer is positioned on the etching stop layer.

Optionally, the forming method of the first conductive plug includes: forming a first mask structure on the second dielectric layer, wherein part of the top surface of the second dielectric layer is exposed by the first mask structure; etching the second dielectric layer by taking the first mask structure as a mask until the etching stop layer is exposed, and forming a first opening in the second dielectric layer; forming an inner liner layer on the side wall of the first opening; etching the etching stop layer and the first dielectric layer by taking the first mask structure and the inner liner layer as masks until the first area position of the grid structure is exposed, and forming a second opening in the etching stop layer and the first dielectric layer; the first conductive plug is formed within the first opening and the second opening.

Optionally, the forming method of the inner liner layer includes: forming a liner material layer on the side wall and the bottom surface of the first opening and the top surface of the first mask structure; and etching the lining material layer until the surfaces of the first mask structure and the etching stop layer are exposed, so as to form the lining layer.

Optionally, the forming process of the lining material layer includes: atomic layer deposition process.

Optionally, the forming method of the second conductive layer and the conductive structure includes: forming a second mask structure on the third dielectric layer, wherein part of the top surface of the third dielectric layer is exposed by the second mask structure; etching the third dielectric layer by the second mask structure until the surface of the first conductive plug is exposed, forming a third opening and a fourth opening in the third dielectric layer, wherein the third opening exposes the surface of the first conductive plug; etching the fourth opening to expose the second dielectric layer until the surface of the first conductive layer is exposed, forming a fifth opening in the second dielectric layer, wherein the fifth opening exposes the surface of the first conductive layer; the second conductive layer is formed in the third opening, and the conductive structure is formed in the fourth opening and the fifth opening.

Compared with the prior art, the technical scheme of the invention has the following advantages:

The semiconductor structure of the technical scheme of the invention comprises the following components: the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer arranged on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed electrical connection structures, and the second conductive plug is in contact with the first conductive layer. Because the second conductive plug and the third conductive layer are integrally formed, the processing steps can be effectively reduced, the process difficulty is reduced, and meanwhile, the electrical connection between the second conductive plug and the third conductive layer is effectively improved, and the electrical performance of the semiconductor structure is further improved.

In the method for forming a semiconductor structure according to the technical scheme of the invention, a second conductive layer is formed in the third dielectric layer, and a conductive structure is formed in the second dielectric layer and the third dielectric layer, wherein the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer positioned on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed electrical connection structures, and the second conductive plug is in contact with the first conductive layer. The second conductive plug and the third conductive layer are formed at the same time, so that the processing steps can be effectively reduced, the process difficulty is reduced, and meanwhile, the electrical connection between the second conductive plug and the third conductive layer is effectively improved, and the electrical performance of the semiconductor structure is further improved.

Drawings

Fig. 1 to 12 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, there are still a number of problems with the prior art COAG process. The following will specifically explain.

In the COAG process in the prior art, a conductive plug and a conductive layer which are electrically connected with a contact plug on a source-drain doped layer are manufactured independently by adopting two processes, so that the steps of the manufacturing process are increased, and the electrical connectivity between the conductive plug and the conductive layer is poor.

On the basis, the invention provides a semiconductor structure and a forming method thereof, a second conductive layer is formed in the third dielectric layer, a conductive structure is formed in the second dielectric layer and the third dielectric layer, the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer positioned on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed into an electric connection structure, and the second conductive plug is in contact with the first conductive layer. The second conductive plug and the third conductive layer are formed at the same time, so that the processing steps can be effectively reduced, the process difficulty is reduced, and meanwhile, the electrical connection between the second conductive plug and the third conductive layer is effectively improved, and the electrical performance of the semiconductor structure is further improved.

Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 1 and 2, fig. 2 is a schematic cross-sectional view taken along line A-A in fig. 1, providing a substrate.

In this embodiment, the substrate provides a process basis for the subsequent formation of the semiconductor structure.

In this embodiment, the step of providing the substrate includes: a substrate 100, and a plurality of mutually discrete fins 101 on the substrate 100, the fins 101 extending along a second direction Y.

In other embodiments, the substrate may also be a planar substrate, with the corresponding semiconductor structure being a planar transistor (MOSFET).

In other embodiments, the substrate further includes a plurality of suspended channel layers, the channel layers being spaced apart in a direction normal to a surface of the substrate, and the respective semiconductor structure being a fully-enclosed gate transistor (GAA).

In this embodiment, the substrate 100 is a silicon substrate.

In other embodiments, the material of the base may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the base may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.

In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 includes silicon.

With continued reference to fig. 1 and 2, in this embodiment, the substrate further includes: an isolation layer 102, wherein the isolation layer 102 covers part of the side wall of the fin 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin 101.

In this embodiment, the isolation layer 102 is a shallow trench isolation structure (shallowtrench isolation, STI), and the isolation layer 102 is used to electrically isolate the substrate from a gate structure formed later.

In this embodiment, the material of the isolation layer 102 includes silicon oxide.

Referring to fig. 3 and 4, fig. 3 is a top view of a semiconductor structure with a first dielectric layer omitted, fig. 4 is a schematic cross-sectional view along line B-B in fig. 3, a first dielectric layer 103, a gate structure 104, a plurality of source-drain doped layers 105, and a plurality of first conductive layers 106 are formed, the gate structure 104 is located on the substrate, the gate structure 104 extends along a first direction X, the gate structure 104 includes a first region I along the first direction X, and a second region II adjacent to the first region I, the plurality of source-drain doped layers 105 are located in the substrate on two sides of the gate structure 104, the first conductive layers 106 are connected to the plurality of source-drain doped layers 105 located on the same side of the gate structure 104, the first dielectric layer 103 is located on the substrate, the first dielectric layer 103 covers the gate structure 104, the plurality of source-drain doped layers 105, and the plurality of first conductive layers 106, and the first dielectric layer 103 exposes the top surface of the first conductive layers 106.

In this embodiment, the first direction X is perpendicular to the second direction Y.

In this embodiment, the gate structure 104 is located on the isolation layer 102, spans across the fin 101 and covers a portion of the top wall and a portion of the side wall of the fin 101, and the source-drain doped layers 105 are located in the fin 101 at two sides of the gate structure 104.

In this embodiment, the gate structure 104 is used to turn on or off the channel when the semiconductor structure is in operation.

In this embodiment, the material of the first dielectric layer 103 is an insulating material. The material of the first dielectric layer 103 specifically includes silicon oxide.

In this embodiment, the source-drain doped layer 105 is used to provide stress to the channel and increase the migration rate of carriers in the channel when the semiconductor structure is in operation.

When the semiconductor structure is used to form PMOS, the material of the source-drain doped layer 105 is P-type ion doped silicon germanium. Specifically, the P-type ions include: boron, gallium or indium. When the semiconductor structure is used to form an NMOS, the material of the source-drain doped layer 105 is silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include: phosphorus, arsenic or antimony.

In this embodiment, the gate structure 104 includes: a gate dielectric layer and a gate electrode layer (not shown).

The material of the gate layer is metal, and the metal material comprises: titanium nitride, tantalum nitride, titanium aluminide, tungsten, cobalt, titanium silicon nitride, aluminum, titanium, and tantalum.

In this embodiment, tungsten is used as the material of the gate layer.

In this embodiment, the first region I of the gate structure 104 is the active region (ACTIVE AREA, AA), and the first conductive plug can be subsequently formed on the first region I of the gate structure 104 by the COAG process, so that the integration level of the semiconductor structure is higher.

In this embodiment, the sidewall of the gate structure 104 is further formed with a sidewall layer 107. The sidewall layer 107 is used to electrically isolate the source-drain doped layer 105 from the gate structure 104, and also is used to reduce parasitic capacitance between the source-drain doped layer 105 and the gate structure 104.

In this embodiment, the sidewall layer 107 has a single-layer structure. In other embodiments, the sidewall layer may also be a stacked structure.

In this embodiment, the thickness of the first dielectric layer 103 determines the thickness of the first conductive layer 106.

The material of the first conductive layer 106 includes one or more of cobalt, tungsten, and ruthenium.

In this embodiment, cobalt is used as the material of the first conductive layer 106. The lower resistivity of cobalt is beneficial to improving the signal delay of the back-end RC, improving the processing speed of the semiconductor structure, reducing the resistance of the first conductive layer 106 and correspondingly reducing the power consumption.

Referring to fig. 5, the view directions of fig. 5 and fig. 4 are identical, and a second dielectric layer 108 is formed on the first dielectric layer 103.

In this embodiment, the material of the second dielectric layer 108 is an insulating material. The material of the second dielectric layer 108 specifically includes silicon oxide.

With continued reference to fig. 5, in this embodiment, the method further includes: an etch stop layer 115 is formed on the first dielectric layer 103, and the second dielectric layer 108 is located on the etch stop layer 115.

In this embodiment, the material of the etching stop layer 115 is different from the material of the first dielectric layer 103 and the material of the second dielectric layer 108, respectively.

In this embodiment, the material of the etching stop layer 115 includes silicon nitride.

Referring to fig. 6 to 8, fig. 7 is a schematic cross-sectional view along line C-C in fig. 6, and fig. 8 is a schematic cross-sectional view along line D-D in fig. 6, a first conductive plug 109 is formed in the first dielectric layer 103 and the second dielectric layer 108, and the first conductive plug 109 is in contact with the first region I of the gate structure 104.

In this embodiment, the method for forming the first conductive plug 109 includes: forming a first mask structure (not shown) on the second dielectric layer 108, the first mask structure exposing a portion of a top surface of the second dielectric layer 108; etching the second dielectric layer 108 by using the first mask structure as a mask until the etching stop layer 115 is exposed, and forming a first opening (not labeled) in the second dielectric layer 108; forming an inner liner 110 on a sidewall of the first opening; etching the etching stop layer 115 and the first dielectric layer 103 by using the first mask structure and the liner layer 110 as masks until the first region I of the gate structure 104 is exposed, and forming a second opening (not labeled) in the etching stop layer 115 and the first dielectric layer 103; the first conductive plug 109 is formed within the first opening and the second opening.

In this embodiment, the method for forming the liner layer 110 includes: forming a liner material layer (not shown) on sidewalls and bottom surfaces of the first opening and a top surface of the first mask structure; the liner material layer is etched back until the first mask structure and the surface of the etch stop layer 115 are exposed, forming the liner layer 110.

In this embodiment, the process for forming the lining material layer includes: atomic layer deposition process.

In this embodiment, the size of the first conductive plug 109 can be adjusted by the inner liner 110.

In this embodiment, the method of forming the first conductive plug 109 in the first opening and the second opening includes: forming a first conductive plug material layer (not shown) within the first opening, within the second opening, and on a surface of the second dielectric layer 108; and flattening the first conductive plug material layer until the top surface of the second dielectric layer 108 is exposed, so as to form the first conductive plug 109.

The materials of the first conductive plug 109 include: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

In this embodiment, the material of the first conductive plug 109 is tungsten. The lower resistivity of tungsten is beneficial to improving the signal delay of the back-end RC, improving the processing speed of the semiconductor structure, and simultaneously beneficial to reducing the resistance of the first conductive plug 109, thereby correspondingly reducing the power consumption.

In other embodiments, when copper is used as the material of the first conductive plug, in order to prevent metal contamination caused by diffusion of the copper material, a first barrier layer needs to be formed on the sidewall and the bottom surface of the first conductive plug, where the material of the first barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

In this embodiment, after the first conductive plug 109 is formed, the first mask structure is removed.

Referring to fig. 9 and 10, the directions of the views of fig. 9 and 7 are identical, and the directions of the views of fig. 10 and 8 are identical, and a third dielectric layer 111 is formed on the second dielectric layer 108.

In this embodiment, the material of the third dielectric layer 111 is an insulating material. The material of the third dielectric layer 111 specifically includes silicon oxide.

Referring to fig. 11 and 12, the view directions of fig. 11 and 9 are identical, the view directions of fig. 12 and 10 are identical, a second conductive layer 112 is formed in the third dielectric layer 111, and a conductive structure is formed in the second dielectric layer 108 and the third dielectric layer 111, the second conductive layer 112 is in contact with the first conductive plug 109, the conductive structure includes a second conductive plug 113, and a third conductive layer 114 on the second conductive plug 113, the second conductive plug 113 and the third conductive layer 114 are integrally formed as an electrical connection structure, and the second conductive plug 113 is in contact with the first conductive layer 106.

In this embodiment, the method for forming the second conductive layer 112 and the conductive structure includes: forming a second mask structure (not shown) on the third dielectric layer 111, the second mask structure exposing a portion of a top surface of the third dielectric layer 111; etching the third dielectric layer 111 with the second mask structure until the surface of the first conductive plug 109 is exposed, and forming a third opening (not labeled) and a fourth opening (not labeled) in the third dielectric layer 111, where the third opening exposes the surface of the first conductive plug 109; etching the fourth opening to expose the second dielectric layer 108 until the surface of the first conductive layer 106 is exposed, forming a fifth opening (not labeled) in the second dielectric layer 108, where the fifth opening exposes the surface of the first conductive layer 106; the second conductive layer 112 is formed in the third opening, and the conductive structures are formed in the fourth opening and in the fifth opening.

In this embodiment, the method for forming the second conductive layer 112 in the third opening and the conductive structure in the fourth opening and the fifth opening includes: forming a layer of conductive material (not shown) within the third opening, within the fourth opening, and within the fifth opening; and flattening the conductive material layer until the top surface of the third dielectric layer 111 is exposed, forming the second conductive layer 112 in the third opening, and forming the conductive structures in the fourth opening and the fifth opening.

The materials of the second conductive layer 112 include: one or more of copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride; the material of the conductive structure comprises: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

In this embodiment, copper is used as the material of the second conductive layer 112 and the material of the conductive structure.

In order to prevent metal contamination caused by diffusion of the copper material, a second barrier layer (not shown) is formed on the sidewall and bottom surface of the second conductive layer 112, and a third barrier layer (not shown) is formed on the sidewall and bottom surface of the conductive structure, and the second barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

In this embodiment, the second conductive plug 113 and the third conductive layer 114 are formed at the same time, so that the process steps can be effectively reduced, the process difficulty is reduced, and the electrical connection between the second conductive plug 113 and the third conductive layer 114 is effectively improved, thereby improving the electrical performance of the semiconductor structure.

Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 11 and fig. 12, which includes: a substrate; a gate structure 104 on the substrate, the gate structure 104 extending along a first direction X, the gate structure including a first region I and a second region II respectively adjacent to the first region I along the first direction X; a plurality of source-drain doped layers 105 located in the substrate at both sides of the gate structure 104; the first conductive layers 106 are respectively connected with the source-drain doped layers 105 positioned on the same side of the gate structure 104; a first dielectric layer 103 located on the substrate, wherein the first dielectric layer 103 covers the gate structure 104, the source-drain doped layers 105 and the first conductive layers 106, and the first dielectric layer 103 exposes the top surface of the first conductive layers 106; a second dielectric layer 108 on the first dielectric layer 103; a first conductive plug 109 located within the first dielectric layer 103 and the second dielectric layer 108, the first conductive plug 109 being in contact with the first region I of the gate structure 104; a third dielectric layer 111 on the second dielectric layer 108; a second conductive layer 112 located within the third dielectric layer 111; the second conductive layer 112 is in contact with the first conductive plug 109, the conductive structure includes a second conductive plug 113, and a third conductive layer 114 on the second conductive plug 113, the second conductive plug 113 and the third conductive layer 114 are in an integrally formed electrical connection structure, and the second conductive plug 113 is in contact with the first conductive layer 106.

In this embodiment, since the second conductive plug 113 and the third conductive layer 114 are integrally formed, the process steps can be effectively reduced, the process difficulty can be reduced, and the electrical connection between the second conductive plug 113 and the third conductive layer 114 can be effectively improved, so as to further improve the electrical performance of the semiconductor structure.

In this embodiment, further comprising: an etch stop layer 115 between the first dielectric layer 103 and the second dielectric layer 108.

In this embodiment, further comprising: an inner liner layer 110 located in the second dielectric layer 108, wherein the inner liner layer 110 covers a part of the sidewall of the first conductive plug 109.

In order to prevent metal contamination caused by diffusion of the copper material, a second barrier layer (not shown) is formed on the sidewall and bottom surface of the second conductive layer 112 and the sidewall and bottom surface of the conductive structure, and the material of the second barrier layer includes: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

In this embodiment, the substrate includes: the semiconductor device comprises a substrate 100 and a plurality of mutually separated fin parts 101 positioned on the substrate 100, wherein the fin parts 101 extend along a second direction Y, and the first direction X is perpendicular to the second direction Y.

In this embodiment, the gate structure 104 spans across a plurality of the fins 101, and the plurality of source-drain doped layers 105 are located in the fins 101 at two sides of the gate structure 104.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A substrate;

a gate structure on the substrate, the gate structure extending along a first direction, the gate structure including a first region and a second region respectively adjacent to the first region along the first direction;

the source-drain doping layers are positioned in the substrate at two sides of the grid structure;

The first conductive layers are respectively connected with the source-drain doped layers positioned on the same side of the grid structure; the first dielectric layer is positioned on the substrate and covers the grid structure, the source-drain doping layers and the first conductive layers, and the first dielectric layer exposes the top surface of the first conductive layers;

A second dielectric layer on the first dielectric layer;

A first conductive plug within the first dielectric layer and the second dielectric layer, the first conductive plug in contact with the first region of the gate structure;

A third dielectric layer on the second dielectric layer;

A second conductive layer within the third dielectric layer;

The second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer arranged on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed electrical connection structures, and the second conductive plug is in contact with the first conductive layer.

2. The semiconductor structure of claim 1, further comprising: and the etching stop layer is positioned between the first dielectric layer and the second dielectric layer.

3. The semiconductor structure of claim 1, further comprising: and the lining layer is positioned in the second dielectric layer and covers part of the side wall of the first conductive plug.

4. The semiconductor structure of claim 1, wherein the material of the first conductive plug comprises: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

5. The semiconductor structure of claim 4, wherein when the first conductive plug is copper, further comprising: a first barrier layer located on sidewalls and a bottom surface of the first conductive plug.

6. The semiconductor structure of claim 5, wherein the material of the first barrier layer comprises: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

7. The semiconductor structure of claim 1, wherein the material of the second conductive layer comprises: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

8. The semiconductor structure of claim 7, wherein when the material of the second conductive layer is copper, further comprising: and a second barrier layer positioned on the side wall and the bottom surface of the second conductive layer.

9. The semiconductor structure of claim 8, wherein the material of the second barrier layer comprises: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

10. The semiconductor structure of claim 1, wherein the material of the conductive structure comprises: copper, aluminum, tungsten, cobalt, ruthenium, and titanium nitride.

11. The semiconductor structure of claim 10, wherein when the material of the conductive structure is copper, further comprising: and a third barrier layer positioned on the side wall and the bottom surface of the conductive structure.

12. The semiconductor structure of claim 11, wherein the material of the third barrier layer comprises: titanium, titanium tungsten, tantalum nitride, or titanium nitride.

13. The semiconductor structure of claim 1, wherein the substrate comprises: the device comprises a substrate and a plurality of mutually separated fin parts positioned on the substrate, wherein the fin parts extend along a second direction, and the first direction is perpendicular to the second direction.

14. The semiconductor structure of claim 13, wherein the gate structure spans across the plurality of fins and the plurality of source-drain doped layers are located within the fins on both sides of the gate structure.

15. A method of forming a semiconductor structure, comprising:

Providing a substrate;

Forming a first dielectric layer, a gate structure, a plurality of source-drain doped layers and a plurality of first conductive layers, wherein the gate structure is positioned on the substrate, the gate structure extends along a first direction, the gate structure comprises a first region and a second region which is adjacent to the first region respectively along the first direction, the source-drain doped layers are positioned in the substrate at two sides of the gate structure respectively, the first conductive layers are connected with the source-drain doped layers positioned at the same side of the gate structure respectively, the first dielectric layer is positioned on the substrate, the first dielectric layer covers the gate structure, the source-drain doped layers and the first conductive layers, and the first dielectric layer exposes the top surface of the first conductive layer;

Forming a second dielectric layer on the first dielectric layer;

Forming a first conductive plug in the first dielectric layer and the second dielectric layer, wherein the first conductive plug is contacted with a first region of the gate structure;

Forming a third dielectric layer on the second dielectric layer;

And forming a second conductive layer in the third dielectric layer, and forming a conductive structure in the second dielectric layer and the third dielectric layer, wherein the second conductive layer is in contact with the first conductive plug, the conductive structure comprises a second conductive plug and a third conductive layer positioned on the second conductive plug, the second conductive plug and the third conductive layer are integrally formed into an electric connection structure, and the second conductive plug is in contact with the first conductive layer.

16. The method of forming a semiconductor structure of claim 15, further comprising, prior to forming the second dielectric layer: and forming an etching stop layer on the first dielectric layer, wherein the second dielectric layer is positioned on the etching stop layer.

17. The method of forming a semiconductor structure of claim 16, wherein the method of forming a first conductive plug comprises: forming a first mask structure on the second dielectric layer, wherein part of the top surface of the second dielectric layer is exposed by the first mask structure; etching the second dielectric layer by taking the first mask structure as a mask until the etching stop layer is exposed, and forming a first opening in the second dielectric layer; forming an inner liner layer on the side wall of the first opening; etching the etching stop layer and the first dielectric layer by taking the first mask structure and the inner liner layer as masks until the first area position of the grid structure is exposed, and forming a second opening in the etching stop layer and the first dielectric layer; the first conductive plug is formed within the first opening and the second opening.

18. The method of forming a semiconductor structure of claim 17, wherein the method of forming an inner liner layer comprises: forming a liner material layer on the side wall and the bottom surface of the first opening and the top surface of the first mask structure; and etching the lining material layer until the surfaces of the first mask structure and the etching stop layer are exposed, so as to form the lining layer.

19. The method of forming a semiconductor structure of claim 18, wherein the process of forming the liner material layer comprises: atomic layer deposition process.

20. The method of forming a semiconductor structure of claim 15, wherein the method of forming a second conductive layer and a conductive structure comprises: forming a second mask structure on the third dielectric layer, wherein part of the top surface of the third dielectric layer is exposed by the second mask structure; etching the third dielectric layer by the second mask structure until the surface of the first conductive plug is exposed, forming a third opening and a fourth opening in the third dielectric layer, wherein the third opening exposes the surface of the first conductive plug; etching the fourth opening to expose the second dielectric layer until the surface of the first conductive layer is exposed, forming a fifth opening in the second dielectric layer, wherein the fifth opening exposes the surface of the first conductive layer; the second conductive layer is formed in the third opening, and the conductive structure is formed in the fourth opening and the fifth opening.