CN118095168A

CN118095168A - Logic analyzer, system, method and computer readable storage medium

Info

Publication number: CN118095168A
Application number: CN202410458287.6A
Authority: CN
Inventors: 卢圣才; 刘伟; 王洪良
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-04-16
Filing date: 2024-04-16
Publication date: 2024-05-28
Anticipated expiration: 2044-04-16
Also published as: CN118095168B

Abstract

The invention discloses a logic analyzer, a system, a method and a computer readable storage medium, which relate to the field of data processing and aim to solve the problem that the signal state triggered continuously and repeatedly cannot be analyzed in the debugging process; the signal control module is used for determining a trigger condition and a target duration corresponding to the trigger signal, writing the trigger signal into the storage module after the target duration is delayed when the trigger signal is detected to meet the trigger condition, and generating a synchronous write enabling signal; the data control module is used for writing trigger data of the trigger signal in the observation time period into the storage module at the current moment of receiving the synchronous write-enabling signal; and the storage module is used for storing the trigger signals and the trigger data so that the upper computer can perform logic analysis based on the trigger signals and the trigger data. The invention can analyze the signal state triggered repeatedly for a continuous period of time in the debugging process, and has high flexibility and strong compatibility.

Description

Logic analyzer, system, method and computer readable storage medium

Technical Field

The present invention relates to the field of data processing, and in particular, to a logic analyzer, a logic analyzer system, a logic analyzer method, and a computer readable storage medium.

Background

In the logic design of an FPGA (Field Programmable GATE ARRAY ), it is generally required to observe the real-time state of signals inside the FPGA or observe the signal state of some signals at the trigger time by using some signals or some signal combinations as trigger conditions. The domestic FPGA manufacturer has a certain gap between the functions of EDA (Electronic Design Automation, electrical design automation) software compared with foreign FPGA manufacturers due to late starting, and similar tools, such as Debugger and chipwatcher, are provided, but at present, the two tools only support single triggering of signals and do not support multiple triggering of signals. In the debugging process, if the signal states corresponding to the continuous multiple triggers are to be compared, or the signal states which are triggered for a long time and multiple times are recorded, the signal states cannot be realized temporarily.

Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.

Disclosure of Invention

The invention aims to provide a logic analyzer, a logic analyzer system, a logic analyzer method and a computer readable storage medium, which can analyze signal states triggered repeatedly for a continuous period of time in a debugging process, and have high flexibility and high compatibility.

In order to solve the above technical problems, the present invention provides a logic analyzer, including:

the register module is used for storing the triggering parameter of at least one triggering signal;

The signal control module is used for determining a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter, writing the trigger signal into the storage module after the trigger signal is detected to meet the trigger condition and the target duration is delayed, and generating a synchronous write enabling signal;

The data control module is used for writing the trigger data of the trigger signal in the observation time period into the storage module at the current moment of receiving the synchronous write enabling signal; the starting time of the observation time period is the time when the trigger signal meets the trigger condition, and the cut-off time of the observation time period is the current time;

the storage module is used for storing the trigger signals and the trigger data so that the upper computer can perform logic analysis based on the trigger signals and the trigger data.

The register module comprises an attribute register, wherein the attribute register comprises a mode selection bit for storing a trigger mode parameter of the trigger signal, an enable bit for storing a trigger enable parameter of the trigger signal and an operation selection bit for storing a trigger operation parameter of the trigger signal;

the process of determining the triggering condition corresponding to the triggering signal based on the triggering parameter comprises the following steps:

and determining a trigger condition corresponding to the trigger signal based on the trigger mode parameter in the mode selection bit and/or the trigger enabling parameter in the enabling bit and/or the trigger operation parameter in the operation selection bit.

The trigger mode parameters comprise one or more of a first mode parameter corresponding to a rising edge trigger mode, a second mode parameter corresponding to a falling edge trigger mode, a third mode parameter corresponding to a high level trigger mode and a fourth mode parameter corresponding to a low level trigger mode.

The trigger operation parameters comprise one or more of first operation parameters corresponding to logical AND operation, second operation parameters corresponding to logical OR operation and third operation parameters corresponding to logical NOT operation.

The register module further comprises a global control register, wherein the global control register comprises an offset configuration bit for storing a trigger offset parameter of the trigger signal;

the process of determining the target duration corresponding to the trigger signal based on the trigger parameter comprises the following steps:

And determining the target duration corresponding to the trigger signal based on the trigger offset parameter in the offset configuration bit.

Wherein the global control register further comprises a trigger clear bit for storing a first clear parameter;

and the attribute register is used for responding to an attribute resetting instruction when the first clearing parameter in the trigger clearing bit is a parameter value corresponding to resetting, and executing attribute resetting operation on the mode selection bit, the enabling bit and the operation selection bit.

Wherein the global control register further comprises a global enable control bit for storing a global enable parameter;

The signal control module is specifically configured to determine a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter when the global enable parameter in the global enable control bit is a parameter value corresponding to global enable, and write the trigger signal into the storage module after the target duration is delayed when the trigger signal is detected to satisfy the trigger condition, and generate a synchronous write enable signal.

Wherein the register module further comprises a status register comprising a count bit for storing a write cycle count value;

The global control register further includes a period configuration bit for storing a trigger period parameter of the trigger signal;

The signal control module is further configured to determine a trigger period count value according to a trigger period parameter in the period configuration bit, after the trigger signal is written into the storage module after the target duration is delayed, increment a write count value of the write counter by 1, increment the write period count value of the write period counter by 1 when the write count value reaches the trigger period count value, and write the write period count value into a count bit of the status register, so that the upper computer can read the trigger signal and the trigger data from the storage module when the write period count value in the status register meets a reading condition.

And the signal control module is further used for stopping writing the trigger signal into the storage module and stopping outputting the write enable signal to the data control module when the write cycle count value meets the write stop condition.

The signal control module is further configured to determine whether the writing cycle count value is equal to a preset threshold, if yes, determine that the writing cycle count value meets the writing stopping condition, and if not, determine that the writing cycle count value does not meet the writing stopping condition; the preset threshold is determined based on the storage depth of the storage module.

The process of reading the trigger signal and the trigger data from the storage module when the upper computer determines that the writing period count value in the status register meets the reading condition comprises the following steps:

and when the upper computer judges that the writing period count value in the state register meets the reading condition, determining a maximum reading address based on the writing period count value, and reading a trigger signal and trigger data according to the maximum reading address in the storage module.

The register module further comprises a read control register, wherein the read control register comprises address bits for storing a current read address and read enable control bits for storing read enable parameters;

the logic analyzer further comprises a read control module, wherein the read control module is used for reading the trigger signal and the trigger data from the storage module according to the current read address in the address bits of the read control register when the read enabling control bit of the read control register is a parameter value corresponding to enabling.

When the upper computer determines that the writing period count value in the state register meets the reading condition, determining a maximum reading address based on the writing period count value, and reading a trigger signal and trigger data according to the maximum reading address in the storage module, wherein the process comprises the following steps:

And when the upper computer judges that the writing period count value in the state register meets the reading condition, determining a maximum reading address based on the writing period count value, and writing the current reading address into the address bit in the reading control register so as to read the trigger signal and the trigger data according to the current reading address in the storage module until the current reading address is the maximum reading address.

The read control register further comprises a first storage space and a second storage space;

The read control module is further configured to store the trigger signal to the first storage space and store the trigger data to the second storage space after the trigger signal and the trigger data are read from the storage module according to a current read address in address bits of the read control register, so that the upper computer reads the trigger signal from the first storage space and reads the trigger data from the second storage space.

Wherein the global control register further comprises a capture clear bit for storing a second clear parameter;

The read control register is further configured to reset the first storage space, the second storage space, the address bits, and the read enable control bits in response to a capture reset instruction when the second clear parameter in the capture clear bit is a parameter value corresponding to a reset.

The logic analyzer further comprises an interface conversion module, wherein the interface conversion module is used for carrying out first protocol conversion on the trigger parameters sent by the upper computer, and carrying out second protocol conversion on the trigger signals and the trigger data in the register module.

The storage module comprises a first storage and a second storage;

the signal control module is specifically configured to determine a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter, and when detecting that the trigger signal meets the trigger condition, write the trigger signal into the first memory after delaying the target duration, and generate a synchronous write enable signal;

The data control module is specifically configured to write trigger data of the trigger signal in an observation period into the second memory at a current time when the synchronous write enable signal is received.

The first memory is a dual-port random access memory built based on a register or a distributed random access memory;

the second memory is a block random access memory.

In order to solve the technical problem, the present invention further provides a logic analysis system, including:

The upper computer is used for sending triggering parameters of at least one triggering signal and carrying out logic analysis based on the triggering signal and triggering data corresponding to the triggering signal;

A logic analyser as claimed in any preceding claim.

In order to solve the above technical problems, the present invention further provides a logic analysis method, which is applied to the logic analyzer as described in any one of the above, and the logic analysis method includes:

storing, by a register module, a trigger parameter of at least one trigger signal;

determining a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter through a signal control module, and writing the trigger signal into a storage module after delaying the target duration when the trigger signal is detected to meet the trigger condition, and generating a synchronous write enabling signal;

Writing trigger data of the trigger signal in an observation time period into the storage module by a data control module at the current moment of receiving the synchronous write enabling signal; the starting time of the observation time period is the time when the trigger signal meets the trigger condition, and the cut-off time of the observation time period is the current time;

And storing the trigger signal and the trigger data through the storage module so that the upper computer performs logic analysis based on the trigger signal and the trigger data.

To solve the above technical problem, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the logic analysis method as described above.

The invention provides a logic analyzer, which is characterized in that trigger parameters corresponding to trigger signals are written in a register module, the trigger signals and trigger data to be observed can be flexibly and conveniently adjusted by utilizing parameterization design, a signal control module determines trigger conditions and target time length according to the trigger parameters, when trigger signals meeting the trigger conditions exist, the trigger signals are written in a storage module after the target time length is delayed, and the trigger data corresponding to the trigger signals are written in the storage module by a synchronous control data control module, so that a subsequent upper computer can analyze signal triggers for a plurality of times in a continuous period of time, and the logic analyzer can be transplanted on various platforms, and has high flexibility and strong compatibility. The invention also provides a logic analysis system, a logic analysis method and a computer readable storage medium, which have the same beneficial effects as the logic analyzer.

Drawings

For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a first logic analyzer according to the present invention;

FIG. 2 is a schematic diagram of a second logic analyzer according to the present invention;

FIG. 3 is a schematic diagram of an attribute register according to the present invention;

FIG. 4 is a schematic diagram of a global control register according to the present invention;

FIG. 5 is a schematic diagram of a third logic analyzer according to the present invention;

FIG. 6 is a schematic diagram of a fourth logic analyzer according to the present invention;

FIG. 7 is a schematic diagram of a fifth logic analyzer according to the present invention;

FIG. 8 is a schematic diagram of a sixth logic analyzer according to the present invention;

FIG. 9 is a schematic diagram of a logic analysis system according to the present invention;

FIG. 10 is a flowchart illustrating a logic analysis method according to the present invention;

fig. 11 is a schematic structural diagram of a computer readable storage medium according to the present invention.

Detailed Description

The core of the invention is to provide a logic analyzer, a system, a method and a computer readable storage medium, which can analyze signal states triggered repeatedly for a continuous period of time in the debugging process, and have high flexibility and strong compatibility.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first logic analyzer according to the present invention, the logic analyzer includes:

a register module 1 for storing trigger parameters of at least one trigger signal;

The signal control module 2 is used for determining a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter, writing the trigger signal into the storage module 4 after the trigger signal is detected to meet the trigger condition and the target duration is delayed, and generating a synchronous write enabling signal;

The data control module 3 is used for writing trigger data of the trigger signal in the observation time period into the storage module 4 at the current moment of receiving the synchronous write enable signal; the starting time of the observation time period is the time when the trigger signal meets the trigger condition, and the cut-off time of the observation time period is the current time;

And the storage module 4 is used for storing the trigger signals and the trigger data so that the upper computer can perform logic analysis based on the trigger signals and the trigger data.

In this embodiment, the logic analyzer may be implemented by an FPGA, and includes a register module 1, a signal control module 2, a data control module 3, and a storage module 4, where the register module 1 is configured to store a trigger parameter of at least one trigger signal to be observed sent by an upper computer, where the trigger signal to be observed is any signal of any design circuit logic existing in the FPGA, and the trigger parameter includes, but is not limited to, a trigger attribute parameter, a trigger control parameter, and the like.

It will be appreciated that the register module 1 comprises a plurality of registers having different functions, each of which can store at least one trigger parameter of at least one trigger signal. The signal control module 2 and the data control module 3 are both in logic connection with a design circuit in the FPGA so as to acquire trigger signals and trigger data corresponding to the design circuit logic. The signal control module 2 is connected with each register in the register module 1 to acquire trigger parameters stored in each register, and determines a trigger condition and a target duration corresponding to each trigger signal to be observed based on all the trigger parameters. For example, assuming that the signal state at the time of falling edge triggering needs to be analyzed, the triggering condition is falling edge triggering, that is, when the falling edge of the triggering signal is detected, the triggering signal is judged to meet the triggering condition, and triggering data corresponding to the triggering signal is monitored for subsequent analysis.

The target duration is the duration of delay sending the trigger signal meeting the trigger condition and the trigger data thereof from the trigger time, starting timing when the trigger signal is detected to meet the trigger condition, and writing the trigger signal into the storage module 4 after the timing time reaches the target duration, and generating the synchronous write enabling signal. After receiving the synchronous write enable signal, the data control module 3 writes trigger data corresponding to the trigger signal in an observation time period from the trigger time to the current time into the storage module 4, and because the trigger signal and the trigger data in the embodiment are written after delaying the target time, the trigger data written into the storage module 4 in the embodiment is not only the trigger data at the trigger time, but also the trigger data before and after the trigger time, and simultaneously, the trigger signal and the trigger data corresponding to each time satisfying the trigger condition are stored into the storage module 4 first, so that the subsequent upper computer can analyze the signal state of continuous multiple triggers, and the defect of the existing electrical design automation software function is solved.

It can be seen that, in this embodiment, by writing the trigger parameter corresponding to the trigger signal in the register module, the trigger signal to be observed and the trigger data can be adjusted more flexibly and conveniently by using the parameterized design, the signal control module determines the trigger condition and the target duration according to the trigger parameter, when the trigger signal meeting the trigger condition exists, the trigger signal is written into the storage module after the target duration is delayed, and the trigger data corresponding to the trigger signal is written into the storage module by the synchronous control data control module, so that the subsequent upper computer can analyze the signal trigger for a plurality of times in a continuous period of time, and the system can be transplanted on various platforms, and has high flexibility and strong compatibility.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a second logic analyzer according to the present invention, where the logic analyzer is based on the above embodiments:

In an exemplary embodiment, the register module 1 includes an attribute register 11, the attribute register 11 including a mode selection bit for storing a trigger mode parameter of a trigger signal, an enable bit for storing a trigger enable parameter of the trigger signal, an operation selection bit for storing a trigger operation parameter of the trigger signal;

In this embodiment, the register module 1 includes an attribute register 11, where the attribute register 11 is used to store a trigger attribute parameter of a trigger signal, the trigger attribute parameter is a parameter used to determine a trigger condition, and referring to fig. 3, a 0 bit of the attribute register 11 is an enable bit, and 2:1, namely 1-2 bits are mode selection bits, 4:3, that is, 3-4 bits are operation selection bits, the upper computer writes the trigger mode parameters and/or the enabling parameters and/or the trigger operation parameters of each trigger signal to be observed into the bits corresponding to the attribute register 11 corresponding to the trigger signal in turn, when there are a plurality of trigger signals to be observed, as shown in fig. 3, the number of the attribute registers 11 is also correspondingly plurality, and in fig. 3, the attribute register of signal 0 corresponding to the signal 0 and the attribute register of signal 1 corresponding to the signal N corresponding to the signal … … are shown, and the control module 2 determines the trigger condition of the trigger signal according to the attribute trigger parameters stored in each attribute register 11.

The triggering mode parameters include, but are not limited to, one or more of a first mode parameter corresponding to a rising edge triggering mode, a second mode parameter corresponding to a falling edge triggering mode, a third mode parameter corresponding to a high level triggering mode, and a fourth mode parameter corresponding to a low level triggering mode, and the triggering operation parameters include one or more of a first operation parameter corresponding to a logical AND operation, a second operation parameter corresponding to a logical OR operation, and a third operation parameter corresponding to a logical NOT operation.

The enabling parameter is used for determining the validity of the trigger mode parameter and the trigger operation parameter, and for example, assuming that the enabling parameter is 1, the current trigger condition is indicated as valid rising edge trigger, and the first mode parameter is stored in a first attribute register corresponding to the first trigger signal s 1; assuming that the first attribute register corresponding to the first trigger signal s1 stores the third mode parameter and the first operation parameter, the enabling parameter is 1, and the second attribute register corresponding to the second trigger signal s2 stores the third mode parameter and the first operation parameter, it is indicated that the current trigger condition is valid when the phases of the first trigger signal s1 and the second trigger signal s2 are 1.

In an exemplary embodiment, the register module 1 further comprises a global control register 12, the global control register 12 comprising an offset configuration bit for storing a trigger offset parameter of the trigger signal;

In this embodiment, the register module 1 further includes a global control register 12, where the global control register 12 includes an offset configuration bit and a period configuration bit, where the offset configuration bit is used to store a trigger offset parameter, the period configuration bit is used to store a trigger period parameter, and the upper computer writes the trigger offset parameter into the offset configuration bit in the global control register 12 and writes the trigger period parameter into the period configuration bit. The signal control module 2 determines a target duration corresponding to each trigger period according to the offset configuration parameters, so as to realize offset transmission in each trigger period. For example, assuming that the offset configuration parameter is 10ms, the target period may be set to 10ms, i.e., the trigger signal and the trigger data are written to the memory module 4 within each trigger period with a delay of 10ms from the trigger timing (i.e., the timing at which the trigger signal satisfies the trigger condition). It can be understood that, in this embodiment, the trigger signal and the trigger data are written into the storage module 4 after each trigger period is delayed by the target duration, so that the trigger data written into the storage module 4 can represent the state of the trigger signal in a continuous period of time, so that the subsequent upper computer can analyze the trigger signal conveniently.

In an exemplary embodiment, global control register 12 also includes a trigger clear bit for storing a first clear parameter;

And an attribute register 11 for performing an attribute reset operation on the mode selection bit, the enable bit, and the operation selection bit in response to an attribute reset instruction when the first clearing parameter in the trigger clearing bit is a parameter value corresponding to reset.

In this embodiment, the global control register 12 further includes a trigger clearing bit, the upper computer writes a first clearing parameter into the trigger clearing bit, the first clearing parameter includes a first parameter value corresponding to a response attribute reset instruction and a second parameter value corresponding to a non-response attribute reset instruction, when the trigger clearing bit in the global control register 12 is the first parameter value, the parameter values of each bit in the attribute register 11 are reset, so that the parameter values of each bit are reset to an initial value, and in response to the attribute reset instruction, the attribute register 11 can be used for attribute configuration of other trigger signals to be observed.

In an exemplary embodiment, global control register 12 also includes global enable control bits for storing global enable parameters;

The signal control module 2 is specifically configured to determine a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter when the global enable parameter in the global enable control bit is a parameter value corresponding to global enable, and write the trigger signal into the storage module 4 after the target duration is delayed when the trigger signal is detected to satisfy the trigger condition, and generate a synchronous write enable signal.

In this embodiment, the global control register 12 further includes a global enable control bit for storing a global enable parameter, the upper computer writes the global enable parameter into the global enable control bit in the global control register 12, and when detecting that the global enable parameter is a parameter value corresponding to global enable, the signal control module 2 executes subsequent calculation operations, and if detecting that the global enable parameter is not a parameter value corresponding to global enable, no signal observation is required, then no subsequent calculation is required. Referring to FIG. 4, global control register 12 is a 32-bit register, wherein 0 bit is a global control enable bit, 1 bit is a trigger clear bit, 2 bits are capture clear bits, 15:3, 3 to 15 bits are offset configuration bits, 31:16, i.e., 16-31 bits, are the periodic configuration bits.

In this embodiment, the register module 1 utilizes a parameterized design, so that the trigger signal and the trigger data can be modified more flexibly and conveniently.

In an exemplary embodiment, referring to fig. 5, the register module 1 further includes a status register 13, the status register 13 including a count bit for storing a write cycle count value;

the global control register 12 also includes a period configuration bit for storing a trigger period parameter of the trigger signal;

The signal control module 2 is further configured to determine a trigger period count value according to the trigger period parameter in the period configuration bit, after writing the trigger signal into the storage module 4 after delaying the target period, increment a write count value of the write counter by 1, and increment the write period count value of the write period counter by 1 when the write count value reaches the trigger period count value, and write the write period count value into the count bit of the status register 13, so that the host computer reads the trigger signal and the trigger data from the storage module 4 when determining that the write period count value in the status register 13 satisfies the reading condition.

It can be understood that after the trigger signal and the trigger data are written into the storage module 4, the upper computer can read the trigger signal and the trigger data stored in the storage module 4 according to a preset reading rule, and the preset reading rule can be one-time reading or multiple-time reading, and can be set according to actual engineering requirements, which is not limited herein.

In order to facilitate the host computer to determine whether data can be read from the storage module 4, the register module 1 of the present embodiment further includes a status register 13, the status register 13 including a count bit for storing a write cycle count value written by the signal control module 2. In this embodiment, the initial value of the writing period count value and the initial value of the writing period count value are both 0, the signal control module 2 may determine the triggering period count value according to the triggering period parameter, after writing the triggering signal into the storage module 4 each time, increment the writing period count value by 1, if the writing period count value is equal to the preset triggering period count value, complete the writing operation of one triggering period, increment the writing period count value by 1, and write the current writing period count value into the count bit of the status register 13, and then circulate in this way until the writing period count value is equal to the preset threshold value, where the preset threshold value is determined according to the storage depth of the storage module 4, to determine that the writing period count value meets the condition of stopping writing.

The upper computer judges how many times the triggering writing period is completed according to the writing period counting value in the counting bit of the state register 13, so as to judge whether the data can be read from the storage module 4, specifically, the upper computer can determine the target counting value according to the current observation requirement, and when the writing period counting value reaches the target counting value, the upper computer can start to read the data from the storage module 4.

In an exemplary embodiment, the process of reading the trigger signal and the trigger data from the memory module 4 when the upper computer determines that the write cycle count value in the status register 13 satisfies the reading condition includes:

When the upper computer determines that the writing cycle count value in the status register 13 satisfies the reading condition, the maximum reading address is determined based on the writing cycle count value so that the trigger signal and the trigger data are read at the maximum reading address in the memory module 4. In this embodiment, the upper computer may determine the maximum read address according to the write cycle count value in the status register 13, and traverse the data stored in the read storage module 4 according to the maximum read address during reading, so as to read the data corresponding to the maximum read address and the previous data.

In an exemplary embodiment, referring to fig. 6, the register module 1 further includes a read control register 14, where the read control register 14 includes address bits for storing a current read address and read enable control bits for storing a read enable parameter;

The logic analyzer further comprises a read control module 5 for reading the trigger signal and the trigger data from the memory module 4 according to the current read address in the address bits of the read control register 14 when the read enable control bit of the read control register 14 is the parameter value corresponding to the enable.

In this embodiment, the register module 1 further includes a read control register 14, and the upper computer determines a current read address according to the maximum read address, writes the current read address into an address bit in the read control register 14, and then writes a parameter value corresponding to the enable into a read enable control bit of the read register.

When the upper computer determines that the writing cycle count value in the status register 13 meets the reading condition, the maximum reading address is determined based on the writing cycle count value, and the current reading address is written into the address bit in the reading control register 14, so that the trigger signal and the trigger data are read according to the current reading address in the storage module 4 until the current reading address is the maximum reading address.

Specifically, the logic analyzer further comprises a read control module 5, and the read control module 5 is used for completing conversion from an APB (ADVANCED PERIPHERAL Bus ) interface to a read-write interface of a common RAM (Random Access Memory ) and mainly completing the read operation of the RAM. It can be understood that when the read control module 5 detects that the read enable control bit in the read control register 14 is a parameter value corresponding to the enable, the trigger signal and the trigger data are read from the storage module 4 according to the current read address in the address bit, so as to complete one-time data reading operation, and the upper computer sets the next read address until the maximum read address.

In an exemplary embodiment, read control register 14 further includes a first memory space and a second memory space;

The read control register 5 is further configured to store the trigger signal into the first storage space and the trigger data into the second storage space after the trigger signal and the trigger data are read from the storage module 4 according to the current read address in the address bits of the read control register 14, so that the host computer reads the trigger signal from the first storage space and the trigger data from the second storage space.

In this embodiment, the read control register 14 further includes two independent storage spaces for storing the trigger signal and the trigger data respectively, and further, the read control module 5 includes a first read control unit 51 and a second read control unit 52, where the first read control unit 51 reads the trigger signal from the storage module 4, stores the trigger signal in the first storage space, the second read control unit 52 reads the trigger data from the storage module 4 according to the current read address, stores the trigger data in the second storage space, and the upper computer can read all the data buffered in different storage spaces at one time through the APB interface, so as to improve the reading efficiency. Wherein the first memory space and the second memory space may be implemented by a FIFO (First Input First Output, first in first out) memory.

And the upper computer caches, processes, extracts and redraws the waveforms of the trigger signals and the trigger data acquired from the first storage space and the second storage space, so that subsequent analysis is performed.

In an exemplary embodiment, global control register 12 also includes a capture clear bit for storing a second clear parameter;

the read control register 14 is further configured to reset the first memory space, the second memory space, the address bits, and the read enable control bits in response to the capture reset instruction when the second clear parameter in the capture clear bit is a parameter value corresponding to the reset.

In this embodiment, the global control register 12 further includes a capture clear bit, where the capture clear bit is used to store a second clear parameter, where the second clear parameter includes a first parameter value corresponding to a capture reset instruction and a second parameter value corresponding to a non-capture reset instruction, and when the second clear parameter stored in the capture clear bit in the global control register 12 is the first parameter value, a capture reset operation is performed on the read control register 14, and signals, data, and addresses stored in the read control register 14 are cleared, so as to implement resetting of the first storage space, the second storage space, the address bits, and the read enable control bits.

In an exemplary embodiment, referring to fig. 7, the logic analyzer further includes an interface conversion module 6, configured to perform a first protocol conversion on the trigger parameter sent by the host computer, and perform a second protocol conversion on the trigger signal and the trigger data in the register module 1.

In this embodiment, the logic analyzer further includes an interface conversion module 6, and the interface conversion module 6 is used to perform protocol conversion on data transmitted between the host computer and the register module 1, where the logic analyzer may communicate with the host computer through an external interface such as a UART (Universal Asynchronous Receiver/Transmitter ) interface or a JTAG (Joint Test Action Group, joint test working group) interface, and the interface conversion module 6 mainly implements protocol conversion of the UART-APB, or protocol conversion of the JTAG-APB, in this embodiment, taking the external interface as a UART interface, determining the protocol conversion from UART to APB as a first protocol conversion, determining the protocol conversion from APB to UART as a second protocol conversion, and other interface protocols, and the same.

Of course, the external interface may also select a high-speed interface such as USB (Universal Serial Bus ), ETHERNET (ETHERNET) interface or PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed serial computer expansion bus standard) with higher speed and bandwidth, so as to improve the data communication rate, and the interface conversion module 6 may adaptively adjust the interface protocol converted by the interface conversion module.

In an exemplary embodiment, referring to fig. 8, the memory module 4 includes a first memory 41 and a second memory 42;

The signal control module 2 is specifically configured to determine a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter, and when detecting that the trigger signal meets the trigger condition, write the trigger signal into the first memory 41 after delaying the target duration, and generate a synchronous write enable signal;

the data control module 3 is configured to write trigger data of the trigger signal in the observation period into the second memory 42 at the current moment when the synchronous write enable signal is received.

In this embodiment, the storage module 4 includes two memories, namely a first memory 41 and a second memory 42, where the first memory 41 may be used to store a trigger signal with a smaller bit width, and the second memory 42 may be used to store trigger data with a larger bit width, so that when the subsequent upper computer reads data, the read address may be better distinguished, and the read efficiency may be improved.

Correspondingly, the signal control module 2 writes the trigger signal into the first memory 41, the data control module 3 synchronously writes the trigger data into the second memory 42, the first read control unit 51 reads the trigger signal from the first memory 41, and the second read control unit 52 reads the trigger data from the second memory 42.

The first memory 41 and the second memory 42 may be selected from memories with the same category, or may be selected from memories with different categories, for example, the first memory 41 and the second memory 42 may be implemented by selecting block RAM, or, of course, the first memory 41 and the second memory 42 may be combined according to the size of resources used in actual engineering.

In an exemplary embodiment, the first memory 41 is a dual-port random access memory built based on registers or a distributed random access memory; the second memory 42 is a block random access memory.

In this embodiment, in order to reduce the occupation of the block RAM resources in the system, the first memory 41 for storing the trigger signal with smaller bit width may be a register or a dual-port RAM designed for a distributed random access RAM, and the second memory 42 for storing the larger bit width may be a dual-port RAM designed for the block RAM in the system.

In summary, the invention realizes an internal logic analyzer based on FPGA (Field Programmable GATE ARRAY ), in the process of FPGA logic design and related SOC (System on Chip) development and debugging, related time sequence waveform diagrams triggered by continuous and repeated signals are always needed to be observed and compared, then partial EDA software has imperfect functions in this aspect and only supports single signal triggering.

In a second aspect, referring to fig. 9, fig. 9 is a schematic structural diagram of a logic analysis system according to the present invention, where the logic analysis system includes:

the upper computer 71 is configured to send a trigger parameter of at least one trigger signal, and perform logic analysis based on the trigger signal and trigger data corresponding to the trigger signal;

A logic analyzer 72 as described in any of the embodiments above.

In this embodiment, the upper computer 71 firstly sets the trigger attribute parameters (enable, trigger mode, trigger operation) of each trigger signal, secondly sets the trigger offset and trigger period in the global control register, and finally turns on the global trigger enable switch, i.e. writes the corresponding trigger parameters into the register in the register module of the logic analyzer 72.

The signal control module calculates a trigger condition according to the trigger attribute parameter set by the upper computer 71, and sets a corresponding delay parameter (target duration) and a trigger period count value according to the trigger offset parameter and the trigger period parameter, and waits for signal triggering.

When the trigger is to be triggered, the delayed trigger signals and trigger data are synchronously written into the corresponding dual-port RAM, meanwhile, the write count value is increased by one until the preset trigger period count value is reached, the write operation of one trigger period is completed, the write count period is increased by 1, and the write operation is synchronized into the state register. The cycle is thus completed until all cycles trigger a write operation.

The upper computer 71 judges how many cycles of trigger writing operation are finished currently according to the writing cycle count value in the status register, further determines the maximum read dual-port RAM address, traverses and reads the address, caches the trigger data in the RAM to read the corresponding address of the control register, and then sends the corresponding address to the upper computer 71, and the upper computer 71 completes caching, processing, extraction and waveform redrawing.

In a third aspect, referring to fig. 10, fig. 10 is a flowchart illustrating steps of a logic analysis method according to the present invention, which is applied to a logic analyzer as described in any one of the above, the logic analysis method includes:

s101: storing, by a register module, a trigger parameter of at least one trigger signal;

S102: determining a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter through a signal control module, writing the trigger signal into a storage module after the target duration is delayed when the trigger signal is detected to meet the trigger condition, and generating a synchronous write enabling signal;

S103: writing trigger data of the trigger signal in an observation time period into the storage module at the current moment of receiving the synchronous write-enable signal through the data control module; the starting time of the observation time period is the time when the trigger signal meets the trigger condition, and the cut-off time of the observation time period is the current time;

S104: and the storage module is used for storing the trigger signals and the trigger data so that the upper computer can perform logic analysis based on the trigger signals and the trigger data.

In an exemplary embodiment, the register module includes an attribute register including a mode select bit for storing a trigger mode parameter of the trigger signal, an enable bit for storing a trigger enable parameter of the trigger signal, an operation select bit for storing a trigger operation parameter of the trigger signal;

In an exemplary embodiment, the trigger mode parameters include one or more of a first mode parameter corresponding to a rising edge trigger mode, a second mode parameter corresponding to a falling edge trigger mode, a third mode parameter corresponding to a high level trigger mode, and a fourth mode parameter corresponding to a low level trigger mode.

In an exemplary embodiment, the trigger operation parameters include one or more of a first operation parameter corresponding to a logical AND operation, a second operation parameter corresponding to a logical OR operation, and a third operation parameter corresponding to a logical NOT operation.

In an exemplary embodiment, the register module further comprises a global control register comprising an offset configuration bit for storing a trigger offset parameter of the trigger signal;

In an exemplary embodiment, the global control register further includes a trigger clear bit for storing a first clear parameter;

the logic analysis method further comprises the following steps:

When the first clearing parameter in the trigger clearing bit is a parameter value corresponding to reset, the control attribute register responds to an attribute reset instruction to execute attribute reset operation on the mode selection bit, the enable bit and the operation selection bit.

Determining, by the signal control module, a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter, and writing the trigger signal into the storage module after delaying the target duration when the trigger signal is detected to satisfy the trigger condition, where the process of generating the synchronous write enable signal includes:

And when the trigger signal is detected to meet the trigger condition, the trigger signal is written into the storage module after the target duration is delayed, and a synchronous write-enabling signal is generated.

the logic analysis method further comprises the following steps:

The method comprises the steps that a trigger period count value is determined according to a trigger period parameter in a period configuration bit through a signal control module, after a trigger signal is written into a storage module after a target delay time is long, the write count value of a write counter is increased by 1, when the write count value reaches the trigger period count value, the write period count value of the write period counter is increased by 1, the write period count value is written into a count bit of a state register, and therefore the upper computer can read the trigger signal and trigger data from the storage module when judging that the write period count value in the state register meets a reading condition.

In an exemplary embodiment, the logic analysis method further includes:

And stopping writing the trigger signal into the storage module and stopping outputting the write enable signal to the data control module when the write cycle count value meets the write stopping condition through the signal control module.

In an exemplary embodiment, the logic analysis method further includes:

Judging whether the writing period count value is equal to a preset threshold value or not through a signal control module, if so, judging that the writing period count value meets the writing stopping condition, and if not, judging that the writing period count value does not meet the writing stopping condition; the preset threshold is determined based on a storage depth of the storage module.

In an exemplary embodiment, the process of reading the trigger signal and the trigger data from the memory module when the upper computer determines that the write cycle count value in the status register satisfies the reading condition includes:

When the upper computer judges that the writing period count value in the state register meets the reading condition, the maximum reading address is determined based on the writing period count value, and the trigger signal and the trigger data are read according to the maximum reading address in the storage module.

In an exemplary embodiment, the register module further includes a read control register including address bits for storing a current read address and read enable control bits for storing a read enable parameter;

the logic analyzer also comprises a read control module;

the logic analysis method further comprises the following steps:

When the read enabling control bit of the read control register is a parameter value corresponding to enabling, the read control module reads the trigger signal and the trigger data from the storage module according to the current read address in the address bit of the read control register.

In an exemplary embodiment, when the upper computer determines that the write cycle count value in the status register satisfies the read condition, determining the maximum read address based on the write cycle count value so as to read the trigger signal and the trigger data at the maximum read address in the memory module includes:

When the upper computer judges that the writing period count value in the state register meets the reading condition, the maximum reading address is determined based on the writing period count value, and the current reading address is written into the address bit in the reading control register, so that the trigger signal and the trigger data are read according to the current reading address in the storage module until the current reading address is the maximum reading address.

In an exemplary embodiment, the read control register further includes a first memory space and a second memory space;

the logic analysis method further comprises the following steps:

after the trigger signal and the trigger data are read from the storage module according to the current read address in the address bit of the read control register through the read control module, the trigger signal is stored in the first storage space, and the trigger data are stored in the second storage space, so that the upper computer reads the trigger signal from the first storage space and the trigger data from the second storage space.

In an exemplary embodiment, the global control register further includes a capture clear bit for storing a second clear parameter;

the logic analysis method further comprises the following steps:

And resetting the first storage space, the second storage space, the address bit and the read enabling control bit in response to the capture reset instruction when the second clearing parameter in the capture clearing bit is a parameter value corresponding to reset through the read control register.

In an exemplary embodiment, the logic analyzer further comprises an interface conversion module;

the logic analysis method further comprises the following steps:

And performing first protocol conversion on the trigger parameters sent by the upper computer through the interface conversion module, and performing second protocol conversion on the trigger signals and the trigger data in the register module.

In an exemplary embodiment, the memory module includes a first memory and a second memory;

Determining a trigger condition and a target duration corresponding to the trigger signal based on the trigger parameter through a signal control module, writing the trigger signal into a first memory after the target duration is delayed when the trigger signal is detected to meet the trigger condition, and generating a synchronous write enabling signal;

The process of writing the trigger data of the trigger signal in the observation time period into the storage module at the current moment of receiving the synchronous write enable signal through the data control module comprises the following steps:

And writing trigger data of the trigger signal in the observation time period into the second memory by the data control module at the current moment of receiving the synchronous write-enabling signal.

In an exemplary embodiment, the first memory is a dual-port random access memory built based on registers or a distributed random access memory;

The second memory is a block random access memory.

In a fourth aspect, referring to fig. 11, fig. 11 is a schematic structural diagram of a computer readable storage medium provided in the present invention, where a computer program 81 is stored on the computer readable storage medium 80, and the computer program 81 implements the steps of the logic analysis method described in any one of the embodiments when executed by a processor.

The computer-readable storage medium 80 may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

For an introduction to a computer readable storage medium provided by the present invention, refer to the above embodiments, and the disclosure is not repeated here.

The computer readable storage medium provided by the invention has the same beneficial effects as the logic analysis method.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A logic analyzer, comprising:

2. The logic analyzer of claim 1, wherein the register module comprises an attribute register comprising a mode select bit for storing a trigger mode parameter of the trigger signal, an enable bit for storing a trigger enable parameter of the trigger signal, an operation select bit for storing a trigger operation parameter of the trigger signal;

3. The logic analyzer of claim 2, wherein the trigger mode parameters include one or more of a first mode parameter corresponding to a rising edge trigger mode, a second mode parameter corresponding to a falling edge trigger mode, a third mode parameter corresponding to a high level trigger mode, and a fourth mode parameter corresponding to a low level trigger mode.

4. The logic analyzer of claim 2, wherein the trigger operation parameters include one or more of a first operation parameter corresponding to a logical AND operation, a second operation parameter corresponding to a logical OR operation, and a third operation parameter corresponding to a logical NOT operation.

5. The logic analyzer of claim 2, wherein the register module further comprises a global control register comprising an offset configuration bit for storing a trigger offset parameter of the trigger signal;

6. The logic analyzer of claim 5, wherein the global control register further comprises a trigger clear bit for storing a first clear parameter;

7. The logic analyzer of claim 5, wherein the global control register further comprises a global enable control bit for storing a global enable parameter;

8. The logic analyzer of claim 5, wherein the register module further comprises a status register comprising a count bit for storing a write cycle count value;

9. The logic analyzer of claim 8, wherein the signal control module is further configured to stop writing the trigger signal to the memory module and stop outputting the write enable signal to the data control module when the write cycle count satisfies a stop writing condition.

10. The logic analyzer of claim 9, wherein the signal control module is further configured to determine whether the write cycle count value is equal to a preset threshold, if so, determine that the write cycle count value meets the stop-write condition, and if not, determine that the write cycle count value does not meet the stop-write condition; the preset threshold is determined based on the storage depth of the storage module.

11. The logic analyzer of claim 8, wherein the process of reading the trigger signal and the trigger data from the memory module when the upper computer determines that the write cycle count value in the status register satisfies a read condition comprises:

12. The logic analyzer of claim 11, wherein the register module further comprises a read control register including address bits for storing a current read address and read enable control bits for storing a read enable parameter;

13. The logic analyzer of claim 12, wherein when the host computer determines that the write cycle count value in the status register satisfies a read condition, determining a maximum read address based on the write cycle count value, and reading the trigger signal and the trigger data at the maximum read address in the memory module comprises:

14. The logic analyzer of claim 12, wherein the read control register further comprises a first memory space and a second memory space;

15. The logic analyzer of claim 14, wherein the global control register further comprises a capture clear bit for storing a second clear parameter;

16. The logic analyzer of claim 1, further comprising an interface conversion module configured to perform a first protocol conversion on the trigger parameter sent by the host computer, and perform a second protocol conversion on the trigger signal and the trigger data in the register module.

17. The logic analyzer of any of claims 1-16, wherein the memory module comprises a first memory and a second memory;

18. The logic analyzer of claim 17, wherein the first memory is a dual-port random access memory built based on registers or a distributed random access memory;

the second memory is a block random access memory.

19. A logic analysis system, comprising:

the logic analyzer of any of claims 1-18.

20. A logic analysis method applied to the logic analyzer according to any one of claims 1 to 18, the logic analysis method comprising:

21. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the logic analysis method according to claim 20.