CN118074660A - Wafer level package structure - Google Patents
Wafer level package structure Download PDFInfo
- Publication number
- CN118074660A CN118074660A CN202410466750.1A CN202410466750A CN118074660A CN 118074660 A CN118074660 A CN 118074660A CN 202410466750 A CN202410466750 A CN 202410466750A CN 118074660 A CN118074660 A CN 118074660A
- Authority
- CN
- China
- Prior art keywords
- wafer
- interdigital transducer
- level package
- support structure
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 13
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007723 die pressing method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/25—Constructional features of resonators using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/88—Mounts; Supports; Enclosures; Casings
Landscapes
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
The application relates to the technical field of semiconductors, and discloses a wafer-level packaging structure, which comprises the following components: a substrate, the surface of which is provided with a first interdigital transducer; the support structure is arranged on one surface of the substrate, on which the first interdigital transducer is arranged; a cover wafer coupled to the support structure such that a gap exists between the cover wafer and the first interdigital transducer; the support structure is positioned between the substrate and the cover plate wafer; the cover plate wafer is made of piezoelectric materials. The wafer level packaging structure can effectively reduce the packaging area size, and is suitable for multiplexers/all-in-one filters with smaller packaging area size.
Description
Technical Field
The present application relates to the field of semiconductor technology, for example, to a wafer level package structure.
Background
At present, a SAW (Surface Acoustic Wave ) filter device is one of the currently mainstream piezoelectric acoustic wave filter devices, which has a selective effect on frequency by utilizing the surface acoustic wave effect and resonance characteristics, and is a key device in the fields of mobile communication, automobile electronics and the like.
SAW filters are widely used in the field of communications, and at present, SAW filters are often used to build a duplexer, and an existing duplexer generally includes a transmitting filter and a receiving filter, where the duplexer is used to share signal transmission and reception by an antenna in a frequency division communication system, and performs processing such as signal filtering and selection by an internal transmitting end filter and a receiving end filter. With the recent trend of miniaturization and high performance of communication devices, a higher challenge is presented to the rf front end, and how to reduce the chip size is a problem to be solved.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
The SAW filter is usually in a wafer level package (WAFER LEVEL PACKAGE, WLP) form, and for a Multiplexer/all-in-one filter (n-in-1 Fliter), the conventional SAW filter package structure has the disadvantage of large package area size.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
Embodiments of the present disclosure provide a wafer level package structure to reduce the package area size.
In some embodiments, the wafer level package structure comprises: a substrate, the surface of which is provided with a first interdigital transducer; the support structure is arranged on one surface of the substrate, on which the first interdigital transducer is arranged; a cover wafer coupled to the support structure such that a gap exists between the cover wafer and the first interdigital transducer; the support structure is positioned between the substrate and the cover plate wafer; the cover plate wafer is made of piezoelectric materials.
In some embodiments, the substrate is the same material as the cover wafer.
In some embodiments, the support structure is made of a high molecular polymer.
In some embodiments, a side of the cover wafer facing the support structure is provided with a second interdigital transducer.
In some embodiments, the support structure is provided with a shielding layer between the first interdigital transducer and the second interdigital transducer; the shielding layer and the first interdigital transducer have a gap; the shielding layer and the second interdigital transducer have a gap.
In some embodiments, a solder mask layer is further disposed on a surface of the cover wafer facing away from the support structure.
In some embodiments, the solder mask layer has solder bumps disposed thereon; and the surface of the cover plate wafer is circumferentially provided with leads, and the second interdigital transducer is connected with the soldering tin convex blocks through the leads.
In some embodiments, the first interdigital transducer and the second interdigital transducer are both filter interdigital transducers.
In some embodiments, the first interdigital transducer and the second interdigital transducer are both interdigital transducers of a resonator.
In some embodiments, the resonator is further cascaded with a capacitance; the capacitor is arranged on the cover plate wafer; or, the resonator is also cascaded with an inductor; the inductor is arranged on the cover plate wafer.
The wafer level packaging structure provided by the embodiment of the disclosure can realize the following technical effects: the cover plate wafer is made of piezoelectric materials, two paths of interdigital transducers for manufacturing the SAW resonator can be respectively arranged on the substrate and the cover plate wafer of the structure, or two paths of interdigital transducers for manufacturing the SAW filter are respectively arranged on the substrate and the cover plate wafer of the structure, so that the packaging area size is effectively reduced, and the method is suitable for multiplexers/all-in-one filters with smaller packaging area size.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
fig. 1 is a schematic diagram of a wafer level package structure according to an embodiment of the disclosure.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
Referring to fig. 1, an embodiment of the disclosure provides a wafer level package structure, including: a substrate 1, a support structure 8, a cover wafer 2. The surface of the substrate 1 is provided with a first interdigital transducer 3. The support structure 8 is arranged on the side of the substrate on which the first interdigital transducer is arranged. The cover wafer 2 is coupled to the support structure 8 such that there is a gap between the cover wafer 2 and the first interdigital transducer 3; the support structure 8 is located between the substrate 1 and the cover wafer 2; the cover plate wafer 2 is made of piezoelectric materials.
By adopting the wafer-level packaging structure provided by the embodiment of the disclosure, the cover plate wafer is made of the piezoelectric material, two paths of interdigital transducers for manufacturing the SAW resonator can be respectively arranged on the substrate and the cover plate wafer of the structure, or two paths of interdigital transducers for manufacturing the SAW filter are respectively arranged on the substrate and the cover plate wafer of the structure, so that the packaging area size is effectively reduced while a certain packaging thickness size is sacrificed, and the wafer-level packaging structure is suitable for a multiplexer/all-in-one filter with smaller packaging area size.
Optionally, the substrate is the same material as the cover plate wafer.
The cover plate wafer is made of the same material as the substrate, so that the material at the bottom of the packaging structure and the material at the top of the packaging structure have the same linear expansion coefficient, and the die pressing resistance and the reliability of the whole structure are improved.
Optionally, the support structure is made of a high molecular polymer.
Optionally, the support structure adopts a Dry Film (Dry Film) to form a non-cavity (staggered) support structure, so that the area of the support structure is effectively reduced, and more available area is reserved for the resonator in a limited package size.
As shown in connection with fig. 1, optionally, a second interdigital transducer 4 is provided on the side of the cover wafer facing the supporting structure. The method is suitable for the multiplexer/all-in-one filter with smaller packaging area size.
As shown in connection with fig. 1, the support structure is optionally provided with a shielding layer 6, which shielding layer 6 is located between the first interdigital transducer 3 and the second interdigital transducer 4; the shielding layer 6 and the first interdigital transducer have a gap; the shielding layer 6 has a gap with the second interdigital transducer. Optionally, the shielding layer 6 is a copper foil layer. For acoustic wave devices in electronic devices, such as surface acoustic wave devices, the principle of operation is that acoustic waves are transmitted along an interdigital transducer, so that packaging for the surface acoustic wave device must ensure that the transducer surface cannot contact other substances, i.e., that the surface of the acoustic wave device is in a void or cavity structure.
In some embodiments, when no second interdigital transducer is needed as a filter unit, the cover plate wafer is thinned while the shielding layer is removed, thereby reducing the overall package thickness.
In some embodiments, the cover wafer is consistent with the material of the substrate and the support structure is provided with a shielding layer, further improving the stability of the package structure.
As shown in fig. 1, optionally, a solder mask layer 9 is further disposed on a surface of the cover wafer facing away from the support structure.
As shown in fig. 1, optionally, a solder bump 5 is disposed on the solder mask layer; the surface of the cover plate wafer 2 is circumferentially provided with a lead 11, and the second interdigital transducer 4 is connected with the soldering tin bump 5 through a first bonding pad 10 and the lead 11 in sequence. The second interdigital transducer 4 is connected to the first interdigital transducer 3 via the first bond pad 10, the conductive via 12, and the second bond pad 7 in this order.
Because the cover plate wafer is not provided with the conductive through holes, namely, the lead wires surrounding the cover plate wafer are connected with the solder bumps, the performance influence on the cover plate wafer is avoided.
Optionally, the first interdigital transducer and the second interdigital transducer are both interdigital transducers of a filter.
Optionally, the first interdigital transducer and the second interdigital transducer are both interdigital transducers of a resonator.
Optionally, the resonator is further cascaded with a capacitor; the capacitor is arranged on the cover plate wafer; or, the resonator is also cascaded with an inductor; the inductor is arranged on the cover plate wafer.
When the design is used for the design scene that the number of resonators is large or the cascade capacitor and inductor in the resonator chip are needed, the planar capacitor or inductor is designed on the cover plate wafer, so that the use area after encapsulation can be effectively reduced.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A wafer level package structure, comprising:
A substrate, the surface of which is provided with a first interdigital transducer;
the support structure is arranged on one surface of the substrate, on which the first interdigital transducer is arranged;
A cover wafer coupled to the support structure such that a gap exists between the cover wafer and the first interdigital transducer; the support structure is positioned between the substrate and the cover plate wafer; the cover plate wafer is made of piezoelectric materials.
2. The wafer level package structure of claim 1, wherein the substrate is the same material as the cover wafer.
3. The wafer level package structure of claim 1, wherein the support structure is made of a high molecular polymer.
4. The wafer level package structure of claim 1, wherein a side of the cover wafer facing the support structure is provided with a second interdigital transducer.
5. The wafer level package structure of claim 4, wherein the support structure is provided with a shielding layer between the first interdigital transducer and the second interdigital transducer; the shielding layer and the first interdigital transducer have a gap; the shielding layer and the second interdigital transducer have a gap.
6. The wafer level package structure of claim 1, wherein a solder mask layer is further disposed on a side of the cover wafer facing away from the support structure.
7. The wafer level package structure of claim 6, wherein solder bumps are disposed on the solder mask layer; and the surface of the cover plate wafer is circumferentially provided with leads, and the second interdigital transducer is connected with the soldering tin convex blocks through the leads.
8. The wafer level package structure of any one of claims 1 to 7, wherein the first and second interdigital transducers are both interdigital transducers of a filter.
9. The wafer level package structure of any one of claims 1 to 7, wherein the first and second interdigital transducers are each interdigital transducers of a resonator.
10. The wafer level package structure of claim 9, wherein the resonator is further cascaded with a capacitor; the capacitor is arranged on the cover plate wafer; or alternatively, the first and second heat exchangers may be,
The resonator is also cascaded with an inductor; the inductor is arranged on the cover plate wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410466750.1A CN118074660B (en) | 2024-04-18 | 2024-04-18 | Wafer level package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410466750.1A CN118074660B (en) | 2024-04-18 | 2024-04-18 | Wafer level package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118074660A true CN118074660A (en) | 2024-05-24 |
| CN118074660B CN118074660B (en) | 2024-06-25 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410466750.1A Active CN118074660B (en) | 2024-04-18 | 2024-04-18 | Wafer level package structure |
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| Country | Link |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060249824A1 (en) * | 2005-05-06 | 2006-11-09 | Samsung Electro-Mechanics Co., Ltd. | Stack type surface acoustic wave package, and method for manufacturing the same |
| CN107134986A (en) * | 2016-02-29 | 2017-09-05 | 太阳诱电株式会社 | Electronic device |
| CN109088614A (en) * | 2018-06-28 | 2018-12-25 | 深圳华远微电科技有限公司 | SAW filter and its packaging method and electronic equipment |
| JP2019114985A (en) * | 2017-12-25 | 2019-07-11 | 株式会社村田製作所 | Composite electronic component |
| CN113224012A (en) * | 2020-01-18 | 2021-08-06 | 深圳市麦捷微电子科技股份有限公司 | Wafer-level packaging structure and process of surface acoustic wave filter |
| CN114157258A (en) * | 2022-02-09 | 2022-03-08 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
-
2024
- 2024-04-18 CN CN202410466750.1A patent/CN118074660B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060249824A1 (en) * | 2005-05-06 | 2006-11-09 | Samsung Electro-Mechanics Co., Ltd. | Stack type surface acoustic wave package, and method for manufacturing the same |
| CN107134986A (en) * | 2016-02-29 | 2017-09-05 | 太阳诱电株式会社 | Electronic device |
| JP2019114985A (en) * | 2017-12-25 | 2019-07-11 | 株式会社村田製作所 | Composite electronic component |
| CN109088614A (en) * | 2018-06-28 | 2018-12-25 | 深圳华远微电科技有限公司 | SAW filter and its packaging method and electronic equipment |
| CN113224012A (en) * | 2020-01-18 | 2021-08-06 | 深圳市麦捷微电子科技股份有限公司 | Wafer-level packaging structure and process of surface acoustic wave filter |
| CN114157258A (en) * | 2022-02-09 | 2022-03-08 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118074660B (en) | 2024-06-25 |
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