CN113224012A - Wafer-level packaging structure and process of surface acoustic wave filter - Google Patents
Wafer-level packaging structure and process of surface acoustic wave filter Download PDFInfo
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- CN113224012A CN113224012A CN202010056270.XA CN202010056270A CN113224012A CN 113224012 A CN113224012 A CN 113224012A CN 202010056270 A CN202010056270 A CN 202010056270A CN 113224012 A CN113224012 A CN 113224012A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H—ELECTRICITY
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Abstract
A wafer level packaging structure and process of a surface acoustic wave filter, aiming at solving the CSP packaging process defects of the surface acoustic wave filter device at present, the invention adopts the following technical scheme: the wafer-level packaging structure of the surface acoustic wave filter comprises a piezoelectric substrate, wherein a PAD electrode and an IDT interdigital transducer are arranged inside the piezoelectric substrate, a wall layer is attached to the functional surface of the IDT interdigital transducer, and a top layer is attached to the upper part of the wall layer; a closed cavity C1 is formed among the wall layer, the top layer, the IDT interdigital transducer and the piezoelectric substrate; the outer side surfaces of the PAD electrode, the wall layer and the top layer are also provided with climbing layers; and welding spots are arranged on the surface of the climbing layer. The invention has the beneficial effects that: 1. the top layer is not required to be provided with holes, and the formed cavity can improve the packaging reliability and has small volume; 2. the top layer is not required to be perforated, only the climbing layer is required, and the process is simple; 3. and the liquid leakage of the top layer open pore is prevented without opening pores and metal connecting pieces in the pores.
Description
Technical Field
The invention relates to a wafer-level packaging structure, in particular to a wafer-level packaging structure and a process of a surface acoustic wave filter.
Background
The fifth generation mobile communication system (5G) will promote the overall upgrade of the mobile communication terminal radio frequency system, obtain high-speed and new frequency band communication functions for mobile phone communication, need to increase the number and application of Surface Acoustic Wave Filters (SAWFs), and will bring direct benefits to manufacturers. However, the current mainstream packaging process of the SAWF in China is Chip Scale Packaging (CSP), and the CSP is performed on the piezoelectric chip, the substrate, the metal ball and the resin packaging film through flip chip and resin packaging processes to realize transmission of electrical signals and mechanical signals and packaging protection of devices. The CSP packaging technology of the SAWF at present has the following defects:
1. the cost of the substrate and the resin packaging film is high;
the CSP device is about 20% larger than the bare chip;
3, the CSP device can not be placed in a radio frequency front-end module and is limited in high-end intelligent equipment;
therefore, how to solve the CSP packaging process defect of the surface acoustic wave filter in production becomes a problem which needs to be solved urgently in the industry.
Disclosure of Invention
In order to solve the above mentioned problems, the present invention provides a wafer level package (WLCSP) structure of surface acoustic wave filter with small size, low cost and wide application (in rf front end module).
The invention adopts the following technical scheme:
the utility model provides a wafer level packaging structure of surface acoustic wave filter, includes the piezoelectricity base member, the inside of piezoelectricity base member be equipped with PAD electrode and interdigital transducer, the functional surface facing of interdigital transducer cover and have the wall layer, the wall layer respectively in the position department of PAD electrode and the position department trompil of interdigital transducer to expose the part of PAD electrode and the whole of interdigital transducer; the upper part of the wall layer is adhered with a top layer; a closed cavity C1 is formed among the wall layer, the top layer, the interdigital transducer and the piezoelectric substrate; the outer side surfaces of the PAD electrode, the wall layer and the top layer are also provided with a climbing layer for connecting the PAD electrode, the wall layer and the top layer; the surface of the climbing layer is provided with welding spots, and the climbing layer is connected with the PAD electrode and the welding spots to form electric connection required by an external circuit.
Furthermore, a PAD electrode arranged at the edge of the piezoelectric substrate and interdigital transducers symmetrically distributed at the center of the piezoelectric substrate are arranged in the piezoelectric substrate.
Furthermore, the material of the wall layer and the top layer is epoxy resin, polyimide, photoresist, silicon or glass.
Furthermore, the material of the climbing layer is copper, aluminum, tin, gold, tantalum, titanium or alloy thereof.
Furthermore, the material of the welding spot is tin, gold, copper, silver, nickel or alloy thereof.
The invention also provides a preparation method of the wafer-level packaging structure of the surface acoustic wave filter, which comprises the following steps:
firstly, a wall layer is attached to a functional surface of an interdigital transducer of a piezoelectric substrate, holes are formed in the position of a PAD electrode and the position of the interdigital transducer respectively, the size of an exposed PAD electrode is larger than 1um, and the size of an exposed IDT interdigital transducer is larger than the sum of the size of the IDT plus 1 um;
secondly, the top layer is attached to the upper part of the wall layer, and holes do not need to be formed in the upper part of the top layer in the step;
thirdly, the connection PAD electrode, the wall layer and the top layer are connected through the climbing layer;
fourthly, welding spots are manufactured on the surface of the climbing layer.
Further, the opening in the first step is formed by an exposure and development process or a laser drilling process.
Furthermore, the manufacturing process of the climbing layer in the third step comprises electroplating or physical vapor deposition, and the pattern manufacturing of the climbing layer adopts photoetching or etching process.
Furthermore, the welding spots adopt a screen printing or ball falling and ball planting mode, and are in the shapes of balls, bumps, columns and squares.
The invention has the beneficial effects that:
1. the surface acoustic wave filter surface is covered by the two-layer structure, a top layer is not required to be provided with holes, a cavity is formed, the packaging reliability can be improved, the size is small, the process is optimized, and the cost is reduced;
2. the top layer is not required to be perforated, and only a climbing layer is required, so that the process is simple and the cost is low;
3. the top layer is prevented from being perforated and leaking liquid without perforating and in-hole metal connecting pieces, so that the packaging reliability is improved;
4. when the polymer with high Young modulus and low thermal expansion coefficient is used as the wall layer and the top layer, the wafer-level packaging has stronger deformation resistance and smaller warping capability, the reliability and consistency of the product are ensured, and the reliability and yield of the manufacturing process are improved.
Drawings
FIG. 1 is a schematic structural view of SAWF;
fig. 2-5 are schematic views illustrating a process for fabricating a wafer level package structure according to the present invention.
Wherein: 101 piezoelectric substrate, 102 interdigital transducer IDT, 103 electrode PAD, 104 wall layer, 105 top layer, 106 ramp layer, 107 welding point, C1 cavity.
Detailed Description
Referring to fig. 5, the wafer level package structure of the saw filter of the present invention is a polymer film package structure, and includes a piezoelectric substrate (101), a wall layer (104), a top layer (105), a ramp layer (106), and pads (107). The PAD electrode (103) and the IDT interdigital transducer (102) are arranged in the piezoelectric substrate (101), and the positions and the sizes of the PAD electrode (103) and the IDT interdigital transducer (102) can be changed according to the design requirements of SAWF, for example: according to the design of a certain SAWF, 2 IDT interdigital transducers (102) are distributed at the central symmetrical positions of a piezoelectric substrate (101), a PAD electrode (103) is positioned at the edge of the piezoelectric substrate (101), and the positions and the sizes of the PAD electrode (103) and the IDT interdigital transducer (102) can be changed according to the design requirements of the SAWF. The material of the piezoelectric substrate (101) of the surface acoustic wave filter comprises lithium tantalate, lithium niobate and other materials.
The wall layer (104) is attached to the functional surface of the IDT interdigital transducer (102) of the piezoelectric substrate (101), holes are formed in the position of the PAD electrode (103) and the position of the IDT interdigital transducer (102) respectively, the partial PAD electrode (103) and the whole IDT interdigital transducer (102) are exposed, the size of the exposed PAD electrode (103) is larger than 1um, the size of the exposed IDT interdigital transducer (102) is larger than [ IDT size +1um, the sum of the IDT size and the IDT size ], the positions of the PAD electrode (103) and the IDT interdigital transducer (102) exposed by the holes reasonably change according to the design requirement of SAWF, and the thickness of the wall layer (104) is larger than 1 um. The wall layer can be made of polymer (epoxy resin, polyimide and the like), photoresist, silicon or glass and the like, the polymer film opening process is an exposure and development process, and other materials can adopt a laser drilling process.
The top layer (105) is attached to the upper part of the wall layer (104), and no hole is formed in the top layer (105) and no metal connecting piece in the hole is needed; a closed cavity C1 is formed among the wall layer (104), the top layer (105) and the surface of the IDT interdigital transducer (102) of the piezoelectric substrate, and the IDT interdigital transducer (102) is completely positioned in the closed cavity C1. The top layer (105) has a thickness greater than 5um and a width less than [ PAD dimension-1 um, difference between the two ]. The material of the top layer (105) may be a polymer (epoxy, polyimide, etc.), silicon, or glass, etc.
The climbing layer (106) connects the PAD electrode (103), the wall layer (104) and the top layer (105). The ramp layer (106) pattern may vary according to the SAWF design, and the ramp layer (106) material may be copper, aluminum, tin, gold, tantalum, titanium, alloys thereof, or other suitable materials. The manufacturing process of the climbing layer (106) comprises electroplating, physical vapor deposition and the like, and the pattern of the climbing layer can be realized by photoetching and etching processes. And (3) manufacturing a welding point (107) on the surface of the climbing layer, wherein the welding point (107) can be made of materials such as tin, gold, copper, silver, nickel, alloys of the tin, the gold, the copper, the silver and the nickel or other suitable materials, the shape is not limited to a ball, a bump, a cylinder and a square, and the position on the climbing layer can be any. The ramp layer (106) connects the PAD electrode (103) and the PAD (107) to form the electrical connection required by the external circuit.
Referring to fig. 2-5, the preparation method is further described:
referring to fig. 2, a wall layer (104) is attached to a functional surface of the IDT interdigital transducer (102) of the piezoelectric substrate (101), and holes are formed at the position of the PAD electrode (103) and the position of the IDT interdigital transducer (102), respectively, and the holes are formed by an exposure development process or a laser drilling process, wherein the exposed PAD size is larger than 1um, and the exposed IDT size is larger than [ IDT size +1um, and the sum of the two sizes ].
Referring to fig. 3, the top layer (105) is attached to the top of the wall layer (104) without the need to open a hole in the top of the top layer (105).
Referring to fig. 4, the PAD electrode (103), the wall layer (104) and the top layer (105) are connected by the climbing layer (106), the manufacturing process of the climbing layer (106) comprises electroplating, physical vapor deposition and the like, and the pattern of the climbing layer can specifically adopt photoetching and etching processes.
The exposure and development process comprises the steps of exposing photosensitive polymers of the wall film or the top film to generate photochemical reaction, changing the solubility of the photosensitive polymers in a developing solution, dissolving the unnecessary wall film or the top film by using the developing solution, and transferring the patterns on the mask plate to the wall film or the top film. The laser drilling process is to irradiate the substrate with high power laser beam to heat the substrate to vaporization temperature and evaporate to form holes.
The above examples of this patent are referred to, but this patent is not limited thereto. Any changes and modifications that may occur to those skilled in the art without departing from the true scope of the patent are intended to be covered by the appended claims.
Claims (9)
1. A wafer-level packaging structure of a surface acoustic wave filter comprises a piezoelectric substrate 101, wherein a PAD electrode 103 and an interdigital transducer 102 are arranged inside the piezoelectric substrate 101, and the wafer-level packaging structure is characterized in that a wall layer 104 is attached to the functional surface of the interdigital transducer 102, and holes are respectively formed in the position of the PAD electrode 103 and the position of the interdigital transducer 102 by the wall layer 104 so as to expose the local part of the PAD electrode 103 and the whole of the interdigital transducer 102; the upper part of the wall layer 104 is adhered with a top layer 105; a closed cavity C1 is formed among the wall layer 104, the top layer 105, the interdigital transducer 102 and the piezoelectric substrate 101; the outer side surfaces of the PAD electrode 103, the wall layer 104 and the top layer 105 are also provided with a climbing layer 106 for connecting the PAD electrode 103, the wall layer 104 and the top layer 105; the surface of the climbing layer 106 is provided with a welding point 107, and the climbing layer is connected with the PAD electrode 103 and the welding point 107 to form the electric connection required by an external circuit.
2. The wafer-level package structure of a surface acoustic wave filter as claimed in claim 1, wherein PAD electrodes 103 at the edge of said piezoelectric substrate 101 and interdigital transducers 102 symmetrically disposed at the center of said piezoelectric substrate 101 are provided inside said piezoelectric substrate 101.
3. The wafer level package structure of surface acoustic wave filter as claimed in claim 1, wherein the material of the wall layer 104 and the top layer 105 is epoxy, polyimide, photoresist, silicon or glass.
4. The wafer level package structure of surface acoustic wave filter as claimed in claim 1, wherein the material of said ramp layer 106 is copper, aluminum, tin, gold, tantalum, titanium or their alloys.
5. The wafer level package structure of surface acoustic wave filter as claimed in claim 1, wherein the material of said pads 107 is tin, gold, copper, silver, nickel or alloys thereof.
6. The method for manufacturing a wafer level package structure for a surface acoustic wave filter as claimed in any of claims 1 to 5, wherein said manufacturing method comprises the steps of:
firstly, a wall layer 104 is attached to a functional surface of an interdigital transducer 102 of a piezoelectric substrate 101, holes are respectively formed in the position of a PAD electrode 103 and the position of the interdigital transducer 102, the size of the exposed PAD electrode is larger than 1um, and the size of the exposed interdigital transducer is larger than the sum of the IDT size plus 1 um;
second, the top layer 105 is applied to the top of the wall layer 104, which step does not require opening a hole in the top of the top layer 105;
thirdly, the ramp layer 106 connects the PAD electrode 103, the wall layer 104 and the top layer 105;
fourthly, a solder joint 107 is formed on the surface of the climbing layer 106.
7. The method for manufacturing a wafer level package structure of a surface acoustic wave filter as claimed in claim 6, wherein the opening in the first step is performed by an exposure and development process or a laser drilling process.
8. The method for manufacturing a wafer level package structure of a surface acoustic wave filter as claimed in claim 6, wherein the fabricating process of the ramp layer 106 in the third step includes electroplating or physical vapor deposition, and the pattern fabrication of the ramp layer 106 adopts a photolithography or etching process.
9. The method of manufacturing a wafer level package structure for a surface acoustic wave filter as claimed in claim 6, wherein the pads 107 are formed in a ball, bump, pillar or square shape by screen printing or ball drop placement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010056270.XA CN113224012A (en) | 2020-01-18 | 2020-01-18 | Wafer-level packaging structure and process of surface acoustic wave filter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010056270.XA CN113224012A (en) | 2020-01-18 | 2020-01-18 | Wafer-level packaging structure and process of surface acoustic wave filter |
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| CN113224012A true CN113224012A (en) | 2021-08-06 |
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| CN202010056270.XA Pending CN113224012A (en) | 2020-01-18 | 2020-01-18 | Wafer-level packaging structure and process of surface acoustic wave filter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922783A (en) * | 2021-09-30 | 2022-01-11 | 电子科技大学 | Packaging structure of surface acoustic wave filter |
| CN114465591A (en) * | 2022-04-13 | 2022-05-10 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138712A (en) * | 2013-01-30 | 2013-06-05 | 深圳市麦捷微电子科技股份有限公司 | Novel laminated two-channel common mode electro-static discharge (ESD) filter |
| CN209497432U (en) * | 2019-02-13 | 2019-10-15 | 厦门云天半导体科技有限公司 | A kind of wafer level packaging structure of filter |
| CN110649909A (en) * | 2019-09-30 | 2020-01-03 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave filter device wafer level packaging method and structure thereof |
-
2020
- 2020-01-18 CN CN202010056270.XA patent/CN113224012A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138712A (en) * | 2013-01-30 | 2013-06-05 | 深圳市麦捷微电子科技股份有限公司 | Novel laminated two-channel common mode electro-static discharge (ESD) filter |
| CN209497432U (en) * | 2019-02-13 | 2019-10-15 | 厦门云天半导体科技有限公司 | A kind of wafer level packaging structure of filter |
| CN110649909A (en) * | 2019-09-30 | 2020-01-03 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave filter device wafer level packaging method and structure thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922783A (en) * | 2021-09-30 | 2022-01-11 | 电子科技大学 | Packaging structure of surface acoustic wave filter |
| CN114465591A (en) * | 2022-04-13 | 2022-05-10 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
| CN114465591B (en) * | 2022-04-13 | 2022-06-21 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
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Application publication date: 20210806 |