CN118041297A - Continuous time linear equalizer circuit with multiple feedback paths - Google Patents

Continuous time linear equalizer circuit with multiple feedback paths Download PDF

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Publication number
CN118041297A
CN118041297A CN202410188272.2A CN202410188272A CN118041297A CN 118041297 A CN118041297 A CN 118041297A CN 202410188272 A CN202410188272 A CN 202410188272A CN 118041297 A CN118041297 A CN 118041297A
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China
Prior art keywords
resistor
capacitor
feedback
nmos tube
circuit
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Inventor
刘继业
屈帅
潘钰媛
张涛
牛世琪
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Priority to CN202410188272.2A priority Critical patent/CN118041297A/en
Publication of CN118041297A publication Critical patent/CN118041297A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/32—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides a continuous time linear equalizer circuit with multiple feedback paths, which comprises a differential amplifying circuit and a multiple path negative feedback circuit; the differential amplifying circuit amplifies the received external differential input signal and generates a current output signal which is sent to the multichannel negative feedback circuit; the multi-channel negative feedback circuit receives a current output signal of the differential amplifying circuit, generates a negative feedback voltage signal and outputs the negative feedback voltage signal to the differential amplifying circuit; meanwhile, the multi-channel negative feedback circuit also receives an external control signal, and adjusts the negative feedback voltage sent to the differential amplifying circuit in real time according to the external control signal; the differential amplifying circuit amplifies each frequency component of the external differential input signal according to the received negative feedback voltage signal, and generates and outputs a differential output voltage signal. The invention can flexibly adjust the frequency response of the equalizer, so that the equalizer circuit can better compensate the line loss of each frequency component of the communication signal, and the compensation effect is improved.

Description

Continuous time linear equalizer circuit with multiple feedback paths
Technical Field
The invention relates to a continuous time linear equalizer analog circuit, belonging to the field of integrated circuit design.
Background
The high-speed serial communication has signal transmission loss, and contains different frequency components, the loss of the high-frequency components on the transmission cable is large, and the loss of the low-frequency components is small, so that an equalization circuit is needed to provide different amplification coefficients for the high-frequency and low-frequency signals at the receiving end to compensate the signal loss. The traditional continuous time linear equalizer circuit has only two feedback loops of low frequency and high frequency, the frequency response is solidified, the frequency response curve can not be flexibly adjusted, and the frequency attenuation conditions of different scenes can not be dealt with.
Disclosure of Invention
The technical solution of the invention is as follows: the continuous time linear equalizer circuit with multiple feedback paths is provided, the feedback circuit of the traditional continuous time linear equalizer is improved, and the frequency response curve of the feedback circuit is smoother; meanwhile, the adjustable parameters of the feedback circuit are increased, the response curve of the equalizer is flexibly adjusted to cope with different frequency attenuation conditions, and the signal compensation effect is improved.
The technical scheme of the invention is as follows: a multi-feedback path continuous time linear equalizer circuit comprises a differential amplifying circuit and a multi-path negative feedback circuit; wherein:
the differential amplifying circuit amplifies the received external differential input signal and generates a current output signal which is sent to the multichannel negative feedback circuit;
The multi-channel negative feedback circuit receives a current output signal of the differential amplifying circuit, generates a negative feedback voltage signal and outputs the negative feedback voltage signal to the differential amplifying circuit; meanwhile, the multi-channel negative feedback circuit also receives an external control signal, and adjusts the negative feedback voltage sent to the differential amplifying circuit in real time according to the external control signal;
The differential amplifying circuit amplifies each frequency component of the external differential input signal according to the received negative feedback voltage signal, and generates and outputs a differential output voltage signal.
The differential amplifying circuit comprises an eighth resistor, a ninth resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the positive electrodes of the eighth resistor and the ninth resistor are connected with a power supply VCC; the eighth resistor cathode is connected with the drain electrode of the first NMOS tube and is used as an inverting output end Von of the differential amplifying circuit; the negative electrode of the ninth resistor is connected with the drain electrode of the second NMOS tube and is used as an in-phase output end Vop of the differential amplifying circuit; the grid electrode of the first NMOS tube is connected with the homodromous end Vinp of an external differential input signal; the grid electrode of the second NMOS tube is connected with the inverting terminal Vinn of the external differential input signal; the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube to form a feedback point VF1 of the differential amplifying circuit; the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube to form a feedback point VF2 of the differential amplifying circuit; the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are respectively connected with external bias voltage signals; the source electrodes of the third NMOS tube and the fourth NMOS tube are respectively connected with the ground GND.
The first NMOS tube and the second NMOS tube receive an external differential input voltage signal and a negative feedback voltage signal, and convert the external differential input voltage signal into a current signal; the current signal flows through the eighth resistor and the ninth resistor to be converted into a differential output voltage signal, and amplification of a differential input signal is completed; meanwhile, the current signal flows into the multi-channel negative feedback circuit through feedback points VF1 and VF2 to provide an input current signal for the multi-channel negative feedback circuit; and the gates of the third NMOS tube and the fourth NMOS tube are connected with external bias voltage to form a current source for providing bias current for the differential amplifying circuit.
The multi-path negative feedback circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube;
The first resistor positive electrode, the drain electrode of the fifth NMOS tube, the fourth capacitor positive electrode, the fifth capacitor positive electrode and the sixth capacitor positive electrode are respectively connected with a feedback point VF1 of the differential amplifying circuit; the third resistor cathode, the fourth resistor cathode, the fifth resistor cathode, the third capacitor cathode and the seventh NMOS tube source electrode respectively differential amplifying circuit feedback point VF2; the positive electrode of the second resistor is connected with the negative electrode of the first resistor and the drain electrode of the fifth NMOS tube; the second resistor cathode is connected with the third resistor anode and the source electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with an external low-frequency feedback control voltage signal V L; the grid electrode of the sixth NMOS tube is correspondingly connected with an external high-frequency feedback control voltage signal V H1、VH2 respectively; the source electrode of the sixth NMOS tube is connected with the positive electrodes of the first capacitor, the second capacitor and the third capacitor; the negative electrode of the first capacitor is connected with the positive electrode of the fourth resistor; the negative electrode of the second capacitor is connected with the positive electrode of the fifth resistor; the negative electrode of the fourth capacitor is connected with the positive electrode of the sixth resistor; the negative electrode of the fifth capacitor is connected with the positive electrode of the seventh resistor; the sixth resistor cathode, the seventh resistor cathode and the sixth capacitor cathode are respectively connected with the drain electrode of the seventh NMOS tube.
The negative feedback circuit receives the current signal sent by the differential amplifying circuit, generates negative feedback voltage signals at feedback points VF1 and VF2, and sends the negative feedback voltage signals back to the differential amplifying circuit; the negative feedback circuit comprises a plurality of feedback paths, wherein a first resistor, a second resistor, a third resistor and a fifth NMOS tube form a low-frequency feedback path, a fourth resistor and a first capacitor form a first high-frequency feedback path, a fifth resistor, a second capacitor form a second high-frequency feedback path, a third capacitor form a third high-frequency feedback path, a sixth resistor and a fourth capacitor form a fourth high-frequency feedback path, a seventh resistor and a fifth capacitor form a fifth feedback path, and a sixth capacitor forms a sixth high-frequency feedback path; the external control signal V L controls the on-resistance of the fifth NMOS tube, so that the overall resistance of the low-frequency feedback path is adjusted, and the low-frequency gain is further adjusted; the external control signal V H1 controls the on or off of the sixth NMOS tube so as to determine whether the first, second and third high-frequency feedback paths are connected into the feedback loop; the external control signal V H2 controls the on or off of the seventh NMOS transistor, so as to determine whether the fourth, fifth and sixth high-frequency feedback paths are connected into the feedback loop; the control signal V H1、VH2 is used for controlling whether the high-frequency feedback path is conducted or not, so that the high-frequency gain is adjusted.
The values of the first resistor and the third resistor are the same.
The sixth NMOS tube and the seventh NMOS tube have the same size, and the fourth resistor, the first capacitor, the fifth resistor, the second capacitor and the third capacitor are respectively and correspondingly the same as the sixth resistor, the fourth capacitor, the seventh resistor, the fifth capacitor and the sixth capacitor.
The values of the first capacitor, the second capacitor and the third capacitor are different, and the values of the fourth capacitor, the fifth capacitor and the sixth capacitor are different.
Compared with the prior art, the invention has the advantages that: the invention provides a continuous time linear equalizer circuit with multiple feedback paths, which is used for compensating signal transmission loss in a high-speed serial communication receiving and transmitting system and shaping a received signal. The frequency response of the equalizer is adjusted by using the multi-channel negative feedback circuit, the feedback circuit provides a plurality of feedback paths, the feedback paths are provided with a plurality of adjustable devices, each feedback path has different frequency gain adjustment effects, the gain curve of the traditional continuous time linear equalizer is improved, the flexible and adjustable frequency response curve of the equalizer circuit is realized, and the signal compensation effect is better.
Drawings
Fig. 1 is a block diagram of a continuous time linear equalizer circuit of the multiple feedback paths of the present invention.
Fig. 2 is a differential amplifying circuit.
Fig. 3 is a multi-path negative feedback circuit.
Detailed Description
The invention relates to a multi-feedback-path continuous time linear equalizer circuit, which comprises a differential amplifying circuit and a multi-path negative feedback circuit; the differential amplifying circuit receives and amplifies input signals, the multi-channel negative feedback circuit receives external control signals, the gain of the differential amplifying circuit to each frequency signal is adjusted, the feedback circuit provides a plurality of feedback paths, each feedback path has different frequency gain adjusting effects, and the frequency response curve of the equalizer circuit is flexibly adjustable.
The differential amplifying circuit comprises an eighth resistor 101, a ninth resistor 102, a first NMOS tube 103, a second NMOS tube 104, a third NMOS tube 105 and a fourth NMOS tube 106; the anodes of the eighth resistor 101 and the ninth resistor 102 are connected with a power supply VCC; the negative electrode of the eighth resistor 101 is connected with the drain electrode of the first NMOS tube 103 to be used as an inverting output end Von of the differential amplifying circuit; the negative electrode of the ninth resistor 102 is connected with the drain electrode of the second NMOS tube 104 and is used as an in-phase output end Vop of the differential amplifying circuit; the grid electrode of the first NMOS tube 103 is connected with the homodromous end Vinp of an external differential input signal; the grid electrode of the second NMOS tube 104 is connected with the inverting terminal Vinn of the external differential input signal; the source electrode of the first NMOS tube 103 is connected with the drain electrode of the third NMOS tube 105 to form a feedback point VF1 of the differential amplifying circuit; the source electrode of the second NMOS tube 104 is connected with the drain electrode of the fourth NMOS tube 106 to form a feedback point VF2 of the differential amplifying circuit; the grid electrodes of the third NMOS tube 105 and the fourth NMOS tube 106 are respectively connected with external bias voltage signals; the sources of the third NMOS tube 105 and the fourth NMOS tube 106 are respectively connected with the ground GND.
The first NMOS tube 103 and the second NMOS tube 104 receive an external differential input voltage signal and a negative feedback voltage signal, and convert the external differential input voltage signal into a current signal; the current signal flows through the eighth resistor 101 and the ninth resistor 102 to be converted into a differential output voltage signal, and amplification of a differential input signal is completed; meanwhile, the current signal flows into the multi-channel negative feedback circuit through feedback points VF1 and VF2 to provide an input current signal for the multi-channel negative feedback circuit; the gates of the third NMOS transistor 105 and the fourth NMOS transistor 106 are connected to an external bias voltage to form a current source, and provide bias current for the differential amplifying circuit.
The multi-path negative feedback circuit comprises a first resistor 201, a second resistor 202, a third resistor 203, a fourth resistor 204, a fifth resistor 205, a sixth resistor 206, a seventh resistor 207, a first capacitor 208, a second capacitor 209, a third capacitor 210, a fourth capacitor 211, a fifth capacitor 212, a sixth capacitor 213, a fifth NMOS transistor 214, a sixth NMOS transistor 215, and a seventh NMOS transistor 216;
The positive electrode of the first resistor 201, the drain electrode of the fifth NMOS tube 214, the positive electrode of the fourth capacitor 211, the positive electrode of the fifth capacitor 212 and the positive electrode of the sixth capacitor 213 are respectively connected with a feedback point VF1 of the differential amplifying circuit; the negative electrode of the third resistor 203, the negative electrode of the fourth resistor 204, the negative electrode of the fifth resistor 205, the negative electrode of the third capacitor 210 and the source electrode of the seventh NMOS transistor 216 are respectively used for differentiating the feedback point VF2 of the amplifying circuit; the anode of the second resistor 202 is connected with the cathode of the first resistor 201 and the drain of the fifth NMOS tube 214; the cathode of the second resistor 202 is connected with the anode of the third resistor 203 and the source of the fifth NMOS tube 214; the gate of the fifth NMOS tube 214 is connected with an external low-frequency feedback control voltage signal V L; the grid electrode of the sixth NMOS tube 215 and the grid electrode of the seventh NMOS tube 216 are correspondingly connected with an external high-frequency feedback control voltage signal V H1、VH2 respectively; the source electrode of the sixth NMOS tube 215 is connected with the positive electrodes of the first capacitor 208, the second capacitor 209 and the third capacitor 210; the cathode of the first capacitor 208 is connected with the anode of the fourth resistor 204; the cathode of the second capacitor 209 is connected with the anode of the fifth resistor 205; the cathode of the fourth capacitor 211 is connected with the anode of the sixth resistor 206; the cathode of the fifth capacitor 212 is connected with the anode of the seventh resistor 207; the negative electrode of the sixth resistor 206, the negative electrode of the seventh resistor 207 and the negative electrode of the sixth capacitor 213 are respectively connected with the drain electrode of the seventh NMOS tube 216.
The negative feedback circuit receives the current signal sent by the differential amplifying circuit, generates negative feedback voltage signals at feedback points VF1 and VF2, and sends the negative feedback voltage signals back to the differential amplifying circuit; the negative feedback circuit comprises a plurality of feedback paths, wherein a first resistor 201, a second resistor 202, a third resistor 203 and a fifth NMOS tube 214 form a low-frequency feedback path, a fourth resistor 204 and a first capacitor 208 form a first high-frequency feedback path, a fifth resistor 205, a second capacitor 209 form a second high-frequency feedback path, a third capacitor 210 forms a third high-frequency feedback path, a sixth resistor 206 and a fourth capacitor 211 form a fourth high-frequency feedback path, a seventh resistor 207 and a fifth capacitor 212 form a fifth feedback path, and a sixth capacitor 213 forms a sixth high-frequency feedback path; the external control signal V L controls the on-resistance of the fifth NMOS transistor 214, so as to adjust the overall resistance of the low-frequency feedback path, and further adjust the low-frequency gain; the external control signal V H1 controls the sixth NMOS 215 to turn on or off, so as to determine whether the first, second, and third high-frequency feedback paths are connected into the feedback loop; the external control signal V H2 controls the seventh NMOS transistor 216 to turn on or off, so as to determine whether the fourth, fifth, and sixth high-frequency feedback paths are connected to the feedback loop; the control signal V H1、VH2 is used for controlling whether the high-frequency feedback path is conducted or not, so that the high-frequency gain is adjusted.
The values of the first resistor 201 and the third resistor 203 are the same.
The sixth NMOS transistor 215 and the seventh NMOS transistor 216 have the same size, and the fourth resistor 204, the first capacitor 208, the fifth resistor 205, the second capacitor 209, and the third capacitor 210 have the same values as the sixth resistor 206, the fourth capacitor 211, the seventh resistor 207, the fifth capacitor 212, and the sixth capacitor 213, respectively.
The values of the first capacitor 208, the second capacitor 209, and the third capacitor 210 are different, and the values of the fourth capacitor 211, the fifth capacitor 212, and the sixth capacitor 213 are different.
The invention will be described in detail below with reference to the drawings and the detailed description.
The invention relates to a continuous time linear equalizer circuit with multiple feedback paths, a circuit structure diagram is shown in fig. 1, and is a general circuit diagram of the invention, namely a basic form of the invention, and the circuit structure diagram comprises a differential amplifying circuit and a multiple path negative feedback circuit. The differential amplifying circuit receives and amplifies input signals, the multi-channel negative feedback circuit receives external control signals, the gain of the differential amplifying circuit to each frequency signal is adjusted, the feedback circuit provides a plurality of feedback paths, each feedback path has different frequency gain adjusting effects, and the equalizer can perform proper high-frequency and low-frequency compensation on the signals.
Fig. 2 is a differential amplifying circuit. The first NMOS transistor 103 and the second NMOS transistor 104 receive the input signal, and amplify the signal in cooperation with the eighth resistor 101 and the ninth resistor 102. The gates of the third NMOS tube 105 and the fourth NMOS tube 106 are connected with an external bias voltage signal to provide bias current for the differential circuit.
Fig. 3 is a multi-path negative feedback circuit. The feedback circuit senses a current signal of the differential amplifying circuit, generates a feedback voltage signal and adjusts a gain curve. The first resistor 201, the second resistor 202, the third resistor 203, and the fifth NMOS transistor 214 form a low-frequency feedback path, and the fourth resistor 204, the first capacitor 208, the fifth resistor 205, the second capacitor 209, the third capacitor 210, the sixth resistor 206, the fourth capacitor 211, the seventh resistor 207, the fifth capacitor 212, and the sixth capacitor 213 form 6 high-frequency feedback paths. The fifth NMOS transistor 214 serves as a low frequency gain control device for adjusting the low frequency gain of the equalizer according to the magnitude of the external control signal V L. The larger the control signal V L, the smaller the resistance of the low-frequency feedback path, and the larger the low-frequency gain of the equalizer. The sixth NMOS transistor 215 and the seventh NMOS transistor 216 are used as high-frequency gain control devices, and adjust the high-frequency gain of the equalizer according to the magnitude of the external control signal V H1、VH2. When the control signal V H1、VH2 is high voltage, the sixth NMOS transistor 215 and the seventh NMOS transistor 216 control the plurality of high frequency feedback paths to be turned on, so as to increase the high frequency gain of the equalizer, otherwise, the high frequency feedback paths are turned off, so as to decrease the high frequency gain of the equalizer. Multiple high frequency feedback paths are used in parallel to make the frequency response curve of the equalizer smoother. The size of each capacitor and resistor in the high-frequency feedback path can influence the frequency characteristic of the equalizer, and the parameters of each capacitor and resistor can be designed according to the gain compensation requirement of specific application, so that the frequency response curve of the equalizer can be flexibly adjusted.
What is not described in detail in the present specification is a known technology to those skilled in the art.

Claims (8)

1. A multi-feedback path continuous time linear equalizer circuit, comprising a differential amplifying circuit and a multi-path negative feedback circuit; wherein:
the differential amplifying circuit amplifies the received external differential input signal and generates a current output signal which is sent to the multichannel negative feedback circuit;
The multi-channel negative feedback circuit receives a current output signal of the differential amplifying circuit, generates a negative feedback voltage signal and outputs the negative feedback voltage signal to the differential amplifying circuit; meanwhile, the multi-channel negative feedback circuit also receives an external control signal, and adjusts the negative feedback voltage sent to the differential amplifying circuit in real time according to the external control signal;
The differential amplifying circuit amplifies each frequency component of the external differential input signal according to the received negative feedback voltage signal, and generates and outputs a differential output voltage signal.
2. The multiple feedback path continuous time linear equalizer circuit of claim 1, wherein the differential amplifier circuit comprises an eighth resistor (101), a ninth resistor (102), a first NMOS transistor (103), a second NMOS transistor (104), a third NMOS transistor (105), and a fourth NMOS transistor (106); the anodes of the eighth resistor (101) and the ninth resistor (102) are connected with a power supply VCC; the negative electrode of the eighth resistor (101) is connected with the drain electrode of the first NMOS tube (103) and is used as an inverting output end Von of the differential amplifying circuit; the negative electrode of the ninth resistor (102) is connected with the drain electrode of the second NMOS tube (104) and is used as an in-phase output end Vop of the differential amplifying circuit; the grid electrode of the first NMOS tube (103) is connected with the homodromous end Vinp of an external differential input signal; the grid electrode of the second NMOS tube (104) is connected with the inverting terminal Vinn of the external differential input signal; the source electrode of the first NMOS tube (103) is connected with the drain electrode of the third NMOS tube (105) to form a feedback point VF1 of the differential amplifying circuit; the source electrode of the second NMOS tube (104) is connected with the drain electrode of the fourth NMOS tube (106) to form a feedback point VF2 of the differential amplifying circuit; the grid electrode of the third NMOS tube (105) and the grid electrode of the fourth NMOS tube (106) are respectively connected with external bias voltage signals; the source electrode of the third NMOS tube (105) and the source electrode of the fourth NMOS tube (106) are respectively connected with the ground GND.
3. A multiple feedback path continuous time linear equalizer circuit according to claim 2, wherein the first NMOS transistor (103), the second NMOS transistor (104) receive an external differential input voltage signal and a negative feedback voltage signal, and convert the external differential input voltage signal into a current signal; the current signal flows through an eighth resistor (101) and a ninth resistor (102) to be converted into a differential output voltage signal, and amplification of a differential input signal is completed; meanwhile, the current signal flows into the multi-channel negative feedback circuit through feedback points VF1 and VF2 to provide an input current signal for the multi-channel negative feedback circuit; and the gates of the third NMOS tube (105) and the fourth NMOS tube (106) are connected with external bias voltage to form a current source for providing bias current for the differential amplifying circuit.
4. The multi-feedback path continuous-time linear equalizer circuit of claim 2, wherein the multi-path negative feedback circuit comprises a first resistor (201), a second resistor (202), a third resistor (203), a fourth resistor (204), a fifth resistor (205), a sixth resistor (206), a seventh resistor (207), a first capacitor (208), a second capacitor (209), a third capacitor (210), a fourth capacitor (211), a fifth capacitor (212), a sixth capacitor (213), a fifth NMOS transistor (214), a sixth NMOS transistor (215), and a seventh NMOS transistor (216);
The positive electrode of the first resistor (201), the drain electrode of the fifth NMOS tube (214), the positive electrode of the fourth capacitor (211), the positive electrode of the fifth capacitor (212) and the positive electrode of the sixth capacitor (213) are respectively connected with a feedback point VF1 of the differential amplifying circuit; the negative electrode of the third resistor (203), the negative electrode of the fourth resistor (204), the negative electrode of the fifth resistor (205), the negative electrode of the third capacitor (210) and the source electrode of the seventh NMOS tube (216) are respectively used for differentiating the feedback point VF2 of the amplifying circuit; the anode of the second resistor (202) is connected with the cathode of the first resistor (201) and the drain of the fifth NMOS tube (214); the cathode of the second resistor (202) is connected with the anode of the third resistor (203) and the source of the fifth NMOS tube (214); the grid electrode of the fifth NMOS tube (214) is connected with an external low-frequency feedback control voltage signal V L; the grid electrode of the sixth NMOS tube (215) and the grid electrode of the seventh NMOS tube (216) are correspondingly connected with an external high-frequency feedback control voltage signal V H1、VH2 respectively; the source electrode of the sixth NMOS tube (215) is connected with the positive electrodes of the first capacitor (208), the second capacitor (209) and the third capacitor (210); the negative electrode of the first capacitor (208) is connected with the positive electrode of the fourth resistor (204); the cathode of the second capacitor (209) is connected with the anode of the fifth resistor (205); the negative electrode of the fourth capacitor (211) is connected with the positive electrode of the sixth resistor (206); the negative electrode of the fifth capacitor (212) is connected with the positive electrode of the seventh resistor (207); the negative electrode of the sixth resistor (206), the negative electrode of the seventh resistor (207) and the negative electrode of the sixth capacitor (213) are respectively connected with the drain electrode of the seventh NMOS tube (216).
5. The multi-feedback path continuous-time linear equalizer circuit of claim 4 wherein the negative feedback circuit receives the current signal from the differential amplifier circuit, generates negative feedback voltage signals at feedback points VF1, VF2, and sends the negative feedback voltage signals back to the differential amplifier circuit; the negative feedback circuit comprises a plurality of feedback paths, wherein a first resistor (201), a second resistor (202), a third resistor (203) and a fifth NMOS tube (214) form a low-frequency feedback path, a fourth resistor (204) and a first capacitor (208) form a first high-frequency feedback path, a fifth resistor (205), a second capacitor (209) form a second high-frequency feedback path, a third capacitor (210) form a third high-frequency feedback path, a sixth resistor (206) and a fourth capacitor (211) form a fourth high-frequency feedback path, a seventh resistor (207) and a fifth capacitor (212) form a fifth feedback path, and a sixth capacitor (213) form a sixth high-frequency feedback path; the external control signal V L controls the on-resistance of the fifth NMOS tube (214), so that the overall resistance of the low-frequency feedback path is adjusted, and the low-frequency gain is further adjusted; the external control signal V H1 controls the sixth NMOS tube (215) to be turned on or off so as to determine whether the first, second and third high-frequency feedback paths are connected into the feedback loop; the external control signal V H2 controls the seventh NMOS tube (216) to be turned on or off so as to determine whether the fourth, fifth and sixth high-frequency feedback paths are connected into the feedback loop; the control signal V H1、VH2 is used for controlling whether the high-frequency feedback path is conducted or not, so that the high-frequency gain is adjusted.
6. A multiple feedback path continuous time linear equalizer circuit according to claim 4, wherein the first resistor (201) and the third resistor (203) have the same value.
7. The multiple feedback path continuous time linear equalizer circuit according to claim 4, wherein the sixth NMOS transistor (215) and the seventh NMOS transistor (216) have the same size, and the fourth resistor (204), the first capacitor (208), the fifth resistor (205), the second capacitor (209), and the third capacitor (210) have the same values as the sixth resistor (206), the fourth capacitor (211), the seventh resistor (207), the fifth capacitor (212), and the sixth capacitor (213), respectively.
8. The multiple feedback path continuous time linear equalizer circuit of claim 4, wherein the first capacitor (208), the second capacitor (209), the third capacitor (210) are different in value, and the fourth capacitor (211), the fifth capacitor (212), and the sixth capacitor (213) are different in value.
CN202410188272.2A 2024-02-20 2024-02-20 Continuous time linear equalizer circuit with multiple feedback paths Pending CN118041297A (en)

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CN202410188272.2A CN118041297A (en) 2024-02-20 2024-02-20 Continuous time linear equalizer circuit with multiple feedback paths

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Application Number Priority Date Filing Date Title
CN202410188272.2A CN118041297A (en) 2024-02-20 2024-02-20 Continuous time linear equalizer circuit with multiple feedback paths

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CN118041297A true CN118041297A (en) 2024-05-14

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