CN111697936A - Low-power-consumption complementary digital variable gain amplifier - Google Patents
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Abstract
The invention relates to a low-power-consumption complementary digital variable gain amplifier, which realizes the control of gain by separating a transconductance stage from a transimpedance stage and applying a mode of controlling the equivalent transconductance of the transconductance stage, changes the transconductance value gm of the transconductance amplifier according to different levels of the accessed transconductance stage, and reduces half of the current of the transconductance stage when the same transconductance value is reached by accessing a complementary transconductance pipe; moreover, in the scheme, by using the complementary input transconductance tube, half of power consumption can be saved when the transconductance stage obtains the same transconductance value, and the output transimpedance stage keeps constant bandwidth and gain; in practical application, when a large load needs to be driven, the output end can simultaneously extract current from the transimpedance amplifier and the transconductance amplifier, and the driving capability is large; therefore, compared with the traditional digital variable gain amplifier, the invention has the characteristics of constant bandwidth, stable direct current working point, small chip area, strong driving capability and the like.
Description
Technical Field
The invention relates to a low-power-consumption complementary digital variable gain amplifier, belonging to the technical field of variable gain amplifiers.
Background
In a radio frequency receiving system, the amplification factor of a signal needs to be adjusted according to the size of the received signal, and a variable gain amplifier is a key module for realizing the function. According to the needs of the system, the variable gain amplifier considers the problems of gain control range, gain control precision, bandwidth, linearity, power consumption and the like. The variable gain amplifier is mainly classified into an analog Variable Gain Amplifier (VGA) and a digital variable gain amplifier (PGA) according to differences between control amplification and implementation, and the digital variable gain amplifier is becoming mainstream due to reasons such as a simple gain control implementation method, high gain control accuracy, and a simple and clear structure.
A common implementation method of a digital variable gain amplifier (PGA) is to control a feedback resistor of a fully differential amplifier to realize gain control, however, a change in a feedback coefficient may affect a closed-loop gain and a bandwidth of the amplifier, and to ensure stability of a circuit in all gain states, a dc gain or power consumption of the circuit needs to be sacrificed, the dc gain is sacrificed to reduce a driving capability of the circuit to a subsequent stage, and increasing the power consumption is not favorable for implementing a low power consumption design.
Disclosure of Invention
The invention aims to solve the technical problem of providing a low-power-consumption complementary digital variable gain amplifier, which adopts a brand-new architecture scheme, can save half of transconductance stage current while realizing the same equivalent gain, obviously reduces power consumption, and effectively ensures that the gain and bandwidth of an output transimpedance amplifier are constant.
The invention adopts the following technical scheme for solving the technical problems: the invention designs a low-power-consumption complementary digital variable gain amplifier, which comprises a transconductance amplifier and a transimpedance amplifier, wherein the transconductance amplifier comprises at least one transconductance stage, the structures of the transconductance stages are the same, the transconductance stages are connected in parallel to form the transconductance amplifier, and the transconductance amplifier is used for converting an input voltage signal into an output current signal and realizing the control of the equivalent transconductance value and gain of each connected transconductance stage by controlling the access of each transconductance stage in the circuit implementation application;
the output end of the transconductance amplifying circuit is connected with the input end of a transimpedance amplifier, and the transimpedance amplifier is used for amplifying a current signal output by the transconductance amplifier, converting the current signal into a voltage signal and outputting the voltage signal.
As a preferred technical scheme of the invention: each transconductance stage in the transconductance amplifier comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first switch Ctr1, a second switch Ctr2, a third switch Ctr3 and a fourth switch Ctr4 respectively;
structure of each transconductance stage: the grid electrode of the first PMOS tube MP1 is butted with a PMOS tube bias voltage Vbp through a third switch Ctr3, and the drain electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP 3; the grid of the second PMOS transistor MP2 is connected to the grid of the second NMOS transistor MN2, and then is butted against one end of the first switch Ctr1, and the other end of the first switch Ctr1 forms the positive input end of the transconductance stage; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, and the connected position forms the positive electrode output end of the transconductance stage; the grid of the third PMOS transistor MP3 is connected to the grid of the third NMOS transistor MN3, and then is butted against one end of the second switch Ctr2, and the other end of the second switch Ctr2 forms the negative input end of the transconductance stage; the drain electrode of the third PMOS tube MP3 is connected with the drain electrode of the third NMOS tube MN3, and the connected position forms the negative electrode output end of the transconductance stage; the drain electrode of the first NMOS transistor MN1 is respectively connected with the source electrode of the second NMOS transistor MN2 and the source electrode of the third NMOS transistor MN 3; the grid electrode of the first NMOS tube MN1 is in butt joint with an NMOS tube bias voltage Vbn through a fourth switch Ctr 4; the source electrode of the first NMOS transistor MN1 is grounded;
the positive input ends of all transconductance stages are connected with each other, and the connected positions form a positive voltage input end Vin + of the transconductance amplifier; the negative input ends of all transconductance stages are connected with each other, and the connected positions form a negative voltage input end Vin-of the transconductance amplifier; the positive output ends of all transconductance stages are connected with each other, and the connected positions form the positive current output end of the transconductance amplifier; the negative output ends of all transconductance stages are connected with each other, and the connected positions form the negative current output end of the transconductance amplifier; the sources of the first PMOS transistor MP1 in each transconductance stage are connected with each other, and the connection position is butted with a power supply VDD;
the positive voltage input end Vin + and the negative voltage input end Vin-of the transconductance amplifier respectively receive the input positive voltage signal and the input negative voltage signal, and the positive current output end and the negative current output end of the transconductance amplifier respectively realize the output of the positive current signal and the output of the negative current signal aiming at the current signals obtained by processing.
As a preferred technical scheme of the invention: the transimpedance amplifier comprises two side position structures with the same structures, and each side position structure branch comprises a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a resistor R1;
in each side position structure: the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode, and the connection position is connected with the grid electrode of the sixth PMOS tube MP6 and the drain electrode of the fourth NMOS tube MN 4; the drain electrode of the fifth PMOS transistor MP5 is connected with the gate electrode of the fourth NMOS transistor MN4 and the drain electrode of the fifth NMOS transistor MN5 in a branch manner; the source electrode of the fourth NMOS transistor MN4, the drain electrode of the sixth NMOS transistor MN6 and the gate electrode of the fifth NMOS transistor MN5 are connected, and the connected positions form the input end of a side position structure; the grid electrode of the sixth NMOS tube MN6 is in butt joint with the NMOS bias voltage Vbn; the drain electrode of the sixth PMOS tube MP6, the drain electrode of the seventh NMOS tube MN7 and one end of the first resistor R1 are connected, and the connected positions form the output end of the side position structure;
the source electrode of the fourth PMOS tube MP4, the source electrode of the fifth PMOS tube MP5 and the source electrode of the sixth PMOS tube MP6 in the two-side structure are connected with each other, and the connection position is butted with a power supply VDD; the grids of the fifth PMOS tube MP5 in the two-side structure are connected with each other, and the connection position is butted with a PMOS bias voltage Vbp; the source electrode of the sixth NMOS transistor MN6, the source electrode of the fifth NMOS transistor MN5 and the source electrode of the seventh NMOS transistor MN7 in the two side structures are connected with one another, and the connection positions are grounded; the other ends of the resistors R1 in the two side position structures are connected with each other, and the connected positions are respectively butted with the grid electrodes of the seventh NMOS tube MN7 in the two side position structures;
the input end of one side position structure forms the positive current input end of the trans-impedance amplifier, and the output end of the side position structure forms the negative voltage output end Vout-of the trans-impedance amplifier; the input end of the other side position structure forms a negative current input end of the transimpedance amplifier, and the output end of the side position structure forms a positive voltage output end Vout + of the transimpedance amplifier;
the positive current input end and the negative current input end of the transimpedance amplifier are respectively butted with the positive current output end and the negative current output end of the transimpedance amplifier, the positive current input end and the negative current input end of the transimpedance amplifier respectively receive a positive current signal and a negative current signal output by the transimpedance amplifier, and the positive voltage output end Vout + and the negative voltage output end Vout-of the transimpedance amplifier respectively realize the output of a positive voltage signal and the output of a negative voltage signal aiming at the voltage signals obtained by processing.
Compared with the prior art, the low-power-consumption complementary digital variable gain amplifier has the following technical effects:
the low-power-consumption complementary digital variable gain amplifier is characterized in that a transconductance stage and a transimpedance stage are separated, gain control is realized by applying a mode of controlling equivalent transconductance of the transconductance stage, the transconductance value gm of the transconductance amplifier is changed according to different levels of the connected transconductance stages, and half of current of the transconductance stage can be reduced when the same transconductance value is reached by accessing a complementary transcatheter tube; moreover, in the scheme, by using the complementary input transconductance tube, half of power consumption can be saved when the transconductance stage obtains the same transconductance value, and the output transimpedance stage keeps constant bandwidth and gain; in practical application, when a large load needs to be driven, the output end can simultaneously extract current from the transimpedance amplifier and the transconductance amplifier, and the driving capability is large; therefore, compared with the traditional digital variable gain amplifier, the invention has the characteristics of constant bandwidth, stable direct current working point, small chip area, strong driving capability and the like.
Drawings
FIG. 1 is a circuit diagram of a low power complementary digital variable gain amplifier according to the present invention;
fig. 2 is a circuit diagram of a transimpedance amplifier designed according to the present invention.
Fig. 3 is a curve showing the variation of the circuit gain with the input frequency when the variable gain amplifier of the present invention is connected to transconductance stages of different stages.
Detailed Description
The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.
The invention designs a low-power-consumption complementary digital variable gain amplifier, which comprises a transconductance amplifier and a transimpedance amplifier, wherein in practical application, as shown in figure 1, the transconductance amplifier is specifically designed to comprise at least one transconductance stage, the structures of the transconductance stages are the same, the transconductance stages are connected in parallel to form the transconductance amplifier, the transconductance amplifier is used for converting an input voltage signal into an output current signal, and the equivalent transconductance value and the gain of each connected transconductance stage are controlled by controlling the connection of each transconductance stage in the circuit implementation application; the output end of the transconductance amplifying circuit is connected with the input end of a transimpedance amplifier, and the transimpedance amplifier is used for amplifying a current signal output by the transimpedance amplifier, converting the current signal into a voltage signal and outputting the voltage signal; when the selected transconductance stage access circuit is changed, the gain value of the circuit can be changed, and the function of digitally controllable circuit gain is realized; and the complementary input transcatheter obtains a larger equivalent circuit transconductance value, thereby reducing the power consumption of the circuit.
Next, specific design is performed on the transconductance amplifier and the transimpedance amplifier, as shown in fig. 1, each transconductance stage in the transconductance amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first switch Ctr1, a second switch Ctr2, a third switch Ctr3, and a fourth switch Ctr4, respectively.
Structure of each transconductance stage: the grid electrode of the first PMOS tube MP1 is butted with a PMOS tube bias voltage Vbp through a third switch Ctr3, and the drain electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP 3; the grid of the second PMOS transistor MP2 is connected to the grid of the second NMOS transistor MN2, and then is butted against one end of the first switch Ctr1, and the other end of the first switch Ctr1 forms the positive input end of the transconductance stage; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, and the connected position forms the positive electrode output end of the transconductance stage; the grid of the third PMOS transistor MP3 is connected to the grid of the third NMOS transistor MN3, and then is butted against one end of the second switch Ctr2, and the other end of the second switch Ctr2 forms the negative input end of the transconductance stage; the drain electrode of the third PMOS tube MP3 is connected with the drain electrode of the third NMOS tube MN3, and the connected position forms the negative electrode output end of the transconductance stage; the drain electrode of the first NMOS transistor MN1 is respectively connected with the source electrode of the second NMOS transistor MN2 and the source electrode of the third NMOS transistor MN 3; the grid electrode of the first NMOS tube MN1 is in butt joint with an NMOS tube bias voltage Vbn through a fourth switch Ctr 4; the source of the first NMOS transistor MN1 is grounded.
The positive input ends of all transconductance stages are connected with each other, and the connected positions form a positive voltage input end Vin + of the transconductance amplifier; the negative input ends of all transconductance stages are connected with each other, and the connected positions form a negative voltage input end Vin-of the transconductance amplifier; the positive output ends of all transconductance stages are connected with each other, and the connected positions form the positive current output end of the transconductance amplifier; the negative output ends of all transconductance stages are connected with each other, and the connected positions form the negative current output end of the transconductance amplifier; the sources of the first PMOS transistors MP1 in the transconductance stages are connected to each other, and the connection is connected to the power supply VDD.
The positive voltage input end Vin + and the negative voltage input end Vin-of the transconductance amplifier respectively receive the input positive voltage signal and the input negative voltage signal, and the positive current output end and the negative current output end of the transconductance amplifier respectively realize the output of the positive current signal and the output of the negative current signal aiming at the current signals obtained by processing.
In addition, as shown in fig. 2, the transimpedance amplifier design includes two side position structures with the same structure, and each side position structure branch includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and a resistor R1.
In each side position structure: the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode, and the connection position is connected with the grid electrode of the sixth PMOS tube MP6 and the drain electrode of the fourth NMOS tube MN 4; the drain electrode of the fifth PMOS transistor MP5 is connected with the gate electrode of the fourth NMOS transistor MN4 and the drain electrode of the fifth NMOS transistor MN5 in a branch manner; the source electrode of the fourth NMOS transistor MN4, the drain electrode of the sixth NMOS transistor MN6 and the gate electrode of the fifth NMOS transistor MN5 are connected, and the connected positions form the input end of a side position structure; the grid electrode of the sixth NMOS tube MN6 is in butt joint with the NMOS bias voltage Vbn; the drain of the sixth PMOS transistor MP6, the drain of the seventh NMOS transistor MN7, and one end of the first resistor R1 are connected, and the connected position constitutes the output end of the side bit structure.
The source electrode of the fourth PMOS tube MP4, the source electrode of the fifth PMOS tube MP5 and the source electrode of the sixth PMOS tube MP6 in the two-side structure are connected with each other, and the connection position is butted with a power supply VDD; the grids of the fifth PMOS tube MP5 in the two-side structure are connected with each other, and the connection position is butted with a PMOS bias voltage Vbp; the source electrode of the sixth NMOS transistor MN6, the source electrode of the fifth NMOS transistor MN5 and the source electrode of the seventh NMOS transistor MN7 in the two side structures are connected with one another, and the connection positions are grounded; the other ends of the resistors R1 in the two-side bit structure are connected with each other, and the connected positions are respectively butted with the gates of the seventh NMOS transistor MN7 in the two-side bit structure.
The input end of one side position structure forms the positive current input end of the trans-impedance amplifier, and the output end of the side position structure forms the negative voltage output end Vout-of the trans-impedance amplifier; the input end of the other side bit structure constitutes the negative current input end of the transimpedance amplifier, and the output end of the side bit structure constitutes the positive voltage output end Vout + of the transimpedance amplifier.
The positive current input end and the negative current input end of the transimpedance amplifier are respectively butted with the positive current output end and the negative current output end of the transimpedance amplifier, the positive current input end and the negative current input end of the transimpedance amplifier respectively receive a positive current signal and a negative current signal output by the transimpedance amplifier, and the positive voltage output end Vout + and the negative voltage output end Vout-of the transimpedance amplifier respectively realize the output of a positive voltage signal and the output of a negative voltage signal aiming at the voltage signals obtained by processing.
The low-power-consumption complementary digital variable gain amplifier designed by the invention is applied to practice, and specifically comprises four transconductance stages, namely a first transconductance stage, a second transconductance stage, a third transconductance stage and a fourth transconductance stage as shown in fig. 1. When the scheme of the present invention is applied to practice, when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage are turned on, and the first switch Ctrl1 and the second switch Ctrl2 in each of the remaining transconductance stages are both turned off, it means that only the first transconductance stage is controlled to be connected, and the remaining second transconductance stage, the third transconductance stage, and the fourth transconductance stage are all turned off, wherein the gain of the variable gain amplifier is the minimum value, which is shown by the 0dB gain curve in fig. 3; when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage and the second transconductance stage are turned on, and the first switch Ctrl1 and the second switch Ctrl2 in each of the remaining transconductance stages are turned off, it means that the first transconductance stage is controlled to be connected, the second transconductance stage is controlled to be connected, and the remaining third transconductance stage and the fourth transconductance stage are controlled to be turned off, where the gain of the variable gain amplifier is the minimum value, as shown by the 2dB gain curve in fig. 3; when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage, the second transconductance stage, and the third transconductance stage are turned on, and the first switch Ctrl1 and the second switch Ctrl2 in the fourth transconductance stage are both turned off, it means that the first transconductance stage, the second transconductance stage, and the third transconductance stage are controlled to be turned on, and the fourth transconductance stage is turned off, where the gain of the variable gain amplifier is the minimum value, as shown by the 4dB gain curve in fig. 3; when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage, the second transconductance stage, the third transconductance stage, and the fourth transconductance stage are all turned on, it is indicated that the access of the first transconductance stage, the access of the second transconductance stage, the access of the third transconductance stage, and the access of the fourth transconductance stage are controlled, where the gain of the variable gain amplifier is the minimum value, as shown by the 6dB gain curve in fig. 3. Therefore, the step size and the gain control range of the controllable gain amplifier can be changed by changing the transconductance value of each transconductance stage and the stage number of the transconductance stage.
Based on the practical application of the technical scheme of the low-power-consumption complementary digital variable gain amplifier, the transconductance stage and the transimpedance stage are separated, the gain is controlled by applying a mode of controlling the equivalent transconductance of the transconductance stage, the transconductance value gm of the transconductance amplifier is changed according to different stages of the connected transconductance stage, and half of the current of the transconductance stage can be reduced when the same transconductance value is reached by accessing the complementary transconductance pipe; moreover, in the scheme, by using the complementary input transconductance tube, half of power consumption can be saved when the transconductance stage obtains the same transconductance value, and the output transimpedance stage keeps constant bandwidth and gain; in practical application, when a large load needs to be driven, the output end can simultaneously extract current from the transimpedance amplifier and the transconductance amplifier, and the driving capability is large; therefore, compared with the traditional digital variable gain amplifier, the invention has the characteristics of constant bandwidth, stable direct current working point, small chip area, strong driving capability and the like.
In practical application, the low-power-consumption complementary digital variable gain amplifier provided by the invention solves the problem that the traditional digital controllable amplifier controls the circuit gain by controlling the feedback coefficient of the fully differential amplifier, but the change of the feedback coefficient can affect the bandwidth and the direct current gain of the fully differential amplifier, so that the power consumption is increased, and provides the low-power-consumption complementary digital variable gain amplifier, so that half of transconductance stage current can be saved when the same equivalent gain is realized, the power consumption is obviously reduced, and the gain and the bandwidth of the output transimpedance amplifier are ensured to be constant.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (3)
1. A low power consumption complementary digital variable gain amplifier, comprising: the transconductance amplifier is used for converting an input voltage signal into an output current signal and realizing the control of equivalent transconductance values and gains of the connected transconductance stages by controlling the access of the transconductance stages in circuit implementation application;
the output end of the transconductance amplifying circuit is connected with the input end of a transimpedance amplifier, and the transimpedance amplifier is used for amplifying a current signal output by the transconductance amplifier, converting the current signal into a voltage signal and outputting the voltage signal.
2. The low power consumption complementary digital variable gain amplifier of claim 1, wherein: each transconductance stage in the transconductance amplifier comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first switch Ctr1, a second switch Ctr2, a third switch Ctr3 and a fourth switch Ctr4 respectively;
structure of each transconductance stage: the grid electrode of the first PMOS tube MP1 is butted with a PMOS tube bias voltage Vbp through a third switch Ctr3, and the drain electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP 3; the grid of the second PMOS transistor MP2 is connected to the grid of the second NMOS transistor MN2, and then is butted against one end of the first switch Ctr1, and the other end of the first switch Ctr1 forms the positive input end of the transconductance stage; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, and the connected position forms the positive electrode output end of the transconductance stage; the grid of the third PMOS transistor MP3 is connected to the grid of the third NMOS transistor MN3, and then is butted against one end of the second switch Ctr2, and the other end of the second switch Ctr2 forms the negative input end of the transconductance stage; the drain electrode of the third PMOS tube MP3 is connected with the drain electrode of the third NMOS tube MN3, and the connected position forms the negative electrode output end of the transconductance stage; the drain electrode of the first NMOS transistor MN1 is respectively connected with the source electrode of the second NMOS transistor MN2 and the source electrode of the third NMOS transistor MN 3; the grid electrode of the first NMOS tube MN1 is in butt joint with an NMOS tube bias voltage Vbn through a fourth switch Ctr 4; the source electrode of the first NMOS transistor MN1 is grounded;
the positive input ends of all transconductance stages are connected with each other, and the connected positions form a positive voltage input end Vin + of the transconductance amplifier; the negative input ends of all transconductance stages are connected with each other, and the connected positions form a negative voltage input end Vin-of the transconductance amplifier; the positive output ends of all transconductance stages are connected with each other, and the connected positions form the positive current output end of the transconductance amplifier; the negative output ends of all transconductance stages are connected with each other, and the connected positions form the negative current output end of the transconductance amplifier; the sources of the first PMOS transistor MP1 in each transconductance stage are connected with each other, and the connection position is butted with a power supply VDD;
the positive voltage input end Vin + and the negative voltage input end Vin-of the transconductance amplifier respectively receive the input positive voltage signal and the input negative voltage signal, and the positive current output end and the negative current output end of the transconductance amplifier respectively realize the output of the positive current signal and the output of the negative current signal aiming at the current signals obtained by processing.
3. A low power consumption complementary digital variable gain amplifier according to claim 1 or 2, characterized in that: the transimpedance amplifier comprises two side position structures with the same structures, and each side position structure branch comprises a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a resistor R1;
in each side position structure: the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode, and the connection position is connected with the grid electrode of the sixth PMOS tube MP6 and the drain electrode of the fourth NMOS tube MN 4; the drain electrode of the fifth PMOS transistor MP5 is connected with the gate electrode of the fourth NMOS transistor MN4 and the drain electrode of the fifth NMOS transistor MN5 in a branch manner; the source electrode of the fourth NMOS transistor MN4, the drain electrode of the sixth NMOS transistor MN6 and the gate electrode of the fifth NMOS transistor MN5 are connected, and the connected positions form the input end of a side position structure; the grid electrode of the sixth NMOS tube MN6 is in butt joint with the NMOS bias voltage Vbn; the drain electrode of the sixth PMOS tube MP6, the drain electrode of the seventh NMOS tube MN7 and one end of the first resistor R1 are connected, and the connected positions form the output end of the side position structure;
the source electrode of the fourth PMOS tube MP4, the source electrode of the fifth PMOS tube MP5 and the source electrode of the sixth PMOS tube MP6 in the two-side structure are connected with each other, and the connection position is butted with a power supply VDD; the grids of the fifth PMOS tube MP5 in the two-side structure are connected with each other, and the connection position is butted with a PMOS bias voltage Vbp; the source electrode of the sixth NMOS transistor MN6, the source electrode of the fifth NMOS transistor MN5 and the source electrode of the seventh NMOS transistor MN7 in the two side structures are connected with one another, and the connection positions are grounded; the other ends of the resistors R1 in the two side position structures are connected with each other, and the connected positions are respectively butted with the grid electrodes of the seventh NMOS tube MN7 in the two side position structures;
the input end of one side position structure forms the positive current input end of the trans-impedance amplifier, and the output end of the side position structure forms the negative voltage output end Vout-of the trans-impedance amplifier; the input end of the other side position structure forms a negative current input end of the transimpedance amplifier, and the output end of the side position structure forms a positive voltage output end Vout + of the transimpedance amplifier;
the positive current input end and the negative current input end of the transimpedance amplifier are respectively butted with the positive current output end and the negative current output end of the transimpedance amplifier, the positive current input end and the negative current input end of the transimpedance amplifier respectively receive a positive current signal and a negative current signal output by the transimpedance amplifier, and the positive voltage output end Vout + and the negative voltage output end Vout-of the transimpedance amplifier respectively realize the output of a positive voltage signal and the output of a negative voltage signal aiming at the voltage signals obtained by processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010564184.XA CN111697936B (en) | 2020-06-19 | 2020-06-19 | Low-power consumption complementary digital variable gain amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010564184.XA CN111697936B (en) | 2020-06-19 | 2020-06-19 | Low-power consumption complementary digital variable gain amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111697936A true CN111697936A (en) | 2020-09-22 |
| CN111697936B CN111697936B (en) | 2023-08-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113422586A (en) * | 2021-07-07 | 2021-09-21 | 南方科技大学 | High-energy-efficiency equalizer architecture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026930A (en) * | 2016-07-19 | 2016-10-12 | 东南大学 | Low-power-consumption high-conversion-gain passive frequency mixer |
| CN108667434A (en) * | 2018-04-12 | 2018-10-16 | 东南大学 | A kind of low-voltage low output impedance trans-impedance amplifier |
| CN109951161A (en) * | 2019-02-28 | 2019-06-28 | 东南大学 | A kind of complementary type digital variable gain amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026930A (en) * | 2016-07-19 | 2016-10-12 | 东南大学 | Low-power-consumption high-conversion-gain passive frequency mixer |
| CN108667434A (en) * | 2018-04-12 | 2018-10-16 | 东南大学 | A kind of low-voltage low output impedance trans-impedance amplifier |
| CN109951161A (en) * | 2019-02-28 | 2019-06-28 | 东南大学 | A kind of complementary type digital variable gain amplifier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422586A (en) * | 2021-07-07 | 2021-09-21 | 南方科技大学 | High-energy-efficiency equalizer architecture |
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