CN111697936A - Low-power-consumption complementary digital variable gain amplifier - Google Patents

Abstract

The invention relates to a low power consumption complementary digital variable gain amplifier. By separating the transconductance stage from the transimpedance stage, the method of controlling the equivalent transconductance of the transconductance stage is used to realize the gain control, and the gain is controlled according to the connected transconductance stage. The number of conduction stages is different, changing the transconductance value gm of the transconductance amplifier, and by connecting the complementary transconductor, when reaching the same transconductance value, the current of the transconductance stage can be reduced by half; not only that, in the scheme by using Complementary input transconductor enables the transconductance stage to save half of the power consumption when obtaining the same transconductance value, and keeps the output transimpedance stage with constant bandwidth and gain; in practical applications, when it is necessary to drive a large load, The output terminal can draw current from the transimpedance amplifier and the transconductance amplifier at the same time, and the driving ability is large; therefore, compared with the traditional digital variable gain amplifier, the present invention has the characteristics of constant bandwidth, stable DC operating point, small chip area, and strong driving ability. .

Description

A Low Power Complementary Digital Variable Gain Amplifier

technical field

The invention relates to a low power consumption complementary digital variable gain amplifier, belonging to the technical field of variable gain amplifiers.

Background technique

In the radio frequency receiving system, the amplification factor of the signal needs to be adjusted according to the size of the received signal, and the variable gain amplifier is the key module to realize this function. According to the needs of the system, the variable gain amplifier considers the gain control range, gain control accuracy, bandwidth, linearity, power consumption and other issues. According to the difference of control amplification and implementation, variable gain amplifiers are mainly divided into analog variable gain amplifiers (VGA) and digital variable gain amplifiers (PGA). High, simple and clear structure and other reasons, gradually become the mainstream.

The commonly used implementation method of digital variable gain amplifier (PGA) is to control the gain by controlling the feedback resistance of the fully differential amplifier. However, the change of the feedback coefficient will affect the closed-loop gain and bandwidth of the amplifier. To be stable, it is necessary to sacrifice the DC gain or power consumption of the circuit. Sacrificing the DC gain reduces the driving ability of the circuit to the subsequent stage, and increasing the power consumption will not be conducive to the realization of low-power design.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a low power consumption complementary digital variable gain amplifier, which adopts a new architecture scheme, can save half of the transconductance stage current while achieving the same equivalent gain, and significantly reduce power consumption, And effectively ensure that the output transimpedance amplifier gain and bandwidth are constant.

In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a low power consumption complementary digital variable gain amplifier, including a transconductance amplifier and a transimpedance amplifier, wherein the transconductance amplifier includes at least one transconductance stage, The structures of each transconductance stage are the same as each other, and each transconductance stage is connected in parallel to form a transconductance amplifier. The transconductance amplifier is used to convert the input voltage signal into an output current signal, and control each transconductance stage in the circuit implementation application. access to realize the control of the equivalent transconductance value and gain of each transconductance stage connected;

The output end of the transconductance amplifying circuit is connected to the input end of the transimpedance amplifier, and the transimpedance amplifier is used to amplify the current signal output by the transconductance amplifier and convert it into a voltage signal for output.

As a preferred technical solution of the present invention, each transconductance stage in the transconductance amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second PMOS transistor MP3, and a second PMOS transistor. NMOS transistor MN2, third NMOS transistor MN3, first switch Ctr1, second switch Ctr2, third switch Ctr3, fourth switch Ctr4;

In the structure of each transconductance stage: the gate of the first PMOS transistor MP1 is connected to the PMOS transistor bias voltage Vbp via the third switch Ctr3, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the third The source of the PMOS transistor MP3 is connected; the gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2, and then connected to one end of the first switch Ctr1, and the other end of the first switch Ctr1 constitutes the transconductance stage. Positive input terminal; the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the connected position constitutes the positive output terminal of the transconductance stage; the gate of the third PMOS transistor MP3 is connected to the third NMOS transistor MN3 After the gate of the second switch Ctr2 is connected, one end of the second switch Ctr2 is connected, and the other end of the second switch Ctr2 constitutes the negative input terminal of the transconductance stage; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3. And the connected position constitutes the negative output terminal of the transconductance stage; the drain of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 respectively; the gate of the first NMOS transistor MN1 The pole is connected to the bias voltage Vbn of the NMOS transistor through the fourth switch Ctr4; the source of the first NMOS transistor MN1 is grounded;

The positive input terminals of each transconductance stage are connected to each other, and the connection position constitutes the positive voltage input terminal Vin+ of the transconductance amplifier; the negative input terminals of each transconductance stage are connected to each other, and the connection position constitutes the negative voltage input terminal of the transconductance amplifier. Vin-; the positive output terminals of each transconductance stage are connected to each other, and this connection position constitutes the positive current output terminal of the transconductance amplifier; the negative output terminals of each transconductance stage are connected to each other, and this connection position constitutes the negative current output terminal of the transconductance amplifier an output end; the sources of the first PMOS transistors MP1 in each transconductance stage are connected to each other, and the connection position is connected to the power supply VDD;

The positive voltage input terminal Vin+ and the negative voltage input terminal Vin- of the transconductance amplifier receive the input positive voltage signal and negative voltage signal respectively. Realize the output of positive current signal and the output of negative current signal.

As a preferred technical solution of the present invention, the transimpedance amplifier includes two lateral structures with the same structure, and each lateral structure subsection includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor. MP6, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the resistor R1;

In each lateral structure: the gate of the fourth PMOS transistor MP4 is connected to the drain, and the connected position is connected to the gate of the sixth PMOS transistor MP6 and the drain of the fourth NMOS transistor MN4; The drain part is connected to the gate of the fourth NMOS transistor MN4 and the drain of the fifth NMOS transistor MN5; the source of the fourth NMOS transistor MN4, the drain of the sixth NMOS transistor MN6, and the gate of the fifth NMOS transistor MN5; are connected, and the connected position constitutes the input end of the lateral structure; the gate of the sixth NMOS transistor MN6 is connected to the NMOS bias voltage Vbn; the drain of the sixth PMOS transistor MP6, the drain of the seventh NMOS transistor MN7, the first One end of the resistor R1 is connected to the three, and the connected position constitutes the output end of the lateral structure;

The source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6 in the two-side structure are connected to each other, and the connection position is connected to the power supply VDD; the two-side structure The gates of the fifth PMOS transistor MP5 are connected to each other, and the connected position is connected to the PMOS bias voltage Vbp; the source of the sixth NMOS transistor MN6, the source of the fifth NMOS transistor MN5, and the seventh NMOS in the two-sided structure are A total of six sources of the tube MN7 are connected to each other, and the connection position is grounded; the other ends of the resistor R1 in the two-side structure are connected to each other, and the connected position is respectively connected to the gate of the seventh NMOS transistor MN7 in the two-side structure;

The input terminal of the lateral structure constitutes the positive current input terminal of the transimpedance amplifier, and the output terminal of the lateral structure constitutes the negative voltage output terminal Vout- of the transimpedance amplifier; the input terminal of the other lateral structure constitutes the transimpedance amplifier. The negative current input terminal of , and the output terminal of the lateral structure constitutes the positive voltage output terminal Vout+ of the transimpedance amplifier;

The positive current input terminal and the negative current input terminal of the transimpedance amplifier are respectively connected to the positive current output terminal and the negative current output terminal of the transimpedance amplifier. The current signal, the negative current signal, the positive voltage output terminal Vout+ and the negative voltage output terminal Vout- of the transimpedance amplifier respectively realize the output of the positive voltage signal and the negative voltage signal for the voltage signal obtained by processing.

The low power consumption complementary digital variable gain amplifier of the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

The low power consumption complementary digital variable gain amplifier designed by the present invention realizes the gain control by separating the transconductance stage from the transimpedance stage, applying the method of controlling the equivalent transconductance of the transconductance stage, and according to the connected transconductance The number of stages is different, changing the transconductance value gm of the transconductance amplifier, and by connecting the complementary transconductor, when reaching the same transconductance value, the transconductance stage current can be reduced by half; not only that, by using complementary The transconductance stage can save half the power consumption when obtaining the same transconductance value, and the output transimpedance stage can maintain a constant bandwidth and gain; in practical applications, when a large load needs to be driven, the output The terminal can draw current from the transimpedance amplifier and the transconductance amplifier at the same time, and the driving ability is large; therefore, compared with the traditional digital variable gain amplifier, the present invention has the characteristics of constant bandwidth, stable DC operating point, small chip area, and strong driving ability.

Description of drawings

1 is a circuit diagram of a low power consumption complementary digital variable gain amplifier designed by the present invention;

FIG. 2 is a circuit diagram of a transimpedance amplifier designed by the invention.

FIG. 3 is a graph showing the variation of circuit gain with input frequency when the variable gain amplifier of the present invention is connected to different stages of transconductance stages.

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

A low-power complementary digital variable gain amplifier designed by the present invention includes a transconductance amplifier and a transimpedance amplifier. In practical applications, as shown in Figure 1, the specifically designed transconductance amplifier includes at least one transconductance stage, each The structures of the conductor stages are the same as each other, and each transconductance stage is connected in parallel with each other to form a transconductance amplifier. input to realize the control of the equivalent transconductance value and gain of each transconductance stage connected; the output end of the transconductance amplifier circuit is connected to the input end of the transimpedance amplifier, and the transimpedance amplifier is used to convert the current signal output by the transconductance amplifier Amplify and convert it into a voltage signal for output; when changing the selected transconductance stage to connect to the circuit, the gain value of the circuit can be changed to realize the function of digitally controllable circuit gain; and the complementary input transconductor can get a larger value. The equivalent transconductance value of the circuit, thereby reducing the power consumption of the circuit.

Next, a specific design is made for the transconductance amplifier and the transimpedance amplifier. As shown in Figure 1, each transconductance stage in the transconductance amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the first switch Ctr1, the second switch Ctr2, the third switch Ctr3, and the fourth switch Ctr4.

In the structure of each transconductance stage: the gate of the first PMOS transistor MP1 is connected to the PMOS transistor bias voltage Vbp via the third switch Ctr3, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the third The source of the PMOS transistor MP3 is connected; the gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2, and then connected to one end of the first switch Ctr1, and the other end of the first switch Ctr1 constitutes the transconductance stage. Positive input terminal; the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the connected position constitutes the positive output terminal of the transconductance stage; the gate of the third PMOS transistor MP3 is connected to the third NMOS transistor MN3 After the gate of the second switch Ctr2 is connected, one end of the second switch Ctr2 is connected, and the other end of the second switch Ctr2 constitutes the negative input terminal of the transconductance stage; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3. And the connected position constitutes the negative output terminal of the transconductance stage; the drain of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 respectively; the gate of the first NMOS transistor MN1 The pole is connected to the bias voltage Vbn of the NMOS transistor through the fourth switch Ctr4; the source of the first NMOS transistor MN1 is grounded.

The positive input terminals of each transconductance stage are connected to each other, and the connection position constitutes the positive voltage input terminal Vin+ of the transconductance amplifier; the negative input terminals of each transconductance stage are connected to each other, and the connection position constitutes the negative voltage input terminal of the transconductance amplifier. Vin-; the positive output terminals of each transconductance stage are connected to each other, and this connection position constitutes the positive current output terminal of the transconductance amplifier; the negative output terminals of each transconductance stage are connected to each other, and this connection position constitutes the negative current output terminal of the transconductance amplifier Output terminal; the sources of the first PMOS transistors MP1 in each transconductance stage are connected to each other, and the connection position is connected to the power supply VDD.

The positive voltage input terminal Vin+ and the negative voltage input terminal Vin- of the transconductance amplifier receive the input positive voltage signal and negative voltage signal respectively. Realize the output of positive current signal and the output of negative current signal.

In addition, as shown in FIG. 2 , the design of the transimpedance amplifier includes two lateral structures with the same structure, and each lateral structure segment includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, The fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the resistor R1.

In each lateral structure: the gate of the fourth PMOS transistor MP4 is connected to the drain, and the connected position is connected to the gate of the sixth PMOS transistor MP6 and the drain of the fourth NMOS transistor MN4; The drain part is connected to the gate of the fourth NMOS transistor MN4 and the drain of the fifth NMOS transistor MN5; the source of the fourth NMOS transistor MN4, the drain of the sixth NMOS transistor MN6, and the gate of the fifth NMOS transistor MN5; are connected, and the connected position constitutes the input end of the lateral structure; the gate of the sixth NMOS transistor MN6 is connected to the NMOS bias voltage Vbn; the drain of the sixth PMOS transistor MP6, the drain of the seventh NMOS transistor MN7, the first One end of the resistor R1 is connected to the three, and the connected position constitutes the output end of the lateral structure.

The source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6 in the two-side structure are connected to each other, and the connection position is connected to the power supply VDD; the two-side structure The gates of the fifth PMOS transistor MP5 are connected to each other, and the connected position is connected to the PMOS bias voltage Vbp; the source of the sixth NMOS transistor MN6, the source of the fifth NMOS transistor MN5, and the seventh NMOS in the two-sided structure are The six sources of the transistor MN7 are connected to each other, and the connection position is grounded; the other ends of the resistor R1 in the double-side structure are connected to each other, and the connection positions are respectively connected to the gate of the seventh NMOS transistor MN7 in the double-side structure.

The input terminal of the lateral structure constitutes the positive current input terminal of the transimpedance amplifier, and the output terminal of the lateral structure constitutes the negative voltage output terminal Vout- of the transimpedance amplifier; the input terminal of the other lateral structure constitutes the transimpedance amplifier. The negative current input terminal of , and the output terminal of the lateral structure constitutes the positive voltage output terminal Vout+ of the transimpedance amplifier.

The positive current input terminal and the negative current input terminal of the transimpedance amplifier are respectively connected to the positive current output terminal and the negative current output terminal of the transimpedance amplifier. The current signal, the negative current signal, the positive voltage output terminal Vout+ and the negative voltage output terminal Vout- of the transimpedance amplifier respectively realize the output of the positive voltage signal and the negative voltage signal for the voltage signal obtained by processing.

The low-power complementary digital variable gain amplifier designed in the present invention is applied in practice, and specifically, the design of the transconductance amplifier includes four transconductance stages, that is, as shown in FIG. Conduction stage, third transconductance stage, and fourth transconductance stage. When the solution of the present invention is applied in practice, when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage are turned on, and the first switch Ctrl1 and the second switch Ctrl2 in the other transconductance stages are both turned off, That is to say, only the first transconductance stage is controlled to be connected, and the remaining second, third, and fourth transconductance stages are all disconnected, and the gain of the variable gain amplifier is the minimum value, that is, 0dB in Figure 3 The gain curve is shown; when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage and the second transconductance stage are turned on, the first switch Ctrl1 and the second switch Ctrl2 in the other transconductance stages are both turned off , it means that the first transconductance stage is controlled to be connected, the second transconductance stage is connected, and the other third and fourth transconductance stages are all disconnected, and the gain of the variable gain amplifier is the minimum value, as shown in the figure As shown in the 2dB gain curve in 3; when the first switch Ctrl1 and the second switch Ctrl2 in the first transconductance stage, the second transconductance stage and the third transconductance stage are turned on, the first switch in the fourth transconductance stage When Ctrl1 and the second switch Ctrl2 are both disconnected, it means that the first transconductance stage is connected, the second transconductance stage is connected, the third transconductance stage is connected, and the fourth transconductance stage is disconnected, and the variable gain is controlled. The gain of the amplifier is the minimum value, as shown in the 4dB gain curve in Figure 3; when the first switch Ctrl1 in the first, second, third, and fourth transconductance stages and the second The switches Ctrl2 are all turned on, which means that the access of the first transconductance stage, the access of the second transconductance stage, the access of the third transconductance stage, and the access of the fourth transconductance stage are controlled, and the gain of the variable gain amplifier is the minimum. value, as shown in the 6dB gain curve in Figure 3. Therefore, the step size and gain control range of the controllable gain amplifier can be changed by changing the transconductance value of each transconductance stage and the number of stages of the transconductance stage.

Based on the practical application of the above-mentioned low-power complementary digital variable gain amplifier technical scheme, by separating the transconductance stage from the transimpedance stage, the control of the gain is realized by controlling the equivalent transconductance of the transconductance stage. The number of transconductance stages is different, changing the transconductance value gm of the transconductance amplifier, and by connecting the complementary transconductor, when reaching the same transconductance value, the transconductance stage current can be reduced by half; not only that, in the scheme By using complementary input transconductors, the transconductance stage can save half of the power consumption when obtaining the same transconductance value, and the output transimpedance stage can maintain a constant bandwidth and gain; in practical applications, when a large load needs to be driven When , the output terminal can draw current from the transimpedance amplifier and the transconductance amplifier at the same time, and the driving ability is large; therefore, compared with the traditional digital variable gain amplifier, the present invention has the advantages of constant bandwidth, stable DC operating point, small chip area and strong driving ability. Features.

In practical application, the low power consumption complementary digital variable gain amplifier designed in the present invention solves the problem that the traditional digital controllable amplifier controls the circuit gain by controlling the feedback coefficient of the fully differential amplifier, but the change of the feedback coefficient will affect the performance of the fully differential amplifier. Bandwidth and DC gain lead to the problem of increased power consumption, providing a low-power complementary digital variable gain amplifier, which can save half of the transconductance stage current when achieving the same equivalent gain, significantly reduce power consumption, and ensure The output transimpedance amplifier has a constant gain and bandwidth.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, and can also be made within the scope of knowledge possessed by those of ordinary skill in the art without departing from the purpose of the present invention. Various changes.

Claims (3)

1. A low power consumption complementary digital variable gain amplifier, comprising: the transconductance amplifier is used for converting an input voltage signal into an output current signal and realizing the control of equivalent transconductance values and gains of the connected transconductance stages by controlling the access of the transconductance stages in circuit implementation application;

the output end of the transconductance amplifying circuit is connected with the input end of a transimpedance amplifier, and the transimpedance amplifier is used for amplifying a current signal output by the transconductance amplifier, converting the current signal into a voltage signal and outputting the voltage signal.

2. The low power consumption complementary digital variable gain amplifier of claim 1, wherein: each transconductance stage in the transconductance amplifier comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first switch Ctr1, a second switch Ctr2, a third switch Ctr3 and a fourth switch Ctr4 respectively;

structure of each transconductance stage: the grid electrode of the first PMOS tube MP1 is butted with a PMOS tube bias voltage Vbp through a third switch Ctr3, and the drain electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP 3; the grid of the second PMOS transistor MP2 is connected to the grid of the second NMOS transistor MN2, and then is butted against one end of the first switch Ctr1, and the other end of the first switch Ctr1 forms the positive input end of the transconductance stage; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, and the connected position forms the positive electrode output end of the transconductance stage; the grid of the third PMOS transistor MP3 is connected to the grid of the third NMOS transistor MN3, and then is butted against one end of the second switch Ctr2, and the other end of the second switch Ctr2 forms the negative input end of the transconductance stage; the drain electrode of the third PMOS tube MP3 is connected with the drain electrode of the third NMOS tube MN3, and the connected position forms the negative electrode output end of the transconductance stage; the drain electrode of the first NMOS transistor MN1 is respectively connected with the source electrode of the second NMOS transistor MN2 and the source electrode of the third NMOS transistor MN 3; the grid electrode of the first NMOS tube MN1 is in butt joint with an NMOS tube bias voltage Vbn through a fourth switch Ctr 4; the source electrode of the first NMOS transistor MN1 is grounded;

the positive input ends of all transconductance stages are connected with each other, and the connected positions form a positive voltage input end Vin + of the transconductance amplifier; the negative input ends of all transconductance stages are connected with each other, and the connected positions form a negative voltage input end Vin-of the transconductance amplifier; the positive output ends of all transconductance stages are connected with each other, and the connected positions form the positive current output end of the transconductance amplifier; the negative output ends of all transconductance stages are connected with each other, and the connected positions form the negative current output end of the transconductance amplifier; the sources of the first PMOS transistor MP1 in each transconductance stage are connected with each other, and the connection position is butted with a power supply VDD;

the positive voltage input end Vin + and the negative voltage input end Vin-of the transconductance amplifier respectively receive the input positive voltage signal and the input negative voltage signal, and the positive current output end and the negative current output end of the transconductance amplifier respectively realize the output of the positive current signal and the output of the negative current signal aiming at the current signals obtained by processing.

3. A low power consumption complementary digital variable gain amplifier according to claim 1 or 2, characterized in that: the transimpedance amplifier comprises two side position structures with the same structures, and each side position structure branch comprises a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a resistor R1;

in each side position structure: the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode, and the connection position is connected with the grid electrode of the sixth PMOS tube MP6 and the drain electrode of the fourth NMOS tube MN 4; the drain electrode of the fifth PMOS transistor MP5 is connected with the gate electrode of the fourth NMOS transistor MN4 and the drain electrode of the fifth NMOS transistor MN5 in a branch manner; the source electrode of the fourth NMOS transistor MN4, the drain electrode of the sixth NMOS transistor MN6 and the gate electrode of the fifth NMOS transistor MN5 are connected, and the connected positions form the input end of a side position structure; the grid electrode of the sixth NMOS tube MN6 is in butt joint with the NMOS bias voltage Vbn; the drain electrode of the sixth PMOS tube MP6, the drain electrode of the seventh NMOS tube MN7 and one end of the first resistor R1 are connected, and the connected positions form the output end of the side position structure;

the source electrode of the fourth PMOS tube MP4, the source electrode of the fifth PMOS tube MP5 and the source electrode of the sixth PMOS tube MP6 in the two-side structure are connected with each other, and the connection position is butted with a power supply VDD; the grids of the fifth PMOS tube MP5 in the two-side structure are connected with each other, and the connection position is butted with a PMOS bias voltage Vbp; the source electrode of the sixth NMOS transistor MN6, the source electrode of the fifth NMOS transistor MN5 and the source electrode of the seventh NMOS transistor MN7 in the two side structures are connected with one another, and the connection positions are grounded; the other ends of the resistors R1 in the two side position structures are connected with each other, and the connected positions are respectively butted with the grid electrodes of the seventh NMOS tube MN7 in the two side position structures;

the input end of one side position structure forms the positive current input end of the trans-impedance amplifier, and the output end of the side position structure forms the negative voltage output end Vout-of the trans-impedance amplifier; the input end of the other side position structure forms a negative current input end of the transimpedance amplifier, and the output end of the side position structure forms a positive voltage output end Vout + of the transimpedance amplifier;

the positive current input end and the negative current input end of the transimpedance amplifier are respectively butted with the positive current output end and the negative current output end of the transimpedance amplifier, the positive current input end and the negative current input end of the transimpedance amplifier respectively receive a positive current signal and a negative current signal output by the transimpedance amplifier, and the positive voltage output end Vout + and the negative voltage output end Vout-of the transimpedance amplifier respectively realize the output of a positive voltage signal and the output of a negative voltage signal aiming at the voltage signals obtained by processing.

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