CN113422586A - High-energy-efficiency equalizer architecture - Google Patents
High-energy-efficiency equalizer architecture Download PDFInfo
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- CN113422586A CN113422586A CN202110766482.1A CN202110766482A CN113422586A CN 113422586 A CN113422586 A CN 113422586A CN 202110766482 A CN202110766482 A CN 202110766482A CN 113422586 A CN113422586 A CN 113422586A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45022—One or more added resistors to the amplifying transistors in the differential amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises: a filtering module for filtering an input signal; the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The high-energy-efficiency equalizer architecture provided by the embodiment of the invention can obtain double transconductance by accessing the complementary transconductance pipe and using the same transconductance amplification stage current, and meanwhile, the output transimpedance stage can still keep constant bandwidth and gain, thereby achieving the effects of strong compensation capability and strong driving capability compared with the traditional linear equalizer architecture.
Description
Technical Field
Embodiments of the present invention relate to integrated circuit technologies, and in particular, to an energy efficient equalizer architecture.
Background
When high-speed serial data is transmitted, due to the influence of non-ideal factors such as skin effect, dielectric loss and the like, high-frequency components of signals are seriously attenuated, so that code elements are distorted, and interference, namely intersymbol interference, is generated on code element judgment. The faster the data transmission rate, the more significant the impact of intersymbol interference. In order to increase the channel bandwidth, a Continuous Time Linear Equalizer (CTLE) is used. Equalizers are a technique used to compensate for signal transmission loss in a communication system and can reverse signal distortion and improve eye diagram quality. A Continuous Time Linear Equalizer (CTLE) is a core device of a receiving end (RX) of a communication system. The traditional CTLE based on a Current Mode Logic (CML) of a source degeneration structure realizes the high-pass characteristic of a closed loop through a low-pass feedback network formed by source degeneration resistance capacitors. The CTLE based on gm-TIA (transconductance-transimpedance amplifier) shows the equalization potential of higher frequency in high-speed data transmission, and the advantages of signal swing and area are more obvious under the condition of limited power supply voltage. Whereas the CTLE based on gm-TIA consists of two stages: the transconductance amplifier stage and the transimpedance amplifier stage are formed, so that more power consumption is required than that of the traditional CML-type CTLE.
Disclosure of Invention
The invention provides an equalizer architecture with high energy efficiency, so that the effects of strong compensation capability and strong driving capability are achieved, and the user experience is improved.
An embodiment of the present invention provides an energy-efficient equalizer architecture, including:
a filtering module for filtering an input signal;
the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal.
Optionally, the filtering module includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter.
Optionally, the processing module includes a plurality of complementary connected NMOS transistors and/or PMOS transistors.
Optionally, the processing module includes a TIA amplifier, and the TIA amplifier is configured to convert the current signal into a voltage signal.
Optionally, the processing module includes an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs4, a resistor Rs4, a MOS transistor M53, a MOS transistor M54, a MOS transistor M51, a MOS transistor M52, a resistor Rs5, and a capacitor Cs5, a first end of the capacitor Cs4 is connected to the voltage terminal VDD, a second end of the capacitor Cs4 is connected to the second end of the resistor Rs4, a gate of the MOS transistor M53 is connected to the input terminal Vin +, a drain of the MOS transistor M53 is connected to the first end of the resistor Rs4, a source of the MOS transistor M53 is connected to the converting module, a drain of the MOS transistor M54 is connected to the second end of the resistor Rs4, a gate of the MOS transistor M54 is connected to the input terminal Vin-, a source of the MOS transistor M54 is connected to the converting module, a drain of the MOS transistor M51 is connected to the converting module, a gate of the MOS transistor M51 is connected to the input terminal Vin +, the source of the MOS transistor M51 is connected to the first end of the resistor Rs5, the drain of the MOS transistor M52 is connected to the conversion module, the gate of the MOS transistor M52 is connected to the input terminal Vin-, the source of the MOS transistor M52 is connected to the second end of the resistor Rs5, the first end of the capacitor Cs5 is connected to the first end of the resistor Rs5, and the second end of the capacitor Cs5 is connected to the second end of the resistor Rs 5.
Optionally, the conversion module includes a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R8 is connected to the TIA amplifier, a second end of the resistor R8 is connected to a first end of the inductor L7, a second end of the inductor L7 is connected to the output terminal Vout +, a first end of the resistor R9 is connected to the TIA amplifier, a second end of the resistor R9 is connected to a first end of the inductor L8, and a second end of the inductor L8 is connected to the output terminal Vout-.
Optionally, the processing module includes an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a resistor R10, a MOS transistor M63, a MOS transistor M64, a MOS transistor M61, a MOS transistor M62, a resistor Rs6, and a capacitor Cs6, a first end of the resistor R10 is connected to the voltage terminal VDD, a second end of the resistor R10 is connected to the voltage terminal VDD, a gate of the MOS transistor M63 is connected to the input terminal Vin +, a drain of the MOS transistor M63 is connected to the first end of the resistor R10, a source of the MOS transistor M63 is connected to the converting module, a drain of the MOS transistor M64 is connected to the second end of the resistor R10, a gate of the MOS transistor M64 is connected to the input terminal Vin-, a source of the MOS transistor M64 is connected to the converting module, a drain of the MOS transistor M61 is connected to the converting module, a gate of the MOS transistor M61 is connected to the input terminal Vin +, a source of the MOS transistor M61 is connected to the first end of the resistor Rs6, the drain of the MOS transistor M62 is connected to the conversion module, the gate of the MOS transistor M62 is connected to the input terminal Vin-, the source of the MOS transistor M62 is connected to the second terminal of the resistor Rs6, the first terminal of the capacitor Cs6 is connected to the first terminal of the resistor Rs6, and the second terminal of the capacitor Cs6 is connected to the second terminal of the resistor Rs 6.
Optionally, the conversion module includes a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R11 is connected to the TIA amplifier, a second end of the resistor R11 is connected to a first end of the inductor L9, a second end of the inductor L9 is connected to the output terminal Vout +, a first end of the resistor R12 is connected to the TIA amplifier, a second end of the resistor R12 is connected to a first end of the inductor L10, and a second end of the inductor L10 is connected to the output terminal Vout-.
Optionally, the processing module includes an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs7, a resistor Rs7, a MOS transistor M73, a MOS transistor M74, a MOS transistor M75, a MOS transistor M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS transistor M75, and a MOS transistor M76, a first end of the capacitor Cs7 is connected to the voltage terminal VDD, a second end of the capacitor Cs7 is connected to the second end of the resistor Rs7, a gate of the MOS transistor M73 is connected to the input terminal Vin +, a drain of the MOS transistor M73 is connected to the first end of the resistor Rs7, a source of the MOS transistor M73 is connected to the converting module, a drain of the MOS transistor M74 is connected to the second end of the resistor Rs7, a gate of the MOS transistor M74 is connected to the input terminal Vin +, a source of the transistor M74 is connected to the converting module, a drain of the MOS transistor M75 is connected to the converting module, a gate of the transistor M75 is connected to the input terminal Vin +, the source of the MOS transistor M75 is connected to the first end of the resistor Rs8, the drain of the MOS transistor M76 is connected to the conversion module, the gate of the MOS transistor M76 is connected to the input terminal Vin-, the source of the MOS transistor M76 is connected to the second end of the resistor Rs8, the first end of the capacitor Cs8 is connected to the first end of the resistor Rs8, and the second end of the capacitor Cs8 is connected to the second end of the resistor Rs 8.
Optionally, the conversion module includes a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R14 is connected to the TIA amplifier, a second end of the resistor R14 is connected to a first end of the inductor L11, a second end of the inductor L11 is connected to the output terminal Vout +, a first end of the resistor R15 is connected to the TIA amplifier, a second end of the resistor R15 is connected to a first end of the inductor L12, and a second end of the inductor L12 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises: a filtering module for filtering an input signal; the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The high-energy-efficiency equalizer architecture provided by the embodiment of the invention can obtain double transconductance by accessing the complementary transconductance pipe and using the same transconductance amplification stage current, and meanwhile, the output transimpedance stage can still keep constant bandwidth and gain, thereby achieving the effects of strong compensation capability and strong driving capability compared with the traditional linear equalizer architecture.
Drawings
Fig. 1 is a block diagram of an embodiment of an efficient equalizer architecture;
fig. 2 is a schematic structural diagram of an embodiment of an energy-efficient equalizer architecture;
FIG. 3 is a circuit diagram of an embodiment of an equalizer architecture with high performance;
fig. 4 is a circuit diagram of an efficient equalizer architecture according to a second embodiment of the present invention;
fig. 5 is a circuit diagram of an energy-efficient equalizer architecture according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first module may be termed a second module, and, similarly, a second module may be termed a first module, without departing from the scope of the present application. The first module and the second module are both modules, but they are not the same module. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic block diagram of an energy-efficient equalizer architecture according to an embodiment of the present invention, where the energy-efficient equalizer architecture according to the embodiment of the present invention is suitable for solving a problem that a conventional gm-TIA-based CTLE is not high in energy efficiency, and specifically, the energy-efficient equalizer architecture according to the embodiment of the present invention includes: the device comprises a filtering module 1, a processing module 2 and a conversion module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, fig. 2 is a schematic structural diagram in this embodiment, a filtering module 1 belongs to an added part, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter, and for different filters, the strength of a signal of each frequency is different, so that a signal in a certain frequency range is allowed to pass through, and signals in other frequency ranges are blocked or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 includes a plurality of complementary MOS transistors, and the processing module 2 is configured to transconductance-amplify a current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of complementary connected NMOS transistors and/or PMOS transistors, gmp and gmn represent transconductances generated by a PMOS pair and an NMOS pair of the transconductance stage band source degeneration network, respectively, and the TIA is responsible for converting a current signal into a voltage signal. The PMOS pair and the NMOS pair can be added with filters for extracting signals of different frequency bands, adjusting a source degeneration network and adjusting the addition and subtraction relation of gmp and gmn, so that rich equalization effect can be obtained.
Fig. 3 is a circuit diagram in this embodiment, the processing module 2 includes an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs4, a resistor Rs4, a MOS transistor M53, a MOS transistor M54, a MOS transistor M51, a MOS transistor M52, a resistor Rs5, and a capacitor Cs5, a first end of the capacitor Cs4 is connected to the voltage terminal VDD, a second end of the capacitor Cs4 is connected to the second end of the resistor Rs4, a gate of the MOS transistor M53 is connected to the input terminal Vin +, a drain of the MOS transistor M53 is connected to the first end of the resistor Rs4, a source of the MOS transistor M53 is connected to the converting module 3, a drain of the MOS transistor M54 is connected to the second end of the resistor Rs4, a gate of the MOS transistor M54 is connected to the input terminal, a source of the MOS transistor M54 is connected to the converting module 3, a drain of the MOS transistor M51 is connected to the converting module 3, a gate of the transistor M51 is connected to the input terminal Vin +, and a first end of the transistor M5 is connected to the converting module 3, a second end of the converting module M3, a second end of the transistor M3 is connected to the input terminal Vin + and a voltage terminal, the source of the MOS transistor M51 is connected to the first end of the resistor Rs5, the drain of the MOS transistor M52 is connected to the conversion module 3, the gate of the MOS transistor M52 is connected to the input terminal Vin-, the source of the MOS transistor M52 is connected to the second end of the resistor Rs5, the first end of the capacitor Cs5 is connected to the first end of the resistor Rs5, and the second end of the capacitor Cs5 is connected to the second end of the resistor Rs 5.
In this embodiment, a complementary PMOS transistor and source degeneration network are added to the transconductance stage, so that the transconductance stage obtains double transconductance at the same current. Setting gmn as transconductance provided by an NMOS and a source electrode degradation network of a transconductance amplifier stage, gmp as transconductance provided by a PMOS and a source electrode degradation network of the transconductance amplifier stage, TIA(s) as a transfer function of TIA, and CTLE as a simple transfer function:
compared with the compensation capability in the prior art, the compensation capability in the embodiment is doubled.
The conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 includes a TIA amplifier, which is configured to convert a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which is not specifically limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as those commonly used in optical-electrical transmission communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R8 is connected to the TIA amplifier, a second end of the resistor R8 is connected to a first end of the inductor L7, a second end of the inductor L7 is connected to the output terminal Vout +, a first end of the resistor R9 is connected to the TIA amplifier, a second end of the resistor R9 is connected to a first end of the inductor L8, and a second end of the inductor L8 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises: a filtering module for filtering an input signal; the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The high-energy-efficiency equalizer architecture provided by the embodiment of the invention can obtain double transconductance by accessing the complementary transconductance pipe and using the same transconductance amplification stage current, and meanwhile, the output transimpedance stage can still keep constant bandwidth and gain, thereby achieving the effects of strong compensation capability and strong driving capability compared with the traditional linear equalizer architecture.
Example two
The embodiment of the present invention provides an energy-efficient equalizer architecture, which is suitable for solving the problem of low energy efficiency of the conventional gm-TIA-based CTLE, and specifically, the embodiment of the present invention provides an energy-efficient equalizer architecture, including: the device comprises a filtering module 1, a processing module 2 and a conversion module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, the filtering module 1 belongs to an adding part, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter, and for different filters, the strength of a signal of each frequency is different, so that a signal in a certain frequency range is allowed to pass through, and signals in other frequency ranges are blocked or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 includes a plurality of complementary MOS transistors, and the processing module 2 is configured to transconductance-amplify a current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of complementary connected NMOS transistors and/or PMOS transistors, gmp and gmn represent transconductances generated by a PMOS pair and an NMOS pair of the transconductance stage band source degeneration network, respectively, and the TIA is responsible for converting a current signal into a voltage signal. The PMOS pair and the NMOS pair can be added with filters for extracting signals of different frequency bands, adjusting a source degeneration network and adjusting the addition and subtraction relation of gmp and gmn, so that rich equalization effect can be obtained.
Fig. 4 is a circuit diagram in the present embodiment, the processing module 2 includes an input terminal Vin +, a voltage terminal VDD, a resistor R10, a MOS transistor M63, a MOS transistor M64, a MOS transistor M61, a MOS transistor M62, a resistor Rs6, and a capacitor Cs6, a first end of the resistor R10 is connected to the voltage terminal VDD, a second end of the resistor R10 is connected to the voltage terminal VDD, a gate of the MOS transistor M63 is connected to the input terminal Vin +, a drain of the MOS transistor M63 is connected to the first end of the resistor R10, a source of the MOS transistor M63 is connected to the converting module 3, a drain of the MOS transistor M64 is connected to the second end of the resistor R10, a gate of the MOS transistor M64 is connected to the input terminal Vin-, a source of the MOS transistor M64 is connected to the converting module 3, a drain of the MOS transistor M61 is connected to the converting module 3, a gate of the MOS transistor M61 is connected to the input terminal Vin +, the source of the MOS transistor M61 is connected to the first end of the resistor Rs6, the drain of the MOS transistor M62 is connected to the conversion module 3, the gate of the MOS transistor M62 is connected to the input terminal Vin-, the source of the MOS transistor M62 is connected to the second end of the resistor Rs6, the first end of the capacitor Cs6 is connected to the first end of the resistor Rs6, and the second end of the capacitor Cs6 is connected to the second end of the resistor Rs 6.
In this embodiment, two signal paths are designed, and a low-pass filter is added to one input end, so that the transfer function of the low-pass filter is expressed as a low-pass. The de-emphasis is achieved by subtracting the low-pass input current from the high-pass input current, which is represented by subtracting the low-frequency part from the high-pass filter, and compensating for the medium-frequency part relative to the high-frequency part, which also saves additional branch current compared to fig. 2. Let gmn(s) be the transconductance provided by the NMOS and source degeneration network in the transconductance amplifier stage, gmp(s) be the transconductance provided by the PMOS and source degeneration network in the transconductance amplifier stage, lpf(s) be the transfer function of the low pass filtering, TIA(s) be the transfer function of TIA, and the simple transfer function of CTLE be:
the conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 includes a TIA amplifier, which is configured to convert a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which is not specifically limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as those commonly used in optical-electrical transmission communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R11 is connected to the TIA amplifier, a second end of the resistor R11 is connected to a first end of the inductor L9, a second end of the inductor L9 is connected to the output terminal Vout +, a first end of the resistor R12 is connected to the TIA amplifier, a second end of the resistor R12 is connected to a first end of the inductor L10, and a second end of the inductor L10 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises: a filtering module for filtering an input signal; the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The high-energy-efficiency equalizer architecture provided by the embodiment of the invention can obtain double transconductance by accessing the complementary transconductance pipe and using the same transconductance amplification stage current, and meanwhile, the output transimpedance stage can still keep constant bandwidth and gain, thereby achieving the effects of strong compensation capability and strong driving capability compared with the traditional linear equalizer architecture.
EXAMPLE III
The embodiment of the present invention provides an energy-efficient equalizer architecture, which is suitable for solving the problem of low energy efficiency of the conventional gm-TIA-based CTLE, and specifically, the embodiment of the present invention provides an energy-efficient equalizer architecture, including: the device comprises a filtering module 1, a processing module 2 and a conversion module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, the filtering module 1 belongs to an adding part, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter, and for different filters, the strength of a signal of each frequency is different, so that a signal in a certain frequency range is allowed to pass through, and signals in other frequency ranges are blocked or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 includes a plurality of complementary MOS transistors, and the processing module 2 is configured to transconductance-amplify a current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of complementary connected NMOS transistors and/or PMOS transistors, gmp and gmn represent transconductances generated by a PMOS pair and an NMOS pair of the transconductance stage band source degeneration network, respectively, and the TIA is responsible for converting a current signal into a voltage signal. The PMOS pair and the NMOS pair can be added with filters for extracting signals of different frequency bands, adjusting a source degeneration network and adjusting the addition and subtraction relation of gmp and gmn, so that rich equalization effect can be obtained.
Fig. 5 is a circuit diagram in the present embodiment, the processing module 2 includes an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs7, a resistor Rs7, a MOS transistor M73, a MOS transistor M74, a MOS transistor M75, a MOS transistor M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS transistor M75, and a MOS transistor M76, a first end of the capacitor Cs7 is connected to the voltage terminal VDD, a second end of the capacitor Cs7 is connected to the second end of the resistor Rs7, a gate of the MOS transistor M73 is connected to the input terminal Vin +, a drain of the MOS transistor M73 is connected to the first end of the resistor Rs7, a source of the MOS transistor M73 is connected to the converting module 3, a drain of the MOS transistor M74 is connected to the second end of the resistor Rs7, a gate of the MOS transistor M74 is connected to the input terminal Vin-, a source of the MOS transistor M74 is connected to the converting module 3, a drain of the transistor M75 is connected to the converting module 3, the gate of the MOS transistor M75 is connected to the input terminal Vin +, the source of the MOS transistor M75 is connected to the first terminal of the resistor Rs8, the drain of the MOS transistor M76 is connected to the conversion module 3, the gate of the MOS transistor M76 is connected to the input terminal Vin-, the source of the MOS transistor M76 is connected to the second terminal of the resistor Rs8, the first terminal of the capacitor Cs8 is connected to the first terminal of the resistor Rs8, and the second terminal of the capacitor Cs8 is connected to the second terminal of the resistor Rs 8.
In this embodiment, compared with the first embodiment and the second embodiment, the circuit structure provided by this embodiment has a larger adjustment range of the high-frequency compensation capability.
The conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 includes a TIA amplifier, which is configured to convert a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which is not specifically limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as those commonly used in optical-electrical transmission communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output terminal Vout + and an output terminal Vout-, a first end of the resistor R14 is connected to the TIA amplifier, a second end of the resistor R14 is connected to a first end of the inductor L11, a second end of the inductor L11 is connected to the output terminal Vout +, a first end of the resistor R15 is connected to the TIA amplifier, a second end of the resistor R15 is connected to a first end of the inductor L12, and a second end of the inductor L12 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises: a filtering module for filtering an input signal; the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The high-energy-efficiency equalizer architecture provided by the embodiment of the invention can obtain double transconductance by accessing the complementary transconductance pipe and using the same transconductance amplification stage current, and meanwhile, the output transimpedance stage can still keep constant bandwidth and gain, thereby achieving the effects of strong compensation capability and strong driving capability compared with the traditional linear equalizer architecture.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An energy-efficient equalizer architecture, comprising:
a filtering module for filtering an input signal;
the processing module is connected with the filtering module and comprises a plurality of complementary MOS (metal oxide semiconductor) tubes, and the processing module is used for transconductance amplification of a current signal of the input signal;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal.
2. The energy efficient equalizer architecture of claim 1, wherein the filtering module comprises a low pass filter, a high pass filter, a band pass filter, or an all pass filter.
3. The energy efficient equalizer architecture of claim 1, wherein the processing module comprises a plurality of complementary connected NMOS and/or PMOS transistors.
4. The energy efficient equalizer architecture of claim 1, wherein the processing module comprises a TIA amplifier to convert a current signal to a voltage signal.
5. The architecture of the energy efficient equalizer according to claim 1, wherein the processing module comprises an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs4, a resistor Rs4, a MOS transistor M53, a MOS transistor M54, a MOS transistor M51, a MOS transistor M52, a resistor Rs5, and a capacitor Cs5, a first terminal of the capacitor Cs4 is connected to the voltage terminal VDD, a second terminal of the capacitor Cs4 is connected to a second terminal of the resistor Rs4, a gate of the MOS transistor M53 is connected to the input terminal Vin +, a drain of the MOS transistor M53 is connected to a first terminal of the resistor Rs4, a source of the MOS transistor M53 is connected to the conversion module, a drain of the MOS transistor M54 is connected to a second terminal of the resistor Rs4, a gate of the MOS transistor M54 is connected to the input terminal Vin-, a source of the MOS transistor M54 is connected to the conversion module, a drain of the MOS transistor M51 is connected to the conversion module, the gate of the MOS transistor M51 is connected to the input terminal Vin +, the source of the MOS transistor M51 is connected to the first terminal of the resistor Rs5, the drain of the MOS transistor M52 is connected to the conversion module, the gate of the MOS transistor M52 is connected to the input terminal Vin-, the source of the MOS transistor M52 is connected to the second terminal of the resistor Rs5, the first terminal of the capacitor Cs5 is connected to the first terminal of the resistor Rs5, and the second terminal of the capacitor Cs5 is connected to the second terminal of the resistor Rs 5.
6. The energy efficient equalizer architecture as claimed in claim 5, wherein said conversion module comprises a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output terminal Vout +, and an output terminal Vout-, wherein a first terminal of said resistor R8 is connected to said TIA amplifier, a second terminal of said resistor R8 is connected to a first terminal of said inductor L7, a second terminal of said inductor L7 is connected to said output terminal Vout +, a first terminal of said resistor R9 is connected to said TIA amplifier, a second terminal of said resistor R9 is connected to a first terminal of said inductor L8, and a second terminal of said inductor L8 is connected to said output terminal Vout-.
7. An energy efficient equalizer architecture as claimed in claim 1, wherein said processing module comprises an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a resistor R10, a MOS transistor M63, a MOS transistor M64, a MOS transistor M61, a MOS transistor M62, a resistor Rs6 and a capacitor Cs6, a first terminal of said resistor R10 is connected to said voltage terminal VDD, a second terminal of said resistor R10 is connected to said voltage terminal VDD, a gate of said MOS transistor M63 is connected to said input terminal Vin +, a drain of said MOS transistor M63 is connected to a first terminal of said resistor R10, a source of said MOS transistor M63 is connected to said conversion module, a drain of said MOS transistor M64 is connected to a second terminal of said resistor R10, a gate of said MOS transistor M64 is connected to said input terminal Vin-, a source of said MOS transistor M64 is connected to said conversion module, a drain of said MOS transistor M61 is connected to said conversion module, the gate of the MOS transistor M61 is connected to the input terminal Vin +, the source of the MOS transistor M61 is connected to the first terminal of the resistor Rs6, the drain of the MOS transistor M62 is connected to the conversion module, the gate of the MOS transistor M62 is connected to the input terminal Vin-, the source of the MOS transistor M62 is connected to the second terminal of the resistor Rs6, the first terminal of the capacitor Cs6 is connected to the first terminal of the resistor Rs6, and the second terminal of the capacitor Cs6 is connected to the second terminal of the resistor Rs 6.
8. The energy-efficient equalizer architecture of claim 7 wherein the conversion module comprises a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output terminal Vout +, and an output terminal Vout-, wherein a first terminal of the resistor R11 is connected to the TIA amplifier, a second terminal of the resistor R11 is connected to a first terminal of the inductor L9, a second terminal of the inductor L9 is connected to the output terminal Vout +, a first terminal of the resistor R12 is connected to the TIA amplifier, a second terminal of the resistor R12 is connected to a first terminal of the inductor L10, and a second terminal of the inductor L10 is connected to the output terminal Vout-.
9. The architecture of the energy efficient equalizer according to claim 1, wherein the processing module comprises an input terminal Vin +, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs7, a resistor Rs7, a MOS transistor M73, a MOS transistor M74, a MOS transistor M75, a MOS transistor M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS transistor M75 and a MOS transistor M76, a first end of the capacitor Cs7 is connected to the voltage terminal VDD, a second end of the capacitor Cs7 is connected to a second end of the resistor Rs7, a gate of the MOS transistor M73 is connected to the input terminal Vin +, a drain of the MOS transistor M73 is connected to a first end of the resistor Rs7, a source of the MOS transistor M73 is connected to the conversion module, a drain of the MOS transistor M74 is connected to a second end of the resistor Rs7, a gate of the MOS transistor M74 is connected to the input terminal Vin-, a source of the MOS transistor M74 is connected to the conversion module, the drain of the MOS transistor M75 is connected to the conversion module, the gate of the MOS transistor M75 is connected to the input terminal Vin +, the source of the MOS transistor M75 is connected to the first end of the resistor Rs8, the drain of the MOS transistor M76 is connected to the conversion module, the gate of the MOS transistor M76 is connected to the input terminal Vin-, the source of the MOS transistor M76 is connected to the second end of the resistor Rs8, the first end of the capacitor Cs8 is connected to the first end of the resistor Rs8, and the second end of the capacitor Cs8 is connected to the second end of the resistor Rs 8.
10. The energy efficient equalizer architecture as claimed in claim 9, wherein the conversion module comprises a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output terminal Vout +, and an output terminal Vout-, wherein a first terminal of the resistor R14 is connected to the TIA amplifier, a second terminal of the resistor R14 is connected to a first terminal of the inductor L11, a second terminal of the inductor L11 is connected to the output terminal Vout +, a first terminal of the resistor R15 is connected to the TIA amplifier, a second terminal of the resistor R15 is connected to a first terminal of the inductor L12, and a second terminal of the inductor L12 is connected to the output terminal Vout-.
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