CN113422586B - Energy-efficient equalizer architecture - Google Patents

Energy-efficient equalizer architecture Download PDF

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CN113422586B
CN113422586B CN202110766482.1A CN202110766482A CN113422586B CN 113422586 B CN113422586 B CN 113422586B CN 202110766482 A CN202110766482 A CN 202110766482A CN 113422586 B CN113422586 B CN 113422586B
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resistor
mos tube
inductor
mos
processing module
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CN113422586A (en
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潘权
罗雄师
王星博
陈隆宇
周文韬
王磊明
毛振江
于洪宇
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Southwest University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45022—One or more added resistors to the amplifying transistors in the differential amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises the following components: the filtering module is used for filtering the input signal; the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The equalizer architecture with high energy efficiency provided by the embodiment of the invention can obtain double transconductance by accessing the complementary type transconductor and using the same transconductance amplifying stage current, and meanwhile, the output transimpedance stage can still maintain constant bandwidth and gain, so that the effects of strong compensation capability and strong driving capability are achieved compared with the traditional linear equalizer architecture.

Description

Energy-efficient equalizer architecture
Technical Field
Embodiments of the present invention relate to integrated circuit technology, and more particularly, to an energy efficient equalizer architecture.
Background
When high-speed serial data is transmitted, high-frequency components of signals are seriously attenuated due to the influence of non-ideal factors such as skin effect, dielectric loss and the like, so that code element distortion is caused, and interference, namely intersymbol interference, is generated on code element judgment. The faster the data transmission rate, the more pronounced the effect of intersymbol interference. In order to increase the channel bandwidth, continuous time linear equalizers (Continuous Time Linear Equalizer, CTLE) need to be used. The equalizer is a technology for compensating signal transmission loss in a communication system, and can reverse signal distortion and improve eye diagram quality. The continuous time linear equalizer (Continuous Time Linear Equalizer, CTLE) is a core device of a receiving end (RX) of the communication system. The CTLE of the traditional current type logic circuit (current mode logic, CML) based on the source degeneration structure realizes the high-pass characteristic of a closed loop through a low-pass feedback network formed by source degeneration resistance and capacitance. CTLEs based on gm-TIA (transconductance-transimpedance amplifiers) exhibit a higher frequency equalization potential for high-rate data transmission, and have more significant signal swing and area advantages at limited supply voltages. However gm-TIA based CTLE is composed of two stages: the transconductance amplifier stage and the transimpedance amplifier stage are configured so that more power consumption is required than in the conventional CML CTLE.
Disclosure of Invention
The invention provides an energy-efficient equalizer architecture, so that the effects of strong compensation capability and strong driving capability are achieved, and the user experience is improved.
The embodiment of the invention provides an energy-efficient equalizer architecture, which comprises the following components:
the filtering module is used for filtering the input signal;
the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal.
Optionally, the filtering module includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter.
Optionally, the processing module includes a plurality of NMOS tubes and/or PMOS tubes that are complementarily connected.
Optionally, the processing module includes a TIA amplifier for converting a current signal to a voltage signal.
Optionally, the processing module includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs4, a resistor Rs4, a MOS transistor M53, a MOS transistor M54, a MOS transistor M51, a MOS transistor M52, a resistor Rs5, and a capacitor Cs5, a first terminal of the capacitor Cs4 is connected to the voltage terminal VDD, a second terminal of the capacitor Cs4 is connected to a second terminal of the resistor Rs4, a gate of the MOS transistor M53 is connected to the input terminal vin+, a drain of the MOS transistor M53 is connected to a first terminal of the resistor Rs4, a source of the MOS transistor M53 is connected to the switching module, a drain of the MOS transistor M54 is connected to a second terminal of the resistor Rs4, a source of the MOS transistor M54 is connected to the switching module, a drain of the MOS transistor M51 is connected to the switching module, a gate of the MOS transistor M51 is connected to the second terminal of the MOS transistor M5, a drain of the MOS transistor M54 is connected to the second terminal of the MOS transistor M5, a drain of the MOS transistor M5 is connected to the second terminal of the switching module is connected to the second terminal of the MOS transistor M5.
Optionally, the conversion module includes a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output terminal vout+ and an output terminal Vout-, a first end of the resistor R8 is connected to the TIA amplifier, a second end of the resistor R8 is connected to the first end of the inductor L7, a second end of the inductor L7 is connected to the output terminal vout+, a first end of the resistor R9 is connected to the TIA amplifier, a second end of the resistor R9 is connected to the first end of the inductor L8, and a second end of the inductor L8 is connected to the output terminal Vout-.
Optionally, the processing module includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a resistor R10, a MOS transistor M63, a MOS transistor M64, a MOS transistor M61, a MOS transistor M62, a resistor Rs6, and a capacitor Cs6, a first terminal of the resistor R10 is connected to the voltage terminal VDD, a second terminal of the resistor R10 is connected to the voltage terminal VDD, a gate of the MOS transistor M63 is connected to the input terminal vin+, a drain of the MOS transistor M63 is connected to a first terminal of the resistor R10, a source of the MOS transistor M63 is connected to the switching module, a drain of the MOS transistor M64 is connected to a second terminal of the resistor R10, a source of the MOS transistor M64 is connected to the switching module, a drain of the MOS transistor M61 is connected to the switching module, a gate of the MOS transistor M61 is connected to the second terminal of the resistor Rs6, a drain of the MOS transistor M62 is connected to the second terminal of the resistor Rs6 is connected to the capacitor Cs 6.
Optionally, the conversion module includes a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output terminal vout+ and an output terminal Vout-, where a first end of the resistor R11 is connected to the TIA amplifier, a second end of the resistor R11 is connected to the first end of the inductor L9, a second end of the inductor L9 is connected to the output terminal vout+, a first end of the resistor R12 is connected to the TIA amplifier, a second end of the resistor R12 is connected to the first end of the inductor L10, and a second end of the inductor L10 is connected to the output terminal Vout-.
Optionally, the processing module includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs7, a resistor Rs7, a MOS transistor M73, a MOS transistor M74, a MOS transistor M75, a MOS transistor M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS transistor M75, and a MOS transistor M76, a first terminal of the capacitor Cs7 is connected to the voltage terminal VDD, a second terminal of the capacitor Cs7 is connected to a second terminal of the resistor Rs7, a gate of the MOS transistor M73 is connected to the input terminal vin+, a drain of the MOS transistor M73 is connected to a first terminal of the resistor Rs7, a source of the MOS transistor M73 is connected to the switching module, a drain of the MOS transistor M74 is connected to a second terminal of the resistor Rs7, a gate of the MOS transistor M74 is connected to the input terminal Vin-, a source of the MOS transistor M74 is connected to the switching module, a drain of the MOS transistor M75 is connected to the second terminal of the MOS transistor M8 is connected to the second terminal of the resistor Rs8, a drain of the MOS transistor M75 is connected to the second terminal of the resistor Rs 76.
Optionally, the conversion module includes a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output terminal vout+ and an output terminal Vout-, where a first end of the resistor R14 is connected to the TIA amplifier, a second end of the resistor R14 is connected to the first end of the inductor L11, a second end of the inductor L11 is connected to the output terminal vout+, a first end of the resistor R15 is connected to the TIA amplifier, a second end of the resistor R15 is connected to the first end of the inductor L12, and a second end of the inductor L12 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises the following components: the filtering module is used for filtering the input signal; the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The equalizer architecture with high energy efficiency provided by the embodiment of the invention can obtain double transconductance by accessing the complementary type transconductor and using the same transconductance amplifying stage current, and meanwhile, the output transimpedance stage can still maintain constant bandwidth and gain, so that the effects of strong compensation capability and strong driving capability are achieved compared with the traditional linear equalizer architecture.
Drawings
Fig. 1 is a schematic block diagram of an energy-efficient equalizer architecture according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of an equalizer architecture with high energy efficiency according to a first embodiment of the present invention;
fig. 3 is a circuit diagram of an energy-efficient equalizer architecture according to a first embodiment of the present invention;
fig. 4 is a circuit diagram of an equalizer architecture with high energy efficiency according to a second embodiment of the present invention;
fig. 5 is a circuit diagram of an equalizer architecture with high energy efficiency according to a third embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Furthermore, the terms "first," "second," and the like, may be used herein to describe various directions, acts, steps, or elements, etc., but these directions, acts, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module, without departing from the scope of the present application. Both the first module and the second module are modules, but they are not the same module. The terms "first," "second," and the like, are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Example 1
Fig. 1 is a schematic block diagram of an energy-efficient equalizer architecture according to a first embodiment of the present invention, where the energy-efficient equalizer architecture according to the first embodiment of the present invention is suitable for solving the problem that a conventional gm-TIA-based CTLE has low energy efficiency, and specifically, the energy-efficient equalizer architecture according to the first embodiment of the present invention includes: a filtering module 1, a processing module 2 and a converting module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, fig. 2 is a schematic structural diagram in this embodiment, where the filtering module 1 belongs to an adding portion, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter, or an all-pass filter, and for different filters, the intensity of signals of each frequency is different, so that signals in a certain frequency range are allowed to pass, and signals in other frequency ranges are prevented or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 comprises a plurality of complementary MOS tubes, and the processing module 2 is used for transconductance amplifying the current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of NMOS transistors and/or PMOS transistors that are complementarily connected, gmp and gmn represent transconductances generated by PMOS pairs and NMOS pairs of the transconductance stage with source degeneration network, respectively, and the TIA is responsible for converting the current signal into the voltage signal. The input of the PMOS pair and the NMOS pair can be added with a filter for extracting signals in different frequency bands, a source degradation network is adjusted, and the addition and subtraction relation between gmp and gmn is adjusted, so that a rich equalization effect can be obtained.
Fig. 3 is a circuit diagram in this embodiment, the processing module 2 includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs4, a resistor Rs4, a MOS transistor M53, a MOS transistor M54, a MOS transistor M51, a MOS transistor M52, a resistor Rs5, and a capacitor Cs5, a first terminal of the capacitor Cs4 is connected to the voltage terminal VDD, a second terminal of the capacitor Cs4 is connected to a second terminal of the resistor Rs4, a gate of the MOS transistor M53 is connected to the input terminal vin+, a drain of the MOS transistor M53 is connected to a first terminal of the resistor Rs4, a source of the MOS transistor M53 is connected to the conversion module 3, a drain of the MOS transistor M54 is connected to a second terminal of the resistor Rs4, a gate of the MOS transistor M54 is connected to the input terminal Vin-, a source of the MOS transistor M54 is connected to the conversion module 3, a drain of the MOS transistor M51 is connected to the second terminal of the MOS transistor M5, a drain of the MOS transistor M5 is connected to the second terminal of the resistor Rs5, a drain of the MOS transistor M52 is connected to the second terminal of the MOS transistor M5.
In this embodiment, a complementary PMOS transistor and source degeneration network are added to the transconductance stage, so that the transconductance stage obtains double transconductance under the same current. Let gmn be the transconductance provided by the NMOS and source degeneration network of the transconductance amplifier stage, gmp be the transconductance provided by the PMOS and source degeneration network of the transconductance amplifier stage, TIA(s) be the transfer function of TIA, and the simple transfer function of CTLE is:
Figure BDA0003151855740000081
the present embodiment is doubled compared to the compensation capability of the prior art.
The conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 comprises a TIA amplifier for converting a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which are not particularly limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as optical-to-electrical communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output terminal vout+ and an output terminal Vout-, wherein a first end of the resistor R8 is connected to the TIA amplifier, a second end of the resistor R8 is connected to the first end of the inductor L7, a second end of the inductor L7 is connected to the output terminal vout+, a first end of the resistor R9 is connected to the TIA amplifier, a second end of the resistor R9 is connected to the first end of the inductor L8, and a second end of the inductor L8 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises the following components: the filtering module is used for filtering the input signal; the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The equalizer architecture with high energy efficiency provided by the embodiment of the invention can obtain double transconductance by accessing the complementary type transconductor and using the same transconductance amplifying stage current, and meanwhile, the output transimpedance stage can still maintain constant bandwidth and gain, so that the effects of strong compensation capability and strong driving capability are achieved compared with the traditional linear equalizer architecture.
Example two
The equalizer architecture with high energy efficiency provided by the embodiment of the invention is suitable for solving the problem that the traditional CTLE based on gm-TIA has low energy efficiency, and specifically, the equalizer architecture with high energy efficiency provided by the embodiment of the invention comprises the following components: a filtering module 1, a processing module 2 and a converting module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, the filtering module 1 belongs to an adding part, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter or an all-pass filter, and for different filters, the signal strength of each frequency is different, so that the signal in a certain frequency range is allowed to pass, and the signals in other frequency ranges are prevented or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 comprises a plurality of complementary MOS tubes, and the processing module 2 is used for transconductance amplifying the current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of NMOS transistors and/or PMOS transistors that are complementarily connected, gmp and gmn represent transconductances generated by PMOS pairs and NMOS pairs of the transconductance stage with source degeneration network, respectively, and the TIA is responsible for converting the current signal into the voltage signal. The input of the PMOS pair and the NMOS pair can be added with a filter for extracting signals in different frequency bands, a source degradation network is adjusted, and the addition and subtraction relation between gmp and gmn is adjusted, so that a rich equalization effect can be obtained.
Fig. 4 is a circuit diagram in this embodiment, the processing module 2 includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a resistor R10, a MOS transistor M63, a MOS transistor M64, a MOS transistor M61, a MOS transistor M62, a resistor Rs6, and a capacitor Cs6, a first terminal of the resistor R10 is connected to the voltage terminal VDD, a second terminal of the resistor R10 is connected to the voltage terminal VDD, a gate of the MOS transistor M63 is connected to the input terminal vin+, a drain of the MOS transistor M63 is connected to a first terminal of the resistor R10, a source of the MOS transistor M63 is connected to the switching module 3, a drain of the MOS transistor M64 is connected to a second terminal of the resistor R10, a source of the MOS transistor M64 is connected to the switching module 3, a drain of the MOS transistor M61 is connected to the switching module 3, a gate of the MOS transistor M61 is connected to the first terminal of the resistor R6 is connected to the second terminal of the resistor Rs6, a drain of the MOS transistor M64 is connected to the second terminal of the resistor Rs 6.
In this embodiment, by designing two signal paths, a low-pass filter is added to one input terminal, so that the transfer function is represented as a low-pass. The de-emphasis is achieved by subtracting the low-pass input and the high-pass input current, which is manifested as subtracting the low-frequency part by high-pass filtering, with the intermediate frequency being compensated for relative to the high frequency, and with additional branch current being saved compared to fig. 2. Let gmn(s) be the transconductance provided by NMOS and source degeneration networks of transconductance amplifier stage, gmp(s) be the transconductance provided by PMOS and source degeneration networks of transconductance amplifier stage, LPF(s) be the transfer function of low pass filtering, TIA(s) be the transfer function of TIA, CTLE's simple transfer function is:
Figure BDA0003151855740000111
the conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 comprises a TIA amplifier for converting a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which are not particularly limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as optical-to-electrical communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output terminal vout+ and an output terminal Vout-, wherein a first end of the resistor R11 is connected to the TIA amplifier, a second end of the resistor R11 is connected to the first end of the inductor L9, a second end of the inductor L9 is connected to the output terminal vout+, a first end of the resistor R12 is connected to the TIA amplifier, a second end of the resistor R12 is connected to the first end of the inductor L10, and a second end of the inductor L10 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises the following components: the filtering module is used for filtering the input signal; the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The equalizer architecture with high energy efficiency provided by the embodiment of the invention can obtain double transconductance by accessing the complementary type transconductor and using the same transconductance amplifying stage current, and meanwhile, the output transimpedance stage can still maintain constant bandwidth and gain, so that the effects of strong compensation capability and strong driving capability are achieved compared with the traditional linear equalizer architecture.
Example III
The equalizer architecture with high energy efficiency provided by the embodiment of the invention is suitable for solving the problem that the traditional CTLE based on gm-TIA has low energy efficiency, and specifically, the equalizer architecture with high energy efficiency provided by the embodiment of the invention comprises the following components: a filtering module 1, a processing module 2 and a converting module 3.
The filtering module 1 is used for filtering an input signal.
In this embodiment, the filtering module 1 belongs to an adding part, and may be added or omitted in an actual circuit according to requirements, specifically, the filtering module 1 includes a low-pass filter, a high-pass filter, a band-pass filter or an all-pass filter, and for different filters, the signal strength of each frequency is different, so that the signal in a certain frequency range is allowed to pass, and the signals in other frequency ranges are prevented or weakened.
The processing module 2 is connected with the filtering module 1, the processing module 2 comprises a plurality of complementary MOS tubes, and the processing module 2 is used for transconductance amplifying the current signal of the input signal.
In this embodiment, the processing module 2 includes a plurality of NMOS transistors and/or PMOS transistors that are complementarily connected, gmp and gmn represent transconductances generated by PMOS pairs and NMOS pairs of the transconductance stage with source degeneration network, respectively, and the TIA is responsible for converting the current signal into the voltage signal. The input of the PMOS pair and the NMOS pair can be added with a filter for extracting signals in different frequency bands, a source degradation network is adjusted, and the addition and subtraction relation between gmp and gmn is adjusted, so that a rich equalization effect can be obtained.
Fig. 5 is a circuit diagram in this embodiment, the processing module 2 includes an input terminal vin+, an input terminal Vin-, a voltage terminal VDD, a capacitor Cs7, a resistor Rs7, a MOS transistor M73, a MOS transistor M74, a MOS transistor M75, a MOS transistor M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS transistor M75, and a MOS transistor M76, a first terminal of the capacitor Cs7 is connected to the voltage terminal VDD, a second terminal of the capacitor Cs7 is connected to a second terminal of the resistor Rs7, a gate of the MOS transistor M73 is connected to the input terminal vin+, a drain of the MOS transistor M73 is connected to a first terminal of the resistor Rs7, a source of the MOS transistor M73 is connected to the switching module 3, a gate of the MOS transistor M74 is connected to the second terminal of the resistor R13, a source of the MOS transistor M74 is connected to the switching module 3, a drain of the MOS transistor M75 is connected to the second terminal of the MOS transistor M8 is connected to the second terminal of the resistor Rs8, a drain of the MOS transistor M73 is connected to the second terminal of the MOS transistor M8, a drain of the MOS transistor M75 is connected to the second terminal of the resistor Rs7, a drain of the MOS transistor M74 is connected to the second terminal of the resistor Rs 7.
In the present embodiment, compared with the first and second embodiments, the circuit structure provided in the present embodiment has a larger adjustment range of high-frequency compensation capability.
The conversion module 3 is connected with the processing module 2, and the conversion module 3 is used for converting the current signal into a voltage signal.
In this embodiment, the processing module 2 comprises a TIA amplifier for converting a current signal into a voltage signal. In this embodiment, the TIA amplifier is a transimpedance amplifier, and is composed of a single-stage inverting amplifier circuit and a feedback network, and may be composed of other structures in other alternative embodiments, which are not particularly limited in this embodiment. TIA amplifiers are commonly used in high-speed circuits, such as optical-to-electrical communication systems, due to their high bandwidth.
The conversion module 3 comprises a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output terminal vout+ and an output terminal Vout-, wherein a first end of the resistor R14 is connected to the TIA amplifier, a second end of the resistor R14 is connected to the first end of the inductor L11, a second end of the inductor L11 is connected to the output terminal vout+, a first end of the resistor R15 is connected to the TIA amplifier, a second end of the resistor R15 is connected to the first end of the inductor L12, and a second end of the inductor L12 is connected to the output terminal Vout-.
The embodiment of the invention discloses an energy-efficient equalizer architecture, which comprises the following components: the filtering module is used for filtering the input signal; the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal; the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal. The equalizer architecture with high energy efficiency provided by the embodiment of the invention can obtain double transconductance by accessing the complementary type transconductor and using the same transconductance amplifying stage current, and meanwhile, the output transimpedance stage can still maintain constant bandwidth and gain, so that the effects of strong compensation capability and strong driving capability are achieved compared with the traditional linear equalizer architecture.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (9)

1. An energy efficient equalizer architecture, comprising:
the filtering module is used for filtering the input signal;
the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal;
the MOS tubes are connected in a complementary manner, wherein the MOS tubes are connected in a complementary manner and comprise NMOS tubes and/or PMOS tubes which are connected in a complementary manner, and the addition and subtraction relation between gmn and gmp can be adjusted;
the gmn is transconductance provided by an NMOS tube and a source electrode degradation network in the transconductance amplification stage;
the gmp is transconductance provided by a PMOS tube and a source electrode degradation network in the transconductance amplification stage;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal;
the processing module comprises an input end Vin+, an input end Vin-, a voltage end VDD, a capacitor Cs4, a resistor Rs4, a MOS tube M53, a MOS tube M54, a MOS tube M51, a MOS tube M52, a resistor Rs5 and a capacitor Cs5, wherein a first end of the capacitor Cs4 is connected to the voltage end VDD, a second end of the capacitor Cs4 is connected to a second end of the resistor Rs4, a gate of the MOS tube M53 is connected to the input end Vin+, a source of the MOS tube M53 is connected to a first end of the resistor Rs4, a drain of the MOS tube M53 is connected to the conversion module, a source of the MOS tube M54 is connected to a second end of the resistor Rs4, a gate of the MOS tube M54 is connected to the input end Vin-, a drain of the MOS tube M54 is connected to the conversion module, a gate of the MOS tube M51 is connected to the second end of the MOS tube, a drain of the MOS tube M5 is connected to the second end of the MOS tube Rs5, a drain of the MOS tube M5 is connected to the second end of the MOS tube 52, and a drain of the MOS tube M5 is connected to the second end of the resistor Rs 5.
2. The energy efficient equalizer architecture of claim 1, wherein the conversion module comprises a resistor R8, an inductor L7, a TIA amplifier, a resistor R9, an inductor L8, an output vout+ and an output Vout-, a first end of the resistor R8 being connected to the TIA amplifier, a second end of the resistor R8 being connected to the first end of the inductor L7, a second end of the inductor L7 being connected to the output vout+, a first end of the resistor R9 being connected to the TIA amplifier, a second end of the resistor R9 being connected to the first end of the inductor L8, a second end of the inductor L8 being connected to the output Vout-.
3. An energy efficient equalizer architecture, comprising:
the filtering module is used for filtering the input signal;
the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal;
the MOS tubes are connected in a complementary manner, wherein the MOS tubes are connected in a complementary manner and comprise NMOS tubes and/or PMOS tubes which are connected in a complementary manner, and the addition and subtraction relation between gmn and gmp can be adjusted;
the gmn is transconductance provided by an NMOS tube and a source electrode degradation network in the transconductance amplification stage;
the gmp is transconductance provided by a PMOS tube and a source electrode degradation network in the transconductance amplification stage;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal;
the processing module comprises an input end Vin+, an input end Vin-, a voltage end VDD, a resistor R10, a MOS tube M63, a MOS tube M64, a MOS tube M61, a MOS tube M62, a resistor Rs6 and a capacitor Cs6, wherein a first end of the resistor R10 is connected to the voltage end VDD, a second end of the resistor R10 is connected to the voltage end VDD, a gate of the MOS tube M63 is connected to the input end Vin-, a source of the MOS tube M63 is connected to the first end of the resistor R10, a drain of the MOS tube M63 is connected to the conversion module, a source of the MOS tube M64 is connected to the second end of the resistor R10, a gate of the MOS tube M64 is connected to the input end Vin+, a drain of the MOS tube M61 is connected to the conversion module, a gate of the MOS tube M61 is connected to the first end of the MOS tube M62 is connected to the second end of the resistor R6, a drain of the MOS tube R64 is connected to the second end of the capacitor Cs6, and a drain of the MOS tube R64 is connected to the second end of the capacitor Cs 6.
4. The energy efficient equalizer architecture of claim 3, wherein the conversion module comprises a resistor R11, an inductor L9, a TIA amplifier, a resistor R12, an inductor L10, an output vout+ and an output Vout-, a first end of the resistor R11 being connected to the TIA amplifier, a second end of the resistor R11 being connected to the first end of the inductor L9, a second end of the inductor L9 being connected to the output vout+, a first end of the resistor R12 being connected to the TIA amplifier, a second end of the resistor R12 being connected to the first end of the inductor L10, a second end of the inductor L10 being connected to the output Vout-.
5. An energy efficient equalizer architecture, comprising:
the filtering module is used for filtering the input signal;
the processing module is connected with the filtering module and comprises a plurality of MOS tubes which are complementarily connected, and the processing module is used for transconductance amplifying the current signal of the input signal;
the MOS tubes are connected in a complementary manner, wherein the MOS tubes are connected in a complementary manner and comprise NMOS tubes and/or PMOS tubes which are connected in a complementary manner, and the addition and subtraction relation between gmn and gmp can be adjusted;
the gmn is transconductance provided by an NMOS tube and a source electrode degradation network in the transconductance amplification stage;
the gmp is transconductance provided by a PMOS tube and a source electrode degradation network in the transconductance amplification stage;
the conversion module is connected with the processing module and is used for converting the current signal into a voltage signal;
the processing module comprises an input end Vin+, an input end Vin-, a voltage end VDD, a capacitor Cs7, a resistor Rs7, a MOS tube M73, a MOS tube M74, a MOS tube M75, a MOS tube M76, a resistor Rs8, a capacitor Cs8, a resistor R13, a MOS tube M75 and a MOS tube M76, wherein a first end of the capacitor Cs7 is connected to the voltage end VDD, a second end of the capacitor Cs7 is connected to a second end of the resistor Rs7, a gate of the MOS tube M73 is connected to the input end Vin+, a source of the MOS tube M73 is connected to a first end of the resistor Rs7, a drain of the MOS tube M73 is connected to the conversion module, a source of the MOS tube M74 is connected to a second end of the resistor Rs7, a gate of the MOS tube M74 is connected to the input end Vin-, a drain of the MOS tube M74 is connected to the conversion module, a drain of the MOS tube M75 is connected to the first end of the MOS tube is connected to the second end of the resistor Rs7, and a drain of the MOS tube is connected to the second end of the MOS tube M75 is connected to the second end of the MOS tube 8.
6. The energy efficient equalizer architecture of claim 5, wherein the conversion module comprises a resistor R14, an inductor L11, a TIA amplifier, a resistor R15, an inductor L12, an output vout+ and an output Vout-, a first end of the resistor R14 being connected to the TIA amplifier, a second end of the resistor R14 being connected to the first end of the inductor L11, a second end of the inductor L11 being connected to the output vout+, a first end of the resistor R15 being connected to the TIA amplifier, a second end of the resistor R15 being connected to the first end of the inductor L12, a second end of the inductor L12 being connected to the output Vout-.
7. The energy efficient equalizer architecture of claim 1 or 3 or 5, wherein the filtering module comprises a low pass filter, a high pass filter, a band pass filter, or an all pass filter.
8. The energy efficient equalizer architecture of claim 1, 3 or 5, wherein the processing module comprises a plurality of complementarily-connected NMOS and/or PMOS transistors.
9. The energy efficient equalizer architecture of claim 1, 3 or 5, wherein the conversion module comprises a TIA amplifier for converting a current signal to a voltage signal.
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101534094A (en) * 2009-04-14 2009-09-16 北京中星微电子有限公司 Compensating circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5757230A (en) * 1996-05-28 1998-05-26 Analog Devices, Inc. Variable gain CMOS amplifier
US7562581B2 (en) * 2005-09-29 2009-07-21 Case Western Reserve University Wireless sensor platform for harsh environments
US20090200999A1 (en) * 2008-02-08 2009-08-13 Mediatek Inc. Voltage regulator with compensation and the method thereof
CN101488808A (en) * 2009-03-02 2009-07-22 天津大学 Trans-impedance compensation type optical receiver
CN107666287A (en) * 2017-09-14 2018-02-06 西安电子科技大学 Variable gain trans-impedance amplifier
CN111030603A (en) * 2019-11-25 2020-04-17 成都信息工程大学 Analog front end structure integrating program control gain amplification function
CN111697936B (en) * 2020-06-19 2023-08-25 东南大学 Low-power consumption complementary digital variable gain amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101534094A (en) * 2009-04-14 2009-09-16 北京中星微电子有限公司 Compensating circuit

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