CN118039566A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN118039566A CN118039566A CN202211366783.6A CN202211366783A CN118039566A CN 118039566 A CN118039566 A CN 118039566A CN 202211366783 A CN202211366783 A CN 202211366783A CN 118039566 A CN118039566 A CN 118039566A
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- layer
- sub
- region
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 208000010392 Bone Fractures Diseases 0.000 description 2
- 206010017076 Fracture Diseases 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area; forming a grid structure on the substrate, wherein the distance between adjacent grid structures in the first area is smaller than that between adjacent grid structures in the second area; forming a first insulating layer on the surface of the gate structure, and forming a first groove between the first insulating layers on the side wall of the gate structure in a first area, wherein the first groove corresponds to a source-drain area of the first area; the second insulating layer is formed and positioned on the surface of the first insulating layer on the side wall of the grid electrode structure in the second area, and the second grooves are formed between the second insulating layers in the second area and correspond to the source drain regions in the second area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
The connection plugs of the semiconductor structure in the prior art, such as the connection plugs for connecting the source and drain and the gate structure, are generally formed synchronously, but due to different formation positions of the connection plugs, the formed connection plugs have different space sizes, so that the formed connection plugs are easy to generate misalignment or fracture risk, for example, the spacing between the gate structures of the core region is smaller than the spacing between the gate structures of the peripheral region in the related art, the source and drain plugs of the core region are easy to be aligned when the source and drain plugs are formed later, and the source and drain plugs formed with smaller formation space are easy to fracture, and short circuit phenomenon is easy to occur.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a preparation method thereof, which can improve the alignment effect of a connecting plug and reduce the risks of breakage and short circuit.
The preparation method of the semiconductor structure according to the embodiment of the invention comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area; forming a grid structure on the substrate, wherein the distance between adjacent grid structures in the first area is smaller than that between adjacent grid structures in the second area; forming a first insulating layer on the surface of the gate structure, and forming a first groove between the first insulating layers of the side wall of the gate structure in the first region, wherein the first groove corresponds to a source region and a drain region of the first region; forming a second insulating layer, wherein the second insulating layer is positioned on the surface of the first insulating layer on the side wall of the gate structure of the second region, a second groove is formed between the second insulating layers in the second region, and the second groove corresponds to the source-drain region of the second region; forming a first connecting plug connected with the source-drain region of the first region in the first groove; and forming a second connecting plug connected with the source-drain region of the second region in the second groove.
According to some embodiments of the invention, the step of forming a first insulating layer on the surface of the gate structure includes: forming a first sub-insulating layer on the surface of the gate structure, wherein a first sub-groove exposing the substrate is formed between the first sub-insulating layers on the side wall of the gate structure; performing first ion implantation on the substrate along the first sub-grooves to form first doped regions in the substrate; and forming a second sub-insulating layer on the surface of the first sub-insulating layer, wherein the first sub-insulating layer and the second sub-insulating layer jointly form the first insulating layer, and the first groove is formed between the second sub-insulating layers in the first area.
According to some embodiments of the invention, in the step of forming a second insulating layer, a third sub-insulating layer is formed on a sidewall of the second sub-insulating layer located in the second region, a third sub-groove is formed between the third sub-insulating layers, and the second insulating layer includes a third sub-insulating layer; and performing second ion implantation on the substrate along the first groove and the third sub-groove to form a source drain region of the first region and a source drain region of the second region.
According to some embodiments of the invention, the step of forming the second insulating layer further comprises forming a fourth sub-insulating layer at least on a surface of the third sub-insulating layer, the fourth sub-insulating layer and the third sub-insulating layer together forming the second insulating layer.
According to some embodiments of the invention, before forming the fourth sub-insulating layer, further comprises: forming a first sacrificial layer in the first groove; in the step of forming a fourth sub-insulating layer on the surface of the third sub-insulating layer, the fourth sub-insulating layer is formed on the surfaces of the first insulating layer, the substrate, the first sacrificial layer and the third sub-insulating layer.
According to some embodiments of the invention, the first sacrificial layer is formed using atomic layer deposition.
According to some embodiments of the invention, the step of forming the first connection plug and the second connection plug comprises: forming a second sacrificial layer on the surface of the fourth sub-insulating layer, and removing the first sacrificial layer and at least part of the second sacrificial layer to expose the first groove and the second groove and expose the source drain region; and forming the first connecting plug in the first groove and forming the second connecting plug in the second groove.
According to some embodiments of the invention, the step of removing the first sacrificial layer and at least part of the second sacrificial layer comprises: forming a first mask layer on the surfaces of the fourth sub-insulating layer and the second sacrificial layer; forming a photoresist layer on the first mask layer, wherein the photoresist layer is provided with photoetching through holes corresponding to the first grooves and the second grooves; etching the first mask layer along the photoetching through hole, and etching the first sacrificial layer and the second sacrificial layer downwards to expose the first groove and the second groove and expose the source drain region; and removing the photoresist layer.
According to some embodiments of the invention, the step of forming the first connection plug in the first recess and the second connection plug in the second recess includes: forming an initial connecting layer on the surface of the first mask layer, in the first groove and in the second groove; and removing part of the initial connection layer positioned on the surface of the first mask layer, reserving part of the initial connection layer positioned in the first groove to form the first connection plug, and reserving part of the initial connection layer positioned in the second groove to form the second connection plug.
According to some embodiments of the invention, the method for manufacturing a semiconductor structure further comprises: and forming a third connecting plug, wherein the third connecting plug is connected with the gate structure.
According to some embodiments of the invention, the step of forming the third connection plug comprises: forming a second mask layer on the surfaces of the first insulating layer, the second insulating layer, the first connecting plug and the second connecting plug; patterning the second mask layer to form a through hole, wherein the through hole corresponds to part of the grid structure; etching the first insulating layer and the second insulating layer on the surface of the gate structure along the etching through hole to expose the gate structure; removing the second mask layer to expose the first connection plug and the second connection plug; and forming a third connecting plug in the etched through hole.
According to some embodiments of the invention, the first insulating layer comprises at least one of an oxide layer and the nitride layer.
The invention also provides a semiconductor structure.
The semiconductor according to the embodiment of the invention comprises: the substrate is provided with a first area and a second area, and a grid structure is arranged on the substrate; the spacing between adjacent gate structures in the first region is smaller than the spacing between adjacent gate structures in the second region;
The first insulating layer is positioned on the surface of the grid structure, a first groove is formed between the first insulating layers of the side walls of the grid structure in the first area, and the first groove corresponds to the source-drain area of the first area; the second insulating layer is formed on the side wall of the first insulating layer of the second region, a second groove is formed between the second insulating layers of the side wall of the gate structure in the second region, and the second groove corresponds to the source region and the drain region of the second region in position;
The first connecting plug is positioned in the first groove and connected with the source-drain region of the first region; and the second connecting plug is positioned in the second groove and is connected with the source-drain region of the second region.
According to some embodiments of the invention, the first insulating layer is at least partially located on the source drain region of the first region, and the second insulating layer is at least partially located on the source drain region of the second region.
According to some embodiments of the invention, the semiconductor structure further comprises a third connection plug connected to the gate structure.
According to the semiconductor structure and the preparation method thereof, the first region can be a core region and a sensing amplification region, the second region can be a peripheral region, the space between the grid structures of the first region is smaller than the space between the grid structures of the second region, the side wall of the grid structure of the first region is provided with the first insulating layer, the side wall of the grid structure of the second region is provided with the first insulating layer and the second insulating layer, the number of insulating layers between the grid structures of the first region and the number of insulating layers between the grid structures of the second region are different, the occupied space of the insulating layers can be reduced by reducing the number of insulating layers between the grid structures of the first region, the space of the first connecting plug between the grid structures of the first region is increased, the formation of the first connecting plug and the self-alignment of the source-drain region of the first region are facilitated, the first connecting plug is prevented from being too thin to break, the insulating layers between the grid structures of the second region are relatively more, and the insulating layers between the grid structures of the second region are prevented from being excessively etched to cause a short circuit phenomenon.
Drawings
Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;
Fig. 2-22 are corresponding cross-sectional views of steps of a method of fabricating a semiconductor structure according to an embodiment of the present invention;
Reference numerals:
100: semiconductor structure, A1: first region, A2: second region, S1: spacing between adjacent gate structures of the first region, S2: a spacing S2 between adjacent gate structures of the second region;
1: substrate, 11: gate structure, 12: first gate layer, 13: second gate layer, 14: third gate layer, 15: oxide layer on top of substrate, 16: nitride cap layer, 17: first doped region, 18: a source/drain region;
2: first insulating layer, 21: first sub-insulating layer, 211: first initial sub-insulating layer, 22: first oxide layer, 23: first nitride layer, 24: second sub-insulating layer, 241: second initial sub-insulating layer, 25 second oxide layer, 26: a second nitride layer;
3: second insulating layer, 31: third sub-insulating layer, 311: third initial sub-insulating layer, 32: fourth sub-insulating layer, 33: first groove, 34: second groove, 35: third sub-groove, 36: first sub-groove 41: first sacrificial layer, 42: a second sacrificial layer;
51: first mask layer, 52: photoresist layer, 53: photoetching through holes;
61: second mask layer, 62: photoresist pattern, 63: etching the through hole,
71: First connection plug, 72: second connection plug, 73: initial connection layer, 74: and a third connection plug.
Detailed Description
The following provides a further detailed description of a semiconductor structure 100 and a method for fabricating the same according to the present invention, in conjunction with the accompanying drawings and detailed description.
In the related art semiconductor structure, during the process of forming the connection plugs, for example, when source-drain plugs are formed between gate structures, the space between the gate structures is small, so that the source-drain plugs are not easily aligned with the source-drain regions, on the other hand, the formed plugs are easily broken due to the small space for forming the source-drain plugs, so that the connection effect is poor, and the connection plugs are formed by photolithography-etching-Lithography-etching (LELE), so that short circuit phenomenon is easily caused when alignment is impossible. Specifically, according to the research of the inventor, when the connection plugs are formed in the semiconductor structure of the related art, the connection plugs in different areas are formed synchronously, the spacing between the gate structures in different areas is different, for example, the spacing between the gate structures in the core area is smaller than the spacing between the gate structures in the peripheral area, the insulating layers on the gate structures in different areas are formed synchronously, the space between the gate structures in the core area for forming the connection plugs is smaller than the space between the gate structures in the peripheral area for forming the connection plugs, and when the connection plugs are formed by adopting a photolithography process (LELE) later, the space between the core area for forming the connection plugs is too small, etching is difficult, so that the formed connection plugs are difficult to align easily, the space for forming the connection plugs is reduced, and the formed connection plugs are easy to break and short circuit risk is also caused.
The method for manufacturing the semiconductor structure 100 according to the embodiment of the present invention is described below with reference to the accompanying drawings, and the method for manufacturing the semiconductor structure 100 according to the embodiment of the present invention forms the connection plug using a self-aligned process, so that the problems of misalignment of the connection plug and occurrence of breakage and short circuit can be avoided.
As shown in fig. 1, a method for fabricating a semiconductor structure 100 according to an embodiment of the present invention may include: s1: providing a substrate 1, wherein the substrate 1 is provided with a first area A1 and a second area A2; s2: forming a gate structure 11 on the substrate 1, wherein the distance between adjacent gate structures 11 in the first area A1 is smaller than the distance between adjacent gate structures 11 in the second area A2; s3: forming a first insulating layer 2 on the surface of the gate structure 11, and forming a first groove 33 between the first insulating layers 2 on the side wall of the gate structure 11 in the first region A1, wherein the first groove 33 corresponds to the source drain region 18 of the first region A1; s4: forming a second insulating layer 3, wherein the second insulating layer 3 is positioned on the surface of the first insulating layer 2 on the side wall of the gate structure 11 of the second region A2, a second groove 34 is formed between the second insulating layers 3 in the second region A2, and the second groove 34 corresponds to the source drain region 18 of the second region A2; s5: forming a first connection plug 71 connected to the source drain region 18 of the first region A1 in the first recess 33; s6: a second connection plug 72 is formed in the second recess 34 to connect to the source drain region 18 of the second region A2.
Fig. 2-22 are cross-sectional views of the semiconductor structure 100 corresponding to steps of a method for fabricating the semiconductor structure 100 according to an embodiment of the present invention, and a method for fabricating the semiconductor structure 100 according to an embodiment of the present invention is described below with reference to fig. 2-21.
As shown in fig. 2, step S1: a substrate 1 is provided, the substrate 1 having a first area A1 and a second area A2, wherein the first area A1 may be a core area and the second area A2 may be a peripheral area. The base 1 may include a substrate having active regions, and the base 1 further includes isolation regions formed between the active regions, and the substrate may be, but is not limited to, a silicon substrate, and this embodiment is described by taking the substrate as a silicon substrate. In other embodiments, the substrate may also be a semiconductor substrate of gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI, etc., for supporting device structures thereon.
As shown in fig. 2, step S2: the gate structures 11 are formed on the substrate 1, and the spacing between adjacent gate structures 11 in the first region A1 is smaller than the spacing between adjacent gate structures 11 in the second region A2.
Specifically, the step of forming the gate structure 11 may include: a stacked structure may be formed on the surface of the substrate 1, and the stacked structure may be etched to form a plurality of gate structures 11, wherein the gate structures 11 are formed on the surfaces of the first region A1 and the second region A2, and a space S1 between adjacent gate structures 11 of the first region A1 is smaller than a space S2 between adjacent gate structures 11 of the second region A2. As shown in fig. 2, the substrate 1 may further include an oxide layer 15 formed on the surface of the substrate and the isolation region, and in the step of forming the gate structure 11, the stacked structure may be etched until the surface of the oxide layer 15 stops to form the gate structure 11. In the example shown in fig. 2, the gate structure 11 may include a first gate layer 12, a second gate layer 13, and a third gate layer 14, and a silicon nitride cap layer 16 on the third gate layer 14, where the first gate layer 12 may be a polysilicon layer, the second gate layer 13 may be a metal layer, and the third gate layer 14 may be a metal silicide layer.
Referring to fig. 3 to 7, step S3: a first insulating layer 2 is formed on the surface of the gate structure 11, and a first groove 33 is formed between the first insulating layers 2 on the side wall of the gate structure 11 in the first region A1, where the first groove 33 corresponds to the source drain region 18 of the first region A1. Wherein the first insulating layer 2 is formed on the surface of the gate structure 11 in both the first region A1 and the second region A2, the first insulating layer 2 may include a stacked structure of alternately stacked nitride layers and oxide layers, and the source drain region 18 is formed in the substrate 1 and corresponds to the first recess 33.
As shown in fig. 3 to 7, the step of forming the first insulating layer 2 on the surface of the gate structure 11 may include:
forming a first sub-insulating layer 21 on the surface of the gate structure 11, wherein a first sub-groove 36 exposing the substrate 1 is formed between the first sub-insulating layers 21 on the side wall of the gate structure 11;
performing a first ion implantation on the substrate 1 along the first sub-recess 36 to form a first doped region 17 in the substrate 1;
A second sub-insulating layer 24 is formed on the surface of the first sub-insulating layer 21, the first sub-insulating layer 21 and the second sub-insulating layer 24 together form the first insulating layer 2, and the first groove 33 is formed between the second sub-insulating layers 24 in the first region A1.
Specifically, as shown in fig. 3, a first initial sub-insulating layer 211 may be formed on the surface of the substrate 1 and the surface of the gate structure 11, as shown in fig. 4, the first initial sub-insulating layer 211 may be etched, a portion of the first initial sub-insulating layer 211 located on the surface of the gate structure 11 may be left to form a first sub-insulating layer 21, in the example shown in fig. 4, the first sub-insulating layer 21 may include a first oxide layer 22 and a first nitride layer 23, the first oxide layer 22 may be formed on a sidewall of the first gate layer 12, the first nitride layer 23 may be formed on a sidewall and an upper surface of the gate structure 11 and cover the first oxide layer 22, alternatively, a thickness of the first oxide layer 22 may be 0-2nm, and a thickness of the first nitride layer 23 may be 0-5nm.
As shown in fig. 4, a first sub-recess 36 may be formed between the first sub-insulating layers 21 of the sidewalls of the gate structure 11 in the first region A1, the first sub-recess 36 exposing the substrate 1, specifically, the first sub-recess 36 exposing a portion of the active region surface of the substrate 1, and then the substrate 1 may be ion-implanted along the first sub-recess 36 to form a doped region 17 in the substrate 1, for example, the substrate 1 may be lightly doped along the first sub-recess 36 to form a lightly doped source drain (light dopant drain LDD) structure.
As shown in fig. 5, at least one of a chemical vapor deposition method, a physical vapor deposition method, and the like may be used to form a second initial sub-insulating layer 241 on the surface of the substrate 1 and the first sub-insulating layer 21, and, as shown in fig. 6 to 7, the second initial sub-insulating layer 241 may be etched, so as to leave a portion of the second initial sub-insulating layer located on the surface of the first sub-insulating layer 21 to form a second sub-insulating layer 24, so that the second sub-insulating layer 24 and the first sub-insulating layer 21 are formed on the surface of the gate structure 11 of the first area A1 and the second area A2, and the first sub-insulating layer 21 and the second sub-insulating layer 24 together form the first insulating layer 2, that is, the sidewalls of the gate structure 11 of the first area A1 and the second area A2 are both formed with the first insulating layer 2, wherein a first groove 33 may be formed between the second sub-insulating layer 24 located in the first area A1, and the first groove 33 is located correspondingly on the first doped area 17.
As shown in fig. 7, the second sub-insulating layer 24 may include a second oxide layer 25 and a second nitride layer 26, the second oxide layer 25 being formed on the surfaces of the first sub-insulating layer 21 and the substrate 1, and the second nitride layer 26 being formed on the surface of the second oxide layer 25, wherein the thickness of the second oxide layer 25 may be 0-2nm, and the thickness of the second nitride layer 26 may be 0-15nm.
Referring to fig. 6 to 10, step S4: a second insulating layer 3 is formed, the second insulating layer 3 is located on the surface of the first insulating layer 2 on the side wall of the gate structure 11 in the second area A2, a second groove 34 is formed between the second insulating layers 3 in the second area A2, and the second groove 34 corresponds to the source drain region 18 in the second area A2.
Thus, the first insulating layer 2 is formed on the side wall of the gate structure 11 in the first area A1, the first insulating layer 2 and the second insulating layer 3 are formed on the side wall of the gate structure 11 in the second area A2, so that the number of layers of the insulating layers formed on the side wall of the gate structure 11 in the first area A1 is different from that of the insulating layers formed on the side wall of the gate structure 11 in the second area A2, the number of layers of the insulating layers on the side wall of the gate structure 11 in the first area A1 is smaller than that of the insulating layers on the side wall of the gate structure 11 in the second area A2, and the thickness of the insulating layers on the side wall of the gate structure 11 in the second area A2 is larger than that of the insulating layers on the side wall of the gate structure 11 in the first area A1, thereby reducing the occupied space of the insulating layers on the side wall of the gate structure 11 in the first area A1, and facilitating the subsequent formation of the connection plug between the gate structures 11.
In some embodiments of the present invention, the second insulating layer 3 may include a third sub-insulating layer 31, and the step of forming the second insulating layer 3 may include:
Forming a third sub-insulating layer 31 on the side wall of the second sub-insulating layer 24 located in the second area A2, forming a third sub-groove 35 between the third sub-insulating layers 31, wherein the second insulating layer 3 includes the third sub-insulating layer 31;
Ion implantation is performed on the doped region 17 and the substrate 1 along the first recess 33 and the third sub-recess 35 to form a source drain region 18 of the first region A1 and a source drain region 18 of the second region A2.
Specifically, as shown in fig. 6, after the second initial sub-insulating layer 241 is formed, a third initial sub-insulating layer 311 may be formed on the surface of the second initial sub-insulating layer 241, and the third initial sub-insulating layer 311 may be an oxide layer, and the thickness of the third sub-insulating layer 31 may be 0 to 10nm.
As shown in fig. 7, in the step of etching the second preliminary sub-insulating layer 241, the third preliminary sub-insulating layer 311 may be simultaneously etched, and in particular, the third preliminary sub-insulating layer 311 located on the upper surface of the second preliminary sub-insulating layer 241 may be removed, a portion of the third preliminary sub-insulating layer 311 located at the sidewall of the second sub-insulating layer 24 may remain to form the third sub-insulating layer 31, and the second preliminary sub-insulating layer may be etched along the sidewall of the third sub-insulating layer 31 to form the second sub-insulating layer 24, while a third sub-recess 35 may be formed between the third sub-insulating layers 31, the third sub-recess 35 corresponding to the doped region 17 located at the second region A2.
As shown in fig. 6, in the step of forming the third preliminary sub-insulation layer 311, since the space between the second sub-insulation layers 24 is small, for example, the space between the sidewalls of the second preliminary sub-insulation layers 241 is generally less than 67nm, in the first region A1, such that an air gap may be formed between the sidewalls of the second preliminary sub-insulation layers 241 of the first region A1 when the third preliminary sub-insulation layer 311 is deposited, the third preliminary sub-insulation layer 311 is formed on the upper surface of the second preliminary sub-insulation layer 241, and the third preliminary sub-insulation layer 311 is not formed on the sidewalls of the second preliminary sub-insulation layer 241 of the first region A1, i.e., the third preliminary sub-insulation layer 311 is not formed between the gate structures 11 of the first region A1.
As shown in fig. 7, after etching the second and third preliminary sub-insulating layers 241 and 311, the first insulating layer 2 is formed between the gate structures 11 of the first region A1, the first and third sub-insulating layers 2 and 31 are formed between the gate structures 11 of the second region A2, wherein the first groove 33 is formed between the first insulating layers 2 of the first region A1, and the third sub-groove 35 is formed between the third sub-insulating layers 31 of the second region A2.
As shown in fig. 8, the substrate 1 may be subjected to a second ion implantation along the first recess 33 and the third sub-recess 35 to form the source drain region 18 of the first region A1 and the source drain region 18 of the second region A2, such that the source drain region 18 between the gate structures 11 of the first region A1 corresponds to the first recess 33 and the source drain region 18 between the gate structures 11 of the second region A2 corresponds to the third sub-recess 35, wherein the first ion implantation and the second ion implantation may be of the same type, for example, the first ion implantation and the second ion implantation may each be an N-type ion implantation, and the second ion implantation may have a concentration and a depth greater than those of the first ion implantation.
In some embodiments of the present invention, the second insulating layer 3 may further include a fourth sub-insulating layer 32, the step of forming the second insulating layer 3 may further include forming the fourth sub-insulating layer 32 at least on the surface of the third sub-insulating layer 31, the fourth sub-insulating layer 32 and the third sub-insulating layer 31 together form the second insulating layer 3, the fourth sub-insulating layer 32 is formed in the third sub-groove 35, the second groove 34 is formed between the fourth sub-insulating layers 32, thereby the sidewall of the gate structure 11 of the first area A1 has the first insulating layer 2, the sidewall of the gate structure 11 of the second area A2 has the first insulating layer 2 and the second insulating layer 3, the sidewall of the gate structure 11 of the first area A1 has the insulating layer less than the insulating layer between the gate structures 11 of the second area A2, by controlling the insulating layers between the gate structures 11 of different areas, thereby reducing the space occupied by the insulating layers between the gate structures 11 of the first area A1, the number of the gate structures 11 may be increased for forming the first area A1, the space between the gate structures 11 may be prevented from being easily broken, and the formation of the plug structures may be prevented from being easily formed, and the occurrence of the short circuit connection between the first area A1 and the gate structures may be prevented from being easily formed. And meanwhile, the phenomenon of short circuit caused by the fact that the insulating layer on the side wall of the gate structure 11 with large spacing is cut through in a thinner way can be prevented.
Referring to fig. 9 to 16, step S5: forming a first connection plug 71 connected to the source drain region 18 of the first region A1 in the first recess 33; step S6: a second connection plug 72 is formed in the second recess 34 to connect to the source drain region 18 of the second region A2.
In some embodiments, the method of forming the first connection plug 71 and the second connection plug 72 may include the steps of:
forming a first sacrificial layer 41 in the first recess 33 before forming the fourth sub-insulating layer 32; in the step of forming the fourth sub-insulating layer 32 on the surface of the third sub-insulating layer 31, the fourth sub-insulating layer 32 is formed on the surfaces of the first insulating layer 2, the substrate 1, the first sacrificial layer 41, and the third sub-insulating layer 31.
Specifically, as shown in fig. 9, after the source and drain regions 18 are formed by performing the second ion implantation, the first sacrificial layer 41 may be formed in the first recess 33, the source and drain regions 18 of the first region A1 are formed by performing the second ion implantation along the first recess 33, the first sacrificial layer 41 fills the first recess 33 to align with the source and drain regions 18 of the first region A1, and the first connection plug 71 is enabled to be self-aligned with the source and drain regions 18 of the first region A1 when the first connection plug 71 is formed by removing the first sacrificial layer 41 in a subsequent step. Alternatively, in this step, the first sacrificial layer 41 may be formed using an atomic layer deposition method, so that the deposition effect can be improved using the atomic layer deposition method because the space of the first recess 33 is small, so that the first sacrificial layer 41 can fill the first recess 33.
As shown in fig. 10, a fourth sub-insulating layer 32 is formed by depositing on the surface of the substrate 1, the surface of the first insulating layer 2, the surface of the first sacrificial layer 41 and the surface of the third sub-insulating layer 31, wherein the fourth sub-insulating layer 32 is formed on the upper surface of the gate structure 11 in the first region A1 and is not formed on the sidewall of the gate structure 11, the fourth sub-insulating layer 32 is formed on the sidewall of the gate structure 11 in the second region A2, the fourth sub-insulating layer 32 and the third sub-insulating layer 31 together form the second insulating layer 3, the second recess 34 is formed between the fourth sub-insulating layers 32 on the sidewall of the gate structure 11,
As shown in fig. 11-16, after forming the fourth sub-insulating layer 32, the method for manufacturing the semiconductor structure 100 further includes:
a second sacrificial layer 42 is formed on the surface of the fourth sub-insulating layer 32,
In the step of forming the first connection plugs 71 and the second connection plugs 72, the first sacrificial layer 41 and the second sacrificial layer 42 are etched to expose the first grooves 33 and the second grooves 34 and to expose the source drain regions 18;
the first connection plug 71 is formed in the first recess 33, and the second connection plug 72 is formed in the second recess 34.
Specifically, as shown in fig. 11, at least one of a chemical vapor deposition method, a physical vapor deposition method, or an atomic layer deposition method may be used to form the second sacrificial layer 42 on the surface of the fourth sub-insulating layer 32, where the second sacrificial layer 42 may be flush with the second insulating layer 3 on the upper surface of the gate structure 11, the second sacrificial layer 42 fills the second recess 34 and is partially located over the source drain regions 18 of the second region A2, and in the subsequent step of forming the second connection plug 72, a portion of the second sacrificial layer 42 located between the gate structures 11 of the second region A2 may be removed for forming the second connection plug 72, so that the second connection plug 72 may be self-aligned with the source drain regions 18 of the second region A2, alternatively, the second sacrificial layer 42 may be deposited to a thickness of 0-200nm.
As shown in connection with fig. 12-14, the step of etching the first sacrificial layer 41 and the second sacrificial layer 42 to expose the first recess 33 and the second recess 34 may include: as shown in fig. 12, a first mask layer 51 is formed on the surfaces of the fourth sub-insulating layer 32 and the second sacrificial layer 42, and the first mask layer 51 covers the upper surfaces of the fourth sub-insulating layer 32 and the second sacrificial layer 42; as shown in fig. 13, a photoresist layer 52 is formed on the first mask layer 51, and the photoresist layer 52 has a photoresist through hole 53 corresponding to the first recess 33 and the second recess 34; as shown in fig. 14, the first mask layer 51 is etched along the photolithographic through hole 53 to expose the first and second sacrificial layers 41 and 42, and the first and second sacrificial layers 41 and 42 are continuously etched downward to expose the first and second grooves 33 and 34; so that the source and drain regions 18 of the first region A1 and the source and drain regions 18 of the second region A2 can be exposed, and finally the photoresist layer 52 is removed.
Specifically, in the first region A1, the first mask layer 51 and the fourth sub-insulating layer 32 may be etched through along the photolithography through hole 53 to expose the first sacrificial layer 41, in the second region A2, the fourth sub-insulating layer 32 may be etched through along the photolithography through hole 53 to expose the second sacrificial layer 42 to stop, and then the first sacrificial layer 41 and the second sacrificial layer 42 are removed, wherein in the step of removing the first sacrificial layer 41 and the second sacrificial layer 42, the first insulating layer 2 may form a stop layer for etching the first sacrificial layer 41, and the second insulating layer 3 may be formed as a stop layer for etching the second sacrificial layer 42. Alternatively, an anisotropic etching process may be used in this step, wherein the first sacrificial layer 41 and the second sacrificial layer 42 may be the same material and different from the materials of the fourth sub-insulating layer 32 and the second sub-insulating layer 24, for example, the first sacrificial layer 41 and the second sacrificial layer 42 may be silicon oxide layers, the fourth sub-insulating layer 32 and the second sub-insulating layer 24 may be silicon nitride layers, and in the step of etching the first sacrificial layer 41 and the second sacrificial layer 42, an etchant having a low etching rate for the silicon oxide layers and a high etching rate for the silicon nitride layers may be selected for the anisotropic etching.
As shown in fig. 15 to 16, a first connection plug 71 is formed in the first recess 33, a second connection plug 72 is formed in the second recess 34, the first connection plug 71 is connected to the source drain region 18 of the first region A1, and the second connection plug 72 is connected to the source drain region 18 of the second region A2.
In some embodiments of the present invention, the step of forming the first connection plug 71 and the second connection plug 72 may include: as shown in fig. 15, an initial connection layer 73 is formed on the surface of the first mask layer 51 and in the first recess 33 and the second recess 34; as shown in fig. 16, a portion of the initial connection layer 73 located on the surface of the first mask layer 51 is removed, a portion of the initial connection layer 73 located in the first recess 33 is left to form the first connection plug 71, and a portion of the initial connection layer 73 located in the second recess 34 is left to form the second connection plug 72. Alternatively, a chemical mechanical polishing process may be used to remove a portion of the initial connection layer 73 located on the surface of the first mask layer 51. Further, the materials of the first connection plug 71 and the second connection plug 72 may be a metal material or a metal silicide material.
In some embodiments of the present invention, the method for manufacturing the semiconductor structure 100 further includes: a third connection plug 74 is formed, which third connection plug 74 is connected to the gate structure 11 and is operable to pull the gate structure 11 out in order to apply a voltage to the gate structure 11.
As shown in connection with fig. 17-22, a method of forming the third connecting plug 74 may include the steps of:
as shown in fig. 17, a second mask layer 61 is formed on the surfaces of the first insulating layer 2, the second insulating layer 3, the first connection plug 71 and the second connection plug 72, the second mask layer 61 shields the first connection plug 71 and the second connection plug 72, in the example shown in fig. 17, the second mask layer 61 may cover the surfaces of the first connection plug 71, the second connection plug 72 and the first mask layer 51, the second mask layer 61 may be a silicon oxide layer, and the thickness of the second mask layer 61 may be 0-20nm.
As shown in fig. 18-20, the second mask layer 61 is patterned to form an etched through hole 63, where the etched through hole 63 corresponds to a portion of the gate structure 11 located outside the second region A2, specifically, as shown in fig. 18, a photoresist pattern 62 may be formed on a surface of the second mask layer 61, the photoresist pattern 62 has a photoresist hole corresponding to the gate structure 11 located outside the second region A2, and the gate structure 11 located outside the second region A2 may refer to the gate structure 11 located in the gate pickup region.
As shown in fig. 19 to 20, the first insulating layer 2 and the second insulating layer 3 on the surface of the gate structure 11 are etched along the etched through holes to expose the gate structure 11, and then, as shown in fig. 20, the second mask layer 61 and the photoresist pattern 62 are removed to expose the first connection plugs 71 and the second connection plugs 72; as shown in fig. 21, a third initial connection plug 75 is formed on the first connection plug 71 and the second connection plug 72 and the exposed surface of the gate structure 11, and as shown in fig. 22, a portion of the third initial connection plug 75 is removed, and a portion of the third initial connection plug 75 located in the etched through hole 63 remains to form a third connection plug 74. Wherein the deposition thickness of the third initial connecting plug 75 may be 10-25nm, for example the deposition thickness of the third initial connecting plug 75 may be 20nm.
The invention also provides the semiconductor structure 100, and the semiconductor structure 100 according to the embodiment of the invention can be formed by adopting the preparation method of the semiconductor structure 100 in the embodiment.
As shown in fig. 22, the semiconductor structure 100 according to an embodiment of the present invention may include a substrate 1, a first insulating layer 2, a second insulating layer 3, a first connection plug 71, and a second connection plug 72.
The substrate 1 is provided with a first area A1 and a second area A2, and a grid structure 11 is arranged on the substrate 1; the spacing S1 between adjacent gate structures 11 in the first region A1 is smaller than the spacing S2 between adjacent gate structures 11 in the second region A2; the first insulating layer 2 is located on the surface of the gate structure 11, and a first groove 33 is formed between the first insulating layers 2 on the side wall of the gate structure 11 in the first area A1, and the first groove 33 corresponds to the source drain region 18 in the first area A1; the second insulating layer 3 is located on the side wall of the first insulating layer 2 of the second region A2, and a second groove 34 is formed between the second insulating layers 3 on the side wall of the gate structure 11 in the second region A2, and the second groove 34 corresponds to the source drain region 18 of the second region A2 in position;
The first connection plug 71 is located in the first recess 33 and is connected to the source drain region 18 of the first region A1, and the second connection plug 72 is located in the second recess 34 and is connected to the source drain region 18 of the second region A2.
According to some embodiments of the present invention, the first insulating layer 2 is at least partially located on the source drain region 18 of the first region A1, and the second insulating layer 3 is at least partially located on the source drain region 18 of the second region A2.
According to some embodiments of the present invention, the semiconductor structure 100 further comprises a third connection plug 74, wherein the third connection plug 74 is connected to the gate structure 11 and is used for pressing the gate structure 11.
According to the semiconductor structure and the manufacturing method thereof of the embodiment of the invention, the first area A1 may be a core area, the second area A2 may be a peripheral area, the space S1 between the gate structures 11 of the first area A1 is smaller than the space S2 between the gate structures 11 of the second area A2, the first insulating layer 2 is disposed on the side wall of the gate structure 11 of the first area A1, the first insulating layer 2 and the second insulating layer 3 are disposed on the side wall of the gate structure 11 of the second area A2, the number of insulating layers between the gate structures 11 of the first area A1 and between the gate structures 11 of the second area A2 is different, the occupied space of the insulating layers can be reduced by reducing the number of insulating layers between the gate structures 11 of the first area A1, so that the space between the gate structures 11 of the first area A1 for forming the first connecting plug 71 is increased, the first connecting plug 71 and the self-alignment with the source region 18 of the first area A1 can be prevented from being broken due to the first connecting plug 71 being excessively thin, and the number of insulating layers between the gate structures 11 of the second area A2 can be prevented from being excessively large, and the insulating layer between the gate structures 11 of the second area A2 can be prevented from being excessively short-circuited.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate, wherein the substrate is provided with a first area and a second area;
Forming a grid structure on the substrate, wherein the distance between adjacent grid structures in the first area is smaller than that between adjacent grid structures in the second area;
Forming a first insulating layer on the surface of the gate structure, and forming a first groove between the first insulating layers of the side wall of the gate structure in the first region, wherein the first groove corresponds to a source region and a drain region of the first region;
Forming a second insulating layer, wherein the second insulating layer is positioned on the surface of the first insulating layer on the side wall of the gate structure of the second region, a second groove is formed between the second insulating layers in the second region, and the second groove corresponds to the source-drain region of the second region;
Forming a first connecting plug connected with the source-drain region of the first region in the first groove;
and forming a second connecting plug connected with the source-drain region of the second region in the second groove.
2. The method of fabricating a semiconductor structure of claim 1, wherein the step of forming a first insulating layer on the surface of the gate structure comprises:
Forming a first sub-insulating layer on the surface of the gate structure, wherein a first sub-groove exposing the substrate is formed between the first sub-insulating layers on the side wall of the gate structure;
Performing first ion implantation on the substrate along the first sub-grooves to form first doped regions in the substrate;
and forming a second sub-insulating layer on the surface of the first sub-insulating layer, wherein the first sub-insulating layer and the second sub-insulating layer jointly form the first insulating layer, and the first groove is formed between the second sub-insulating layers in the first area.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein in the step of forming a second insulating layer, a third sub-insulating layer is formed on a sidewall of the second sub-insulating layer located in the second region, a third sub-groove is formed between the third sub-insulating layers, and the second insulating layer includes a third sub-insulating layer;
And performing second ion implantation on the substrate along the first groove and the third sub-groove to form a source drain region of the first region and a source drain region of the second region.
4. The method of manufacturing a semiconductor structure according to claim 3, wherein the step of forming the second insulating layer further comprises forming a fourth sub-insulating layer at least on a surface of the third sub-insulating layer, the fourth sub-insulating layer and the third sub-insulating layer together forming the second insulating layer.
5. The method of fabricating a semiconductor structure of claim 4, further comprising, prior to forming the fourth sub-insulating layer:
forming a first sacrificial layer in the first groove;
In the step of forming a fourth sub-insulating layer on the surface of the third sub-insulating layer, the fourth sub-insulating layer is formed on the surfaces of the first insulating layer, the substrate, the first sacrificial layer and the third sub-insulating layer.
6. The method of claim 5, wherein the first sacrificial layer is formed by atomic layer deposition.
7. The method of manufacturing a semiconductor structure according to claim 5, wherein the step of forming the first connection plug and the second connection plug includes:
forming a second sacrificial layer on the surface of the fourth sub-insulating layer,
Removing the first sacrificial layer and at least part of the second sacrificial layer to expose the first groove and the second groove and expose the source drain region;
And forming the first connecting plug in the first groove and forming the second connecting plug in the second groove.
8. The method of fabricating a semiconductor structure of claim 7, wherein removing the first sacrificial layer and at least a portion of the second sacrificial layer comprises:
Forming a first mask layer on the surfaces of the fourth sub-insulating layer and the second sacrificial layer;
Forming a photoresist layer on the first mask layer, wherein the photoresist layer is provided with photoetching through holes corresponding to the first grooves and the second grooves;
Etching the first mask layer along the photoetching through hole, and etching the first sacrificial layer and the second sacrificial layer downwards to expose the first groove and the second groove and expose the source drain region;
and removing the photoresist layer.
9. The method of manufacturing a semiconductor structure according to claim 8, wherein forming the first connection plug in the first recess and forming the second connection plug in the second recess comprises:
Forming an initial connecting layer on the surface of the first mask layer, in the first groove and in the second groove; and removing part of the initial connection layer positioned on the surface of the first mask layer, reserving part of the initial connection layer positioned in the first groove to form the first connection plug, and reserving part of the initial connection layer positioned in the second groove to form the second connection plug.
10. The method of fabricating a semiconductor structure of claim 1, further comprising:
and forming a third connecting plug, wherein the third connecting plug is connected with the gate structure.
11. The method of fabricating a semiconductor structure of claim 10, wherein the step of forming the third connection plug comprises:
Forming a second mask layer on the surfaces of the first insulating layer, the second insulating layer, the first connecting plug and the second connecting plug;
Patterning the second mask layer to form a through hole, wherein the through hole corresponds to part of the grid structure; etching the first insulating layer and the second insulating layer which are positioned on the surface of the gate structure downwards along the through hole so as to expose the gate structure;
Removing the second mask layer to expose the first connection plug and the second connection plug;
And forming a third connecting plug in the through hole.
12. The method of manufacturing a semiconductor structure of claim 10, wherein the first insulating layer comprises at least one of an oxide layer and a nitride layer.
13. A semiconductor structure, comprising:
The substrate is provided with a first area and a second area, and a grid structure is arranged on the substrate; the spacing between adjacent gate structures in the first region is smaller than the spacing between adjacent gate structures in the second region;
The first insulating layer is positioned on the surface of the grid structure, a first groove is formed between the first insulating layers of the side walls of the grid structure in the first area, and the first groove corresponds to the source-drain area of the first area;
The second insulating layer is formed on the side wall of the first insulating layer of the second region, a second groove is formed between the second insulating layers of the side wall of the gate structure in the second region, and the second groove corresponds to the source region and the drain region of the second region in position;
the first connecting plug is positioned in the first groove and connected with the source-drain region of the first region;
And the second connecting plug is positioned in the second groove and is connected with the source-drain region of the second region.
14. The semiconductor structure of claim 13, wherein the first insulating layer is at least partially on the source drain region of the first region and the second insulating layer is at least partially on the source drain region of the second region.
15. The semiconductor structure of claim 13, further comprising a third connection plug, the third connection plug being connected to the gate structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211366783.6A CN118039566A (en) | 2022-11-01 | 2022-11-01 | Semiconductor structure and preparation method thereof |
| PCT/CN2022/134056 WO2024092903A1 (en) | 2022-11-01 | 2022-11-24 | Semiconductor structure and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211366783.6A CN118039566A (en) | 2022-11-01 | 2022-11-01 | Semiconductor structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118039566A true CN118039566A (en) | 2024-05-14 |
Family
ID=90929546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211366783.6A Pending CN118039566A (en) | 2022-11-01 | 2022-11-01 | Semiconductor structure and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN118039566A (en) |
| WO (1) | WO2024092903A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI364094B (en) * | 2008-02-18 | 2012-05-11 | Inotera Memories Inc | Fabrication method of memory device |
| US20120309155A1 (en) * | 2011-06-03 | 2012-12-06 | Nanya Technology Corporation | Semiconductor process |
| CN104979292A (en) * | 2015-05-15 | 2015-10-14 | 上海华力微电子有限公司 | Method for forming different sidewall structures |
| CN110190058A (en) * | 2019-05-27 | 2019-08-30 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
| CN114220816A (en) * | 2021-12-13 | 2022-03-22 | 华虹半导体(无锡)有限公司 | Method for forming semiconductor structure |
-
2022
- 2022-11-01 CN CN202211366783.6A patent/CN118039566A/en active Pending
- 2022-11-24 WO PCT/CN2022/134056 patent/WO2024092903A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024092903A1 (en) | 2024-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20040009864A (en) | Semiconductor Device With Self-Aligned Junction Contact Hole And Method Of Fabricating The Same | |
| US8268688B2 (en) | Production of VDMOS-transistors having optimized gate contact | |
| JP4580657B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6380088B1 (en) | Method to form a recessed source drain on a trench side wall with a replacement gate technique | |
| JP4810089B2 (en) | Manufacturing method of semiconductor device | |
| CN110875191A (en) | Method for manufacturing fin type transistor | |
| CN118039566A (en) | Semiconductor structure and preparation method thereof | |
| CN111435680B (en) | Stepped element and method for manufacturing the same | |
| KR101119739B1 (en) | Method for Forming Transistor of Semiconductor Device | |
| KR100345067B1 (en) | Manufacturing method of semiconductor device | |
| KR100271661B1 (en) | Method for fabricating semiconductor device | |
| KR20000045437A (en) | Method for forming self aligned contact of semiconductor device | |
| KR100358046B1 (en) | Method of manufacturing a flash memory device | |
| KR0126641B1 (en) | Manufacturing method of semiconductor device | |
| KR100323725B1 (en) | Semiconductor device and method for fabricating the same | |
| KR20020058512A (en) | Method for fabricating semiconductor device | |
| KR100370132B1 (en) | Method for fabricating semiconductor device | |
| CN115223874A (en) | Semiconductor structure and preparation method thereof | |
| KR100266028B1 (en) | Semiconductor device and method for fabricating the same | |
| CN112289861A (en) | Semiconductor structure and manufacturing method thereof | |
| KR20100030019A (en) | Method for manufacturing semiconductor device | |
| KR20080001926A (en) | Method for fabricating recess gate in semiconductor device | |
| JPH09181177A (en) | Manufacture of semiconductor device | |
| KR20080008535A (en) | Fabricating method of semiconductor device | |
| KR20040079066A (en) | Method for forming contact hole in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |