CN117971721B

CN117971721B - Module verification method and device of multi-core processor and electronic equipment

Info

Publication number: CN117971721B
Application number: CN202410365423.7A
Authority: CN
Inventors: 郇丹丹; 李祖松; 邱剑
Original assignee: Beijing Micro Core Technology Co ltd
Current assignee: Beijing Micro Core Technology Co ltd
Filing date: 2024-03-28
Publication date: 2024-06-28
Anticipated expiration: 2044-03-28

Abstract

The application provides a module verification method and device of a multi-core processor and electronic equipment, wherein the module verification method of the multi-core processor comprises the following steps: acquiring a random constraint address pool, and generating test excitation according to the random constraint address pool; inputting the test excitation into the tested module to obtain a first result of any cache control module in the tested module and a second result of the whole cache control module in the tested module; obtaining a local score board and a global score board, and inputting test excitation into the local score board and the global score board respectively to obtain a third result and a fourth result; and according to the third result and the fourth result, the first result and the second result are respectively verified, and the verification result of the tested module is determined, so that the technical problems of quick expansion and complicated simulation of the module verification space in the prior art are solved, and the module-level verification of the high-efficiency and high-coverage-rate multi-core processor cache control module is realized.

Description

Module verification method and device of multi-core processor and electronic equipment

Technical Field

The present application relates to the field of processor technologies, and in particular, to a method and an apparatus for verifying a module of a multi-core processor, and an electronic device.

Background

The rapid development of semiconductor technology makes the speed and the integration level of microprocessors higher and higher, the high-performance processor design is developed towards the on-chip multi-core processor, the number and the variety of the on-chip integrated processor cores are increased, the multi-core processor design scale and the complexity are also increased rapidly, and the function verification work is complicated and becomes an important challenge for the processor design.

In the existing high-performance multi-core processor, the cache control module is an independent unit module relative to other modules of the processor, and is very suitable for module-level verification; when the multi-core processor cache control module adopts simulation verification, the problem of state space expansion needs to be overcome, so that the function verification is fast converged, and the module-level verification of the high-efficiency and high-coverage multi-core processor cache control module is achieved in a limited time.

Disclosure of Invention

The present application aims to solve at least one of the technical problems in the related art to some extent.

Therefore, a first object of the present application is to provide a module verification method for a multi-core processor, so as to realize efficient and high coverage rate module level verification of a cache control module of the multi-core processor.

A second object of the present application is to provide a module verification apparatus for a multi-core processor.

A third object of the present application is to propose an electronic device.

A fourth object of the present application is to propose a computer readable storage medium.

A fifth object of the application is to propose a computer programme product.

To achieve the above object, an embodiment of a first aspect of the present application provides a module verification method of a multi-core processor, including:

acquiring a random constraint address pool, and generating test excitation according to the random constraint address pool;

inputting the test excitation into a tested module to obtain a first result of any cache control module in the tested module and a second result of the whole cache control module in the tested module;

Acquiring a local score board corresponding to any cache control module and a global score board corresponding to all cache control modules, and respectively inputting the test stimulus into the local score board and the global score board to obtain a third result and a fourth result;

And respectively verifying the first result and the second result according to the third result and the fourth result, and determining a verification result of the tested module.

To achieve the above object, an embodiment of a second aspect of the present application provides a module verification apparatus for a multi-core processor, including:

the excitation generation module is used for acquiring a random constraint address pool and generating test excitation according to the random constraint address pool;

The first acquisition module is used for inputting the test excitation into a tested module to obtain a first result of any cache control module in the tested module and a second result of the whole cache control module in the tested module;

the second acquisition module is used for acquiring a local score board corresponding to any cache control module and a global score board corresponding to all cache control modules, and inputting the test stimulus into the local score board and the global score board respectively to obtain a third result and a fourth result;

And the verification module is used for verifying the first result and the second result respectively according to the third result and the fourth result and determining the verification result of the tested module.

To achieve the above object, an embodiment of a third aspect of the present application provides an electronic device, including: a processor, and a memory communicatively coupled to the processor;

The memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the method as described in the embodiments of the first aspect.

To achieve the above object, an embodiment of a fourth aspect of the present application proposes a computer readable storage medium having stored therein computer executable instructions for implementing the method according to the embodiment of the first aspect when being executed by a processor.

To achieve the above object, an embodiment of a fifth aspect of the present application proposes a computer program product comprising a computer program which, when executed by a processor, implements a method according to the embodiment of the first aspect.

According to the module verification method, the device and the electronic equipment of the multi-core processor, the first result and the second result of the tested module are determined through input test excitation, the third result and the fourth result are determined based on the local score board and the global score board, and the verification result of the tested module is obtained according to the comparison of the first result and the third result and the comparison of the second result and the fourth result, so that the problems of quick space expansion and complicated simulation of the existing module verification are solved, and the module-level verification of the high-efficiency and high-coverage-rate multi-core processor cache control module is realized.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flow chart of a method for verifying a module of a multi-core processor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a multi-core processor according to an embodiment of the present application;

FIG. 3 is a flowchart of a method for obtaining a first result and a second result according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating another method for verifying a module of a multi-core processor according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a module verification method of a multi-core processor according to an embodiment of the present application;

fig. 6 is a block diagram of a module verification method of a multi-core processor according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

The following describes a module verification method and device for a multi-core processor and an electronic device according to an embodiment of the application with reference to the accompanying drawings.

Fig. 1 is a flowchart of a module verification method of a multi-core processor according to an embodiment of the present application. As shown in fig. 1, the module verification method of the multi-core processor includes the following steps:

S101, acquiring a random constraint address pool, and generating test excitation according to the random constraint address pool.

It will be appreciated that test stimulus is an input signal for simulation, and is primarily intended to trigger logic flow in a simulated design and generate simulation results. The test stimulus can be randomly generated, the test stimulus is input into the tested module, and the tested module can be triggered to process and generate a corresponding result based on a processing request included in the test stimulus.

In some implementations, in order to make the test stimulus more efficient for the module under test, a constraint-based random test stimulus generation method is employed in this embodiment, considering more boundaries and coverage.

Optionally, the stimulus generating module is arranged above the second-level cache control module of the tested module so as to input test stimulus to the tested module, and thus, the request and the response sent by the tested module are processed.

Alternatively, a random address pool (also referred to as a "random constraint address pool") may be obtained, where the random address pool includes addresses of N access requests, where N is a positive integer; one or more sample addresses are selected from the random address pool and corresponding test stimulus is generated based on the sample addresses.

In this embodiment, a random constraint address pool is set, where addresses of N previous read/write requests may be stored in the random constraint address pool, that is, the random address pool is a list of N entries, where N is a positive integer. When the read-write request address is generated each time, the corresponding test excitation is generated by selecting the addresses from the random address pool according to a certain proportion, so that the test excitation comprises the read-write related addresses, and the probability of occurrence of conflict operation is improved.

S102, inputting test excitation into a tested module to obtain a first result of any cache control module in the tested module and a second result of the whole cache control module in the tested module.

The tested modules comprise one or more cache control modules in the multi-core processor.

In some implementations, the multi-core processor includes n processor cores, where n is a positive integer, each of which may include multiple cache control modules, e.g., a first level cache and a second level cache, that are processor core private cache control modules.

In some implementations, the multi-core processor may further include a last level cache module, which may be a third level cache control module, that is a cache control module shared by multiple processor cores. Alternatively, multiple processor cores may be interconnected with the last level cache module through a network on chip, as shown in FIG. 2.

Alternatively, the tested modules in this embodiment may be a second-level cache control module and a third-level cache control module, that is, a second-level cache control module and a last-level cache control module in each processor core.

It can be understood that when the test stimulus is input to the second-level cache control module in the tested module, a first result corresponding to the second-level cache control module is obtained; when the test excitation is input to a three-level cache control module in the tested module, a first result corresponding to the three-level cache control module is obtained; accordingly, when the test stimulus is input into all the cache control modules in the tested module, a second result of the whole cache control modules is obtained. That is, when the test stimulus is input to a certain cache control module alone, a first result corresponding to the cache control module is obtained, and when the test stimulus is input to all the cache control modules, a second result of the output of all the cache control modules as a whole is obtained.

S103, a local score board corresponding to any cache control module and a global score board corresponding to all cache control modules are obtained, and test excitation is respectively input into the local score board and the global score board to obtain a third result and a fourth result.

In some implementations, the scoreboard may include the correct results for the test stimulus. That is, the scoreboard may receive the same test stimulus as the module under test and output the corresponding correct results. It will be appreciated that the scope of the modules under test for the local scoreboard and the global scoreboard are different, and in some implementations, the local scoreboard is a scoreboard corresponding to a particular cache control module, and the global scoreboard is a scoreboard corresponding to all cache control modules, that is, a scoreboard corresponding to all modules under test.

In some implementations, for any cache control module of the tested module, there is a corresponding local scoreboard, and the cache control module receives the same test stimulus as its corresponding local scoreboard, which outputs a corresponding third result.

Further, for all cache control modules in the overall tested module, the same test stimulus is received with the corresponding global scoreboard, which outputs the corresponding fourth result. It can be understood that the third result/fourth result output by the local score board and the global score board are both correct results, so that whether the output result of the tested module is wrong can be judged based on the result output by the score board as a comparison.

And S104, respectively verifying the first result and the second result according to the third result and the fourth result, and determining the verification result of the tested module.

In some implementations, since the first result is a result obtained by inputting a test stimulus into a certain cache control module, and the third result is a result output by a local scoreboard corresponding to a specific cache control module, the same test stimulus can be respectively input into the cache control module and the local scoreboard corresponding to the cache control module to obtain the first result and the third result, and the first result and the third result are compared to determine whether an error occurs in the cache control module. Correspondingly, for all the cache control modules, the second results of the whole corresponding to all the cache control modules can be compared with the fourth results output by the global score board, and whether the tested module has errors or not is judged according to the comparison between the second results and the fourth results.

Optionally, if the first result is inconsistent with the corresponding third result, it may be determined that an error occurs in the corresponding cache control module, and if the second result is inconsistent with the fourth result, it may also be determined that an error occurs in the cache control module.

In this embodiment, generation of constraint random test excitation is achieved through a random constraint address pool, so that the generated test excitation is a read-write related address, efficiency of test excitation generation is improved, feasibility of conflict operation is improved, a local first result and a global second result in a corresponding tested module are determined through input test excitation, then a corresponding third result and a corresponding fourth result are respectively determined based on a local score board and a global score board, the local result and the global result are respectively compared, namely the first result and the third result are compared, the second result and the fourth result are compared, accuracy comparison of results is conducted based on each level score board, and module level verification of a cache control module of the multi-core processor is efficiently and accurately completed, and verification effects are better.

Based on the foregoing embodiments, fig. 3 is a schematic flow chart of obtaining a first result and a second result according to an embodiment of the present application. As shown in fig. 3, the method may include the steps of:

S301, acquiring a random constraint address pool, and generating test excitation according to the random constraint address pool.

In the embodiment of the present application, the implementation method of step S301 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

S302, inputting test excitation into the tested module, and determining the access address and the access request of the tested module according to the test excitation.

Alternatively, the access request may include a read request and a write request.

In some implementations, the test stimulus may include an access address and an access request, so that information extraction may be performed on the test stimulus to obtain an access address to be accessed by the tested module; the access address is used for indicating the address which the tested module needs to access, the address stores corresponding data, the access request is used for reflecting the request of the tested module to the data of the access address, the read request is used for reading the data of the access address, and the write request is used for writing the data in the access address.

In some implementations, state information for each access address corresponding cache block to a last level cache control module may be obtained. The state information is one of invalid, shared and exclusive, and the access request of the cache control module is determined according to the state information; the read requests may include read shared cache block requests and read exclusive cache block requests.

The cache block corresponding to the access address does not exist in the upper-level cache control module or is in an invalid state, and the access request of the cache control module is determined to be a read exclusive cache block request and/or a read shared cache block request; and the cache block corresponding to the access address is in a shared state in the upper-level cache control module, and the access request of the cache control module is determined to be a read exclusive cache block request.

In some implementations, if the cache block corresponding to the access address does not exist in the previous-level cache control module, the cache block is retrieved and then replaced, and the cache block of the previous-level cache control module is valid, so that the access request of the cache control module is determined to be a write request; wherein the address of the write request is the address of the replaced cache block and the state is the state of the replaced cache block.

If the stimulus generation module is arranged on the second-level cache control module of the tested module, the stimulus generation module simulates a first-level cache which is a higher-level cache of the second-level cache, and generates test stimulus for the second-level cache. Test stimuli to the tertiary cache come from its upper level cache, the second level cache.

The test stimulus to the memory is from the last level cache, which is a read-write request from the last level cache to the defined memory size address, that is, the test stimulus is a read-write request to the data of the corresponding address in the memory.

S303, obtaining a first result and a second result based on the access address and the access request.

In some implementations, the access request may be converted to a read or write operation command for the data, that is, the corresponding read or write operation command may be determined from the access request. If the last-level cache requests the memory access, the last-level cache finally needs to be converted into a read or write operation command to the memory.

It will be appreciated that the operation of the multi-core processor on the memory is ultimately completed by writing data into the memory or reading data from the memory, with the result that the data in the memory is changed. The embodiment can use a memory model as a simulation memory of the multi-core processor cache control module, the simulation memory is simulated by a two-dimensional array indexed by row and column addresses, and the memory control submodule converts a request command sent by a processor core into a read-write operation command for the two-dimensional array.

Responding to the access request as a write request, and writing data corresponding to the access address into a memory to obtain a first result corresponding to the cache control module or a second result of the whole cache control module; and responding to the access request as a read request, and reading data corresponding to the access address to obtain a first result corresponding to the cache control module or a second result of the whole cache control module. That is, when the access request is a write request, writing the data corresponding to the access address into the corresponding address of the memory, and when the access request is a read request, returning the data corresponding to the access address to obtain a first result and a second result corresponding to the tested module.

In some implementations, the functional points in the module under test may also be acquired; after inputting the test excitation into the tested module, detecting the covered target function points in the tested module based on an analysis tool; the test stimulus is increased according to the number of target function points. That is, the coverage rate analysis is performed according to the result of the simulation output, the function points can be defined in advance by the verifier, and then the occurrence of each function point and the combination thereof is monitored when the test program is run according to the coverage rate analysis tool software, so as to obtain a coverage rate analysis report, wherein the coverage rate analysis report comprises the number of covered target function points, and according to the coverage rate analysis report, the proportion of operations which are not covered is adjusted in the excitation generation part, for example, the address proportion extracted from a random address pool is adjusted, so that the test excitation is increased in a targeted manner.

In the embodiment, the generation of the constraint random test excitation is realized through the random constraint address pool, so that the generated test excitation is a read-write related address, the efficiency of the test excitation generation is improved, the feasibility of conflict operation generation is improved, and the corresponding first result and second result are obtained based on the access request and the access address in the test excitation, so that the debugging is easy; the coverage rate analysis can be further increased, the test excitation is adjusted in a targeted manner, the advantage of high module verification coverage rate is achieved, and a first result and a second result which are accurate are obtained through the access address and the access request in the test excitation so as to facilitate the follow-up verification of the cache module of the multi-core processor with high efficiency and high coverage rate.

Fig. 4 is a flowchart of another module verification method of a multi-core processor according to an embodiment of the present application. As shown in fig. 4, the module verification method of the multi-core processor may include the steps of:

S401, acquiring a random constraint address pool, and generating test excitation according to the random constraint address pool.

In the embodiment of the present application, the implementation method of step S401 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

S402, inputting test excitation into the tested module, and determining the access address and the access request of the tested module according to the test excitation.

In the embodiment of the present application, the implementation method of step S402 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

S403, obtaining a first result and a second result based on the access address and the access request.

In the embodiment of the present application, the implementation method of step S403 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

S404, a local score board corresponding to any cache control module and a global score board corresponding to all cache control modules are obtained, and test excitation is respectively input into the local score board and the global score board to obtain a third result and a fourth result.

In some implementations, a local scoreboard corresponding to each cache control module may be obtained, the cache control module being the same as the local scoreboard corresponding test stimulus; that is, the local score board corresponding to each cache control module is obtained, the same test stimulus is respectively input into the cache control module and the local score board, and whether the first result and the third result output by the local score board are the same is determined.

And responding to the access request in the test stimulus as a read request, and determining a verification result of the cache control module according to the first result of the cache control module and the third result of the local score board. When the access request in the test stimulus is a read request, the module to be tested returns the read data, namely a first result; correspondingly, the local score board also returns the data read by the test stimulus, namely a third result, and the first result and the third result are compared to determine the verification result of the cache control module.

In some implementations, the first result or the third result may further include state information of the cache control module, where the state information is used to indicate a state of the cache control module corresponding to the test stimulus, such as an invalid state, a shared state, and an exclusive state.

As shown in the following tables 1 and 2, the local score boards corresponding to different cache control modules can be represented, and besides the state information, the local score boards can also comprise valid bits, addresses, data and other information, wherein the valid bits are used for representing whether the item in the score boards is valid or not, and 0 represents invalid, and 1 represents valid; the address is an access address, and the data is the data corresponding to the access address, namely the data which should be returned by the cache control module; the state of the cache control module corresponding to the item comprises an Invalid state Invalid, a Shared state Shared and an Exclusive state Exclusive; when the cache control module is in an Invalid state, indicating that the cache control module has not stored valid data, wherein the processor core fails in reading/writing; when the cache control module is in a Shared state, the processor core reads the cache control module to hit directly, and writes the cache control module to fail; when the cache control module is in an Exclusive state, the processor core reads/writes the cache control module and directly hits.

TABLE 1

TABLE 2

In some implementations, generation of test incentives may also be performed based on state information of the cache control module, and in response to the cache control module being in an invalid state, a write failure and/or a read failure may be performed, and the corresponding test incentives may be a read exclusive cache block request and/or a read shared cache block request; in response to the cache control module being in a shared state, which may be a write failure, the corresponding test stimulus may be a read exclusive cache block, which is input to the next level cache control module.

Further, for the global scoreboard, the global scoreboard is the same with the test stimulus corresponding to all the cache control modules, that is, the same test stimulus is input into all the cache control modules and the global scoreboard, the access request in the test stimulus is responded as a read request, and the verification result of the cache control module is determined according to the fourth result output by the global scoreboard and the second result output by all the cache control modules.

In some implementations, the global control module may also include a valid bit, an address, and data, the valid bit indicating whether the item is valid in the scoreboard, where 0 indicates invalid and 1 indicates valid; the address is an access address, and the data is the data corresponding to the access address, that is, the data that should be returned by the cache control module after the test stimulus is input, as shown in table 3.

TABLE 3 Table 3

In the embodiment of the present application, the implementation method of step S404 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

And S405, respectively verifying the first result and the second result according to the third result and the fourth result, and determining the verification result of the tested module.

In some implementations, for each cache control module, responding to the state information of the first result being the same as the state information of the third result, and the data information of the first result being the same as the data information of the third result, the verification result of the corresponding cache control module indicates normal; and responding to the state information of the first result being different from the state information of the third result and/or the data information of the first result being different from the data information of the third result, wherein the verification result of the corresponding cache control module indicates an error. That is, when the data information and the status information returned by the cache control module are consistent with the data information and the status information read from the local scoreboard, the verification result corresponding to the cache control module indicates normal; when the data information and the state information returned by the cache control module are inconsistent with the data information and the state information read from the local score board, the error exists in the design, and the test program is stopped.

It can be understood that when comparing the data information and the status information of the cache control module with the data information and the status information of the local score board, the data information returned by the cache control module is compared with the data information read from the local score board, the status information returned by the cache control module is compared with the status information read from the local score board, that is, the data information and the status information are respectively compared, when the data information and the status information returned by the cache control module are consistent with the data information and the status information read from the local score board, the verification result of the corresponding cache control module indicates normal, when the data information returned by the cache control module is inconsistent with the data information read from the local score board, and/or the status information returned by the cache control module is inconsistent with the status information read from the local score board, which indicates that an error exists in design, and the test program is stopped.

In some implementations, for all cache control modules, responsive to the second result being the same as the fourth result, the validation result indication for the corresponding cache control module is normal; in response to the second result being different from the fourth result, the validation result of the corresponding cache control module indicates an error. That is, when the data corresponding to all the cache control modules are consistent with the data read from the global scoreboard, the verification result of the cache control module indicates normal; otherwise, when the data corresponding to the cache control module is inconsistent with the data read from the global score board, the verification result of the cache control module indicates an error.

It can be understood that when any score board has a comparison error, the verification result indicates the error and the program reports the error.

In the embodiment of the present application, the implementation method of step S405 may be implemented in any manner in each embodiment of the present disclosure, which is not limited herein, and is not described herein again.

In this embodiment, generation of constraint random test excitation is achieved through a random constraint address pool, efficiency of test excitation generation is improved, feasibility of collision operation is improved, based on an access request and an access address in the test excitation, corresponding first results and second results are obtained from a memory, test excitation identical to a cache control module is input into a local score board and a global score board respectively, so that corresponding correct results under each test excitation, namely a third result and a fourth result, the first results and the second results are compared with the third result and the fourth result respectively, data information and/or state information are compared in different score boards, whether the first results and the second results are consistent with the corresponding correct third results and fourth results is determined, whether verification results of the cache control module are wrong is further determined, efficient module verification is achieved, and the overall verification process is easy to debug and easy to implement.

On the basis of the above embodiment, as shown in fig. 5, which is a logic schematic diagram of a module verification method of a multi-core processor provided by the embodiment of the present application, an address input stimulus generating module is selected from a random address pool according to a certain proportion, a test stimulus input tested module is generated by the stimulus generating module, that is, in a second-level cache control module and a third-level cache control module, by comparing the data in the second-level cache control module and the third-level cache control module with the result of a corresponding local score board, the data in an analog memory is read and compared with the result of a global score board, whether the verification result is correct or not is determined, and high-efficiency module level verification is realized.

In order to achieve the above embodiment, the present application further provides a module verification device of a multi-core processor.

Fig. 6 is a schematic structural diagram of a module verification device of a multi-core processor according to an embodiment of the present application. As shown in fig. 6, the module verification apparatus 600 of the multi-core processor includes:

The stimulus generation module 601 is configured to obtain a random constraint address pool, and generate a test stimulus according to the random constraint address pool.

The first obtaining module 602 is configured to input a test stimulus to a tested module, to obtain a first result of any cache control module in the tested module, and a second result of the whole cache control module in the tested module;

The second obtaining module 603 is configured to obtain a local score board corresponding to any cache control module and a global score board corresponding to all cache control modules, and input test stimulus to the local score board and the global score board respectively, so as to obtain a third result and a fourth result;

and the verification module 604 is used for verifying the first result and the second result respectively by the third result and the fourth result, and determining the verification result of the tested module.

Further, in one possible implementation manner of the embodiment of the present application, the random constraint address pool includes addresses of N access requests, where N is a positive integer, and the excitation generation module 601 includes:

one or more sample addresses are selected from the pool of randomly constrained addresses, and corresponding test stimulus is generated from the sample addresses.

Further, in one possible implementation of an embodiment of the present application, the apparatus 600 further includes:

acquiring a function point in a tested module;

after inputting the test excitation into the tested module, detecting the covered target function points in the tested module based on an analysis tool;

The test stimulus is increased according to the number of target function points.

Further, in one possible implementation manner of the embodiment of the present application, the first obtaining module 602 includes:

determining access addresses and access requests of the cache control module according to the test stimulus, wherein the access requests comprise read requests and write requests;

based on the access address and the access request, a first result or a second result is obtained.

Further, in a possible implementation manner of the embodiment of the present application, the last-level cache control module generates an operation command for accessing the memory according to the access request.

Further, in one possible implementation manner of the embodiment of the present application, the access request includes a write request and a read request, and the first obtaining module 602 includes:

Responding to the access request as a write request, and writing data corresponding to the access address into a cache control module/memory to obtain a first result or a second result;

and responding to the access request as a read request, and reading data corresponding to the access address to obtain a first result or a second result.

And responding to the access request in the test stimulus as a read request, and determining a verification result of the cache control module according to the first result of the cache control module and the third result of the local score board.

Further, in one possible implementation manner of the embodiment of the present application, the first result and the third result include state information of the cache control module, where the apparatus 600 includes:

Responding to the condition information in the first result being the same as the condition information in the third result, and the data information of the first result being the same as the data information of the third result, the verification result of the corresponding cache control module indicating normal;

And responding to the state information of the first result being different from the state information of the third result and/or the data information of the first result being different from the data information of the third result, wherein the verification result of the corresponding cache control module indicates an error.

Further, in one possible implementation of the embodiment of the present application, the global scoreboard is the same as the test stimulus input by all cache control modules, and the apparatus 600 includes:

and responding to the access request in the test stimulus as a read request, and determining the verification result of the cache control module according to the second results of all the cache control modules and the fourth results of the global score board.

Further, in one possible implementation of an embodiment of the present application, the apparatus 600 includes:

responding to the second result being identical to the fourth result, and indicating that the verification result of the corresponding cache control module is normal;

in response to the second result being different from the fourth result, the validation result of the corresponding cache control module indicates an error.

And responding to the first result and the third result, and/or the second result and the fourth result are different, wherein the verification result of the tested module indicates errors.

acquiring state information of a cache block corresponding to each access address in a higher-level cache control module, wherein the state information comprises one of invalidation, sharing and monopolization;

and determining the access request of the cache control module according to the state information.

determining that the access request of the cache control module is a read exclusive cache block request and/or a read shared cache block request in response to the cache block corresponding to the access address not being present or being in an invalid state in the previous-level cache control module;

and in response to the cache block corresponding to the access address being in a shared state in the upper-level cache control module, determining that the access request of the cache control module is a read exclusive cache block request.

Responding to the fact that the cache block corresponding to the access address does not exist in the upper-level cache control module, wherein the cache block is effective in the cache block of the upper-level cache control module which is replaced after being retrieved, and determining that the access request of the cache control module is a write request; wherein the address of the write request is the address of the replaced cache block and the state is the state of the replaced cache block.

It should be noted that the foregoing explanation of the embodiment of the module verification method of the multi-core processor is also applicable to the module verification device of the multi-core processor of this embodiment, and will not be repeated herein.

In the embodiment of the application, the first local result and the second global result corresponding to the tested module are determined through input test excitation, then the third local result and the fourth local result are respectively determined based on the local score board and the global score board, the first local result and the third global result are respectively compared, the second result and the fourth result are compared, the result correctness comparison is carried out based on the score boards at all levels, the module level verification of the cache control module of the multi-core processor is effectively completed, and the verification effect is better.

In order to achieve the above embodiment, the present application further provides an electronic device, including: a processor, and a memory communicatively coupled to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the methods provided by the previous embodiments.

In order to implement the above-described embodiments, the present application also proposes a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are adapted to implement the methods provided by the foregoing embodiments.

In order to implement the above embodiments, the present application also proposes a computer program product comprising a computer program which, when executed by a processor, implements the method provided by the above embodiments.

The processing of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user in the application accords with the regulations of related laws and regulations and does not violate the popular regulations of the public order.

It should be noted that personal information from users should be collected for legitimate and reasonable uses and not shared or sold outside of these legitimate uses. In addition, such collection/sharing should be performed after receiving user informed consent, including but not limited to informing the user to read user agreements/user notifications and signing agreements/authorizations including authorization-related user information before the user uses the functionality. In addition, any necessary steps are taken to safeguard and ensure access to such personal information data and to ensure that other persons having access to the personal information data adhere to their privacy policies and procedures.

The present application contemplates embodiments that may provide a user with selective prevention of use or access to personal information data. That is, the present disclosure contemplates that hardware and/or software may be provided to prevent or block access to such personal information data. Once personal information data is no longer needed, risk can be minimized by limiting data collection and deleting data. In addition, personal identification is removed from such personal information, as applicable, to protect the privacy of the user.

In the foregoing description of embodiments, reference has been made to the terms "one embodiment," "some embodiments," "example," "a particular example," or "some examples," etc., meaning that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.

Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A method of module validation for a multi-core processor, the method comprising:

respectively verifying the first result and the second result according to the third result and the fourth result, and determining a verification result of the tested module;

And verifying the first result and the second result according to the third result and the fourth result, respectively, to determine a verification result of the tested module, including:

responding to the access request in the test stimulus as a read request, and determining a verification result of the cache control module according to a first result of the cache control module and a third result of the local score board;

And determining the verification result of the cache control module according to the second results of all the cache control modules and the fourth results of the global score board.

2. The method of claim 1, wherein the random constrained address pool includes addresses of N access requests, N being a positive integer, and wherein generating test stimulus from the random constrained address pool comprises:

3. The method according to claim 1 or 2, characterized in that the method further comprises:

acquiring a function point in a tested module;

after inputting the test excitation into the tested module, detecting a covered target functional point in the tested module based on an analysis tool;

and increasing the test stimulus according to the number of the target function points.

4. A method according to claim 3, wherein the process of obtaining the first result or the second result comprises:

Determining an access address and an access request of the cache control module according to the test stimulus, wherein the access request comprises a read request and a write request;

And obtaining the first result or the second result based on the access address and the access request.

5. The method of claim 4, wherein the last level cache control module generates an operation command to access memory based on the access request.

6. The method of claim 5, wherein the obtaining the first result or the second result based on the access address and the access request comprises:

responding to the access request as a write request, and writing data corresponding to the access address into a cache control module/memory to obtain the first result or the second result;

And responding to the access request as a read request, and reading data corresponding to the access address to obtain the first result or the second result.

7. The method of claim 1, wherein the first result and the third result include status information of the cache control module, wherein the determining the verification result of the cache control module according to the first result of the cache control module and the third result of the local scoreboard includes:

Responding to the state information in the first result being identical to the state information in the third result, wherein the data information of the first result is identical to the data information of the third result, and the verification result corresponding to the cache control module indicates normal;

responsive to the state information of the first result being different from the state information of the third result and/or the data information of the first result being different from the data information of the third result, the validation result corresponding to the cache control module indicates an error.

8. The method of claim 1, wherein determining the validation result of the cache control module based on the second results of all cache control modules and the fourth result of the global scoreboard comprises:

Responding to the second result being identical to the fourth result, wherein the verification result corresponding to the cache control module indicates normal;

responsive to the second result being different from the fourth result, the validation result corresponding to the cache control module indicates an error.

9. The method according to claim 1, characterized in that the method comprises:

and responding to the first result and the third result, and/or the second result and the fourth result, wherein the verification result of the tested module indicates an error.

10. The method of claim 4, wherein determining the access request of the cache control module comprises:

Acquiring state information of a cache block corresponding to each access address in a higher-level cache control module, wherein the state information is one of invalid, shared and exclusive;

11. The method of claim 10, wherein said determining an access request for the cache control module based on the state information comprises:

12. The method of claim 11, wherein said determining an access request for the cache control module based on the state information comprises:

Responding to the fact that the cache block corresponding to the access address does not exist in the upper-level cache control module, wherein the cache block is effective in the cache block of the upper-level cache control module replaced after being retrieved, and determining that the access request of the cache control module is a write request; wherein the address of the write request is the address of the replaced cache block and the state is the state of the replaced cache block.

13. A module verification apparatus of a multi-core processor, comprising:

The verification module is used for verifying the first result and the second result according to the third result and the fourth result respectively and determining a verification result of the tested module;

Wherein, the verification module is further configured to:

14. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;

The memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-12.

15. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-12.

16. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1-12.