CN117971614B

CN117971614B - Clock detection method, system, equipment, medium and server

Info

Publication number: CN117971614B
Application number: CN202410382840.2A
Authority: CN
Inventors: 张鑫伟; 李金锋; 袁征峰; 朱保彬
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-03-29
Filing date: 2024-03-29
Publication date: 2024-06-07
Anticipated expiration: 2044-03-29
Also published as: CN117971614A

Abstract

The application discloses a clock detection method, a clock detection system, clock detection equipment, clock detection media and a clock detection server, relates to the field of data processing, and is used for solving the problem of inaccurate data transmission caused by inaccurate clocks in single-wire communication. The scheme encodes own clock signals and data signals to obtain communication signals; and sending the communication signal to the baseboard management controller so as to analyze the communication signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal obtained by analysis. The application can realize the transmission of the hard disk log data, the hard disk state signal and the clock signal through the hard disk state pin, calibrate the clock of the hard disk through encoding the clock signal and the data signal and analyzing the communication signal, further determine whether the data signal is transmitted based on the correct clock, find out the problem in time and ensure the accuracy of the data signal transmission, and further ensure the reliability of monitoring the hard disk.

Description

Clock detection method, system, equipment, medium and server

Technical Field

The present application relates to the field of data processing, and in particular, to a clock detection method, system, device, medium, and server.

Background

The hard disk is one of the most important storage devices of a computer, and thus, healthy operation of the hard disk is one of the key factors for guaranteeing the reliability of a device server.

In order to ensure accurate control of the running state of the hard disk, equipment is required to monitor in the running process of the hard disk so as to acquire the state information of the hard disk. The main hard disk monitoring schemes at present are divided into hard disk in-band monitoring and hard disk out-of-band monitoring. In-band monitoring of a hard disk, namely, obtaining state information of the hard disk after data communication is carried out between monitoring software running on a central processing unit (Central Processing Unit, CPU) and the hard disk, the monitoring scheme is often difficult to present monitoring data to operation and maintenance personnel. The out-of-band monitoring of the hard disk is performed after the status information of the hard disk is acquired through the baseboard management controller (Baseboard Management Controller, BMC), if the hard disk is in single-wire communication with the baseboard management controller, the hard disk can only transmit monitoring data to the baseboard management controller and cannot perform clock calibration through an additional line, so that the baseboard management controller cannot detect whether the monitoring data transmitted by the hard disk is based on a correct clock, the transmitted monitoring data may be inaccurate, and the reliability of monitoring the hard disk is low.

Disclosure of Invention

The application aims to provide a clock detection method, a system, equipment, a medium and a server, which can realize the transmission of hard disk log data, hard disk state signals and clock signals through a hard disk state pin, and can calibrate the clock of a hard disk through encoding the clock signals and the data signals and analyzing communication signals, so that whether the data signals are transmitted based on the correct clock can be determined, the accuracy of data signal transmission can be ensured by finding problems in time, and the reliability of monitoring the hard disk can be further ensured.

In a first aspect, the present application provides a clock detection method applied to a baseboard management controller, where the baseboard management controller communicates with a hard disk in a single line, the clock detection method includes:

Receiving a communication signal sent by the hard disk through a hard disk state pin, wherein the communication signal is a signal obtained by encoding the hard disk according to a data signal and a clock signal of the hard disk, and the data signal is a signal obtained by modulating the hard disk according to hard disk log data and the hard disk state signal corresponding to the hard disk state pin;

Analyzing the communication signal to obtain the clock signal and the data signal;

And judging whether the clock of the hard disk is accurate or not based on the clock signal.

In one embodiment, parsing the communication signal to obtain the clock signal and the data signal includes:

Analyzing the communication signals to obtain at least two sign signals and data to be transmitted; the data signal comprises data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used for representing the current transmission progress of the data signal, and the hard disk encodes the current clock frequency of the hard disk into the flag signal;

judging whether the clock of the hard disk is accurate based on the clock signal comprises the following steps:

and judging whether the clock of the hard disk is accurate or not according to the pulse widths corresponding to the two marking signals.

In one embodiment, determining whether the clock of the hard disk is accurate according to pulse widths corresponding to the two flag signals includes:

judging whether the pulse widths corresponding to the two mark signals are within a preset range of standard pulse widths or judging whether the difference value between the pulse widths corresponding to the two mark signals is within an error range;

if the pulse widths corresponding to the two marking signals are within a preset range of the standard pulse width, or the difference value is within the error range, judging that the clock of the hard disk is accurate;

If the pulse widths corresponding to the two marking signals are not in the preset range of the standard pulse width or the difference value is not in the error range, judging that the clock of the hard disk is inaccurate.

In one embodiment, the hard disk state pin outputs a control signal of a first level in a state that the hard disk is preset, a plurality of pulse signals of a second level with preset width are inserted into the control signal, so that the control signal is divided by the pulse signals to obtain pulse widths of the first level corresponding to each data bit one by one, the current clock frequency of the control signal is encoded into the pulse signals of the second level with preset width, and the communication signal is obtained according to the pulse signals of the second level with preset width and the pulse widths of the first level, wherein the data signal comprises a plurality of data bits, and the second level is opposite to the first level;

analyzing the communication signal to obtain the clock signal and the data signal, including:

Analyzing the communication signals to obtain at least two pulse signals with the second level and a plurality of pulse widths with the first level;

And judging whether the clock of the hard disk is accurate or not based on at least two pulse signals of the second level.

In one embodiment, determining whether the clock of the hard disk is accurate based on at least two pulse signals of the second level includes:

Judging whether the width difference value of the two pulse signals of the second level is within an error range or not;

if the clock is within the error range, judging that the clock of the hard disk is accurate;

And if the clock is not in the error range, judging that the clock of the hard disk is inaccurate.

Analyzing the communication signal to obtain a square wave signal and the data signal, wherein the square wave frequency of the square wave signal and the clock frequency of the hard disk are in a second mapping relation;

And judging whether the clock of the hard disk is accurate or not based on the square wave signal.

In one embodiment, determining whether the clock of the hard disk is accurate based on the square wave signal includes:

Judging that the frequency difference between the two square wave signals is in a preset frequency range;

If the frequency difference value is in the preset frequency range, judging that the clock of the hard disk is accurate;

and if the frequency difference value is not in the preset frequency range, judging that the clock of the hard disk is inaccurate.

In one embodiment, further comprising:

And when the clock of the hard disk is inaccurate, sending a feedback signal to the hard disk and/or a hard disk controller through the hard disk state pin so that the hard disk retransmits the data signal or the communication signal.

In a second aspect, the present application provides a clock detection method applied to a hard disk, where the hard disk is in single-wire communication with a baseboard management controller, the clock detection method includes:

encoding own clock signals and data signals to obtain communication signals, wherein the data signals are signals obtained by modulating the hard disk according to hard disk log data and hard disk state signals corresponding to hard disk state pins;

And sending the communication signal to the baseboard management controller through a hard disk state pin so that the baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal.

In one embodiment, the data signal includes a flag signal of a fixed pulse width and data to be transmitted, the flag signal is used for representing a current transmission progress of the data signal, and encoding a clock signal and the data signal of the flag signal to obtain a communication signal, and the method includes:

Encoding the current clock frequency of the self into the sign signal;

integrating the marking signal and the data to be transmitted to obtain the communication signal;

The baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and judges whether the clock of the hard disk is accurate based on the clock signal, including:

the baseboard management controller analyzes the communication signals to obtain at least two marking signals and data to be transmitted;

In one embodiment, the hard disk state pin outputs a control signal of a first level when the hard disk is in a preset state; encoding the clock signal and the data signal of the self to obtain a communication signal, including:

Inserting a plurality of pulse signals with second level of preset width into the control signals, and dividing the control signals by utilizing the pulse signals to obtain pulse widths of the first level corresponding to each data bit one by one; the data signal includes a plurality of the data bits, the second level being opposite the first level;

And encoding the clock signal of the communication signal, a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain the communication signal.

In one embodiment, encoding the own clock signal with a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain the communication signal includes:

Encoding the current clock frequency of the communication signal into a pulse signal with a second level of the preset width, wherein the clock frequency and the preset width form a first mapping relation, and the communication signal comprises a plurality of pulse signals with the second level of the preset width and a plurality of pulse widths with the first level;

The baseboard management controller analyzes the communication signals to obtain at least two pulse signals with the second level and a plurality of pulse widths with the first level;

In one embodiment, encoding the own clock signal and data signal to obtain the communication signal includes:

encoding the current clock frequency of the self-body into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relation;

inserting the square wave signal into the data signal to obtain the communication signal;

And the baseboard management controller analyzes the communication signal to obtain the square wave signal and the data signal, and judges whether the clock of the hard disk is accurate or not based on the square wave signal.

Encoding each data bit into pulse widths corresponding to the data bits one by one to obtain a first pulse width signal, wherein the data signal comprises a plurality of data bits, and the first pulse width signal comprises pulse widths corresponding to the data bits;

encoding the square wave signal and the first pulse width signal to obtain the communication signal;

And the baseboard management controller analyzes the communication signal to obtain the square wave signal and the first pulse width signal, and judges whether the clock of the hard disk is accurate or not based on the square wave signal.

In one embodiment, encoding the square wave signal and the first pulse width signal to obtain the communication signal includes:

And respectively inserting at least two square wave signals before the pulse width corresponding to the first data bit and/or after the pulse width corresponding to the last data bit and/or between the pulse widths corresponding to any two data bits to obtain the communication signal.

In one embodiment, encoding each data bit into a pulse width corresponding to the data bit one to obtain a first pulse width signal, including:

And encoding each data bit into a pulse width with a duty ratio corresponding to the data bit one by one to obtain the first pulse width signal, wherein the duty ratio and the data bit are in a third mapping relation.

And encoding each data bit into a pulse width of a preset level corresponding to the data bit to obtain the first pulse width signal, wherein the pulse width of the preset level and the data bit are in a fourth mapping relation.

In one embodiment, further comprising:

After the baseboard management controller judges that the clock of the hard disk is inaccurate, receiving a feedback signal sent by the baseboard management controller;

The data signal or the communication signal is retransmitted based on the feedback signal.

In a third aspect, the present application also provides a clock detection system applied to a baseboard management controller, where the baseboard management controller communicates with a hard disk in a single line, the clock detection system includes:

the receiving unit is used for receiving a communication signal sent by the hard disk through a hard disk state pin, and the hard disk codes the obtained signal according to a data signal and a clock signal of the hard disk when the communication signal is sent;

the analysis unit is used for analyzing the communication signal to obtain the clock signal and the data signal;

And the judging unit is used for judging whether the clock of the hard disk is accurate or not based on the clock signal.

In a fourth aspect, the present application also provides a clock detection system, for single-wire communication between a hard disk and a baseboard management controller, the clock detection system comprising:

The encoding unit is used for encoding the clock signal and the data signal of the encoding unit to obtain a communication signal, wherein the data signal is a signal obtained by modulating the hard disk according to the hard disk log data and the hard disk state signal corresponding to the hard disk state pin;

And the sending unit is used for sending the communication signal to the baseboard management controller through a hard disk state pin so that the baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal.

In a fifth aspect, the present application also provides an electronic device, including:

A memory for storing a computer program;

a processor for implementing the steps of the clock detection method as described above when executing the computer program.

In a sixth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the clock detection method as described above.

In a seventh aspect, the present application further provides a server, including a hard disk and a baseboard management controller, where the hard disk is connected with the baseboard management controller by a single line, and there is only one transmission channel between the hard disk and the baseboard management controller by a single line;

the baseboard management controller is used for realizing the clock detection method applied to the baseboard management controller; the hard disk is used for realizing the steps of the clock detection method applied to the hard disk.

The application provides a clock detection method, a clock detection system, clock detection equipment, clock detection media and a clock detection server, relates to the field of data processing, and is used for solving the problem of inaccurate data transmission caused by inaccurate clocks in single-wire communication. The scheme encodes own clock signals and data signals to obtain communication signals; and sending the communication signal to the baseboard management controller so as to analyze the communication signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal obtained by analysis. The application can realize the transmission of the hard disk log data, the hard disk state signal and the clock signal through the hard disk state pin, calibrate the clock of the hard disk through encoding the clock signal and the data signal and analyzing the communication signal, further determine whether the data signal is transmitted based on the correct clock, find out the problem in time and ensure the accuracy of the data signal transmission, and further ensure the reliability of monitoring the hard disk.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a connection between a hard disk and a baseboard management controller according to the present application;

FIG. 2 is a flowchart of a clock detection method applied to a baseboard management controller according to the present application;

FIG. 3 is a schematic diagram of a data signal according to the present application;

FIG. 4 is a schematic diagram of a square wave signal and data signal combination according to the present application;

FIG. 5 is a schematic diagram of a square wave signal according to the present application;

FIG. 6 is a flowchart of a method for detecting a clock applied to a hard disk according to the present application;

FIG. 7 is a flowchart of a method for detecting a clock applied to a hard disk according to the present application;

FIG. 8 is a flowchart of a clock detection method applied to a baseboard management controller according to the present application;

FIG. 9 is a schematic diagram of a clock detection system for a hard disk according to the present application;

FIG. 10 is a schematic diagram of a clock detection system applied to a baseboard management controller according to the present application;

fig. 11 is a schematic diagram of an electronic device provided by the present application.

Detailed Description

The application provides a clock detection method, a system, equipment, a medium and a server, which can realize the transmission of hard disk log data, hard disk state signals and clock signals through a hard disk state pin, and can calibrate the clock of a hard disk through encoding the clock signals and the data signals and analyzing communication signals, so that whether the data signals are transmitted based on the correct clock can be determined, the accuracy of data signal transmission can be ensured by finding problems in time, and the reliability of monitoring the hard disk can be further ensured.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

For ease of understanding, the description will first be made of the content related to the hard disk out-of-band monitoring scheme. Out-of-band management means that network management is realized through a special network management channel, network management data and service data are separated, and an independent channel is established for the network management data. In the channel, only the management data is transmitted, and the network management data is separated from the service data, so that the efficiency and the reliability of the network management can be improved, and the safety of the network management data can be improved.

Because in-band monitoring cannot meet operation and maintenance requirements, after the server is deployed, an out-of-band management monitoring function is provided through the baseboard management controller. The baseboard management controller is a specialized service processor that uses sensors to monitor the status of a computer, web server, or other hardware driven device and communicates with the system administrator of the device via separate connection lines. In actual use, the baseboard management controller is typically mounted on a motherboard or on a main circuit board of the monitored device. The baseboard management controller is used to measure internal physical variables by sensors, such as: temperature, humidity, power supply voltage, fan speed, communication parameters, operating System (OS) functions, and the like. If any of these variables is outside the limits established, the baseboard management controller will notify the system administrator. The baseboard management controller may provide a network (web) service, which has a network communication function and provides a web page to display a monitoring interface, and an operator may obtain monitoring data of the baseboard management controller by connecting the baseboard management controller of the monitored device through a network cable on a site of the device, or connecting the baseboard management controllers of a plurality of monitored devices through a network in a data center.

Due to the limited performance and pin count of the baseboard management controller chips in baseboard management controller systems, complex programmable logic devices (Complex Programmable logic device, CPLD) are often built into baseboard management controller systems to share performance pressure of baseboard management controller chips and to provide more pins to connect sensors or monitored components as the number of components and items to be monitored increases. The complex programmable logic device is mainly composed of three parts, namely a logic block, a programmable interconnection channel and an input/output block (I/O block). A logic block of a complex programmable logic device typically includes 4-20 macro-cells, each macro-cell typically consisting of an array of product terms, product term assignments, and programmable registers. Each macro unit has a plurality of configuration modes, and each macro unit can be used in cascade connection, so that more complex combinational logic and sequential logic functions can be realized. For complex programmable logic devices with higher integration levels, embedded array blocks with on-chip random access Memory (Random Access Memory, RAM)/Read-Only Memory (ROM) are also typically provided. The programmable interconnect channels mainly provide an interconnect network between logic blocks, macro cells, and input/output pins. An input/output block (I/O block) provides an interface between internal logic to the device I/O pins.

The hard disk is an important component of the server and is an important object of out-of-band monitoring management. According to the type of communication interface, the serial connection small computer system interface (SERIAL ATTACHED SCSI, hereinafter abbreviated as SAS)/serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, hereinafter abbreviated as SATA) interface hard disk and the nonvolatile memory host controller interface (Non Volatile Memory Host Controller Interface Specification, NVMHCIS or NVM Express, hereinafter abbreviated as NVMe) interface hard disk are mainly classified. Wherein the SAS interface is compatible with the SATA interface. According to the type of storage medium, the hard disk is mainly divided into a mechanical hard disk (HARD DISK DRIVE, HDD) and a Solid state disk (Solid STATE DISK or Solid STATE DRIVE, SSD). The mechanical hard disk is mainly an SAS interface or an SATA interface. The solid state disk comprises a SAS interface, a SATA interface and an NVMe interface hard disk.

It should be noted that, in the embodiment of the present invention, the baseboard management controller may only include a baseboard management controller chip, or may be a system including a baseboard management controller chip and a complex programmable logic device, where the complex programmable logic device may be a complex programmable logic device only provided on a hard disk back plate or a complex programmable logic device provided on a server motherboard.

Further, in the present application, the reason why the hard disk selects the hard disk status pin to send data to the baseboard management controller is:

Pins of a hard disk are mainly divided into three types: data pins, power pins, and hard disk status pins. The data pin of the hard disk is connected with the in-band system, and the power pin of the hard disk is used for connecting a power supply and a ground signal. Therefore, the baseboard management controller has direct access to the hard disk status pins of the hard disk only.

The hard disk state pins of the hard disk mainly comprise a hard disk state indication pin, a hard disk production debugging pin and a hard disk idle pin.

The hard disk state indication pins comprise hard disk bit state indication pins, hard disk read-write state indication pins and the like. The hard disk state indication pin is a pin for outputting a hard disk state indication signal, for example, the hard disk in-place state indication pin is used for outputting a hard disk in-place state signal, and the hard disk read-write state indication pin is used for outputting a hard disk read-write state signal.

When the hard disk is connected to the hard disk backboard, the hard disk status indication pin mainly has two connection modes, one is connected to the baseboard management controller to inform the baseboard management controller of corresponding hard disk status data, and the other is connected to a control circuit on the hard disk backboard to control the status of corresponding controlled elements so that a user can learn the status of the corresponding hard disk. For example, a hard disk status indicator is provided on the hard disk backboard to indicate the hard disk operation status. If the hard disk is in the read-write state, the hard disk read-write state indicating pin can be controlled to output square wave signals to the amplifying driving circuit of the hard disk read-write state indicating lamp so as to control the hard disk read-write state indicating lamp to be on, and if the hard disk is not in the read-write state (idle state), the hard disk read-write state indicating pin is controlled to output a constant level signal (such as a constant high level signal) so as to enable the hard disk read-write state indicating lamp to be off to indicate that the hard disk read-write state indicating lamp is in the idle state, so that a user can know whether the hard disk is in the read-write state or not by watching the on-off of the hard disk read-write state indicating lamp. The hard disk shows the same based on the state of the hard disk bit state indication pin. Or the hard disk can also output two different constant level signals (one high and one low) through the hard disk state indicating pins to indicate different states, and the signals can be input to the baseboard management controller so as to trigger corresponding recording, processing or control.

The hard disk production debugging pins are mainly pins (debug pins) of the hard disk of the SAS or SATA interface beside the SAS or SATA interface, and are usually used in the production debugging stage of the hard disk, and in the actual use of the hard disk, the production debugging pins can be used for outputting guide information in the hard disk initialization stage.

And the NVMe interface hard disk comprises a hard disk idle pin besides the hard disk state indication pin.

The hard disk status pins are not pins for outputting data of the hard disk, do not have the risk of revealing user data stored in the hard disk, and are directly connected with the baseboard management controller or have the authority of being connected with the baseboard management controller after the hard disk is inserted into the hard disk backboard.

In an embodiment of the present application, the hard disk status pins of the employed hard disk may include at least one of a hard disk status indication pin, a hard disk production debug pin, and a hard disk idle pin.

In the embodiment of the invention, if the hard disk status indication pins such as the hard disk in-place status indication pins and the hard disk read-write status indication pins are adopted, as the hard disk status indication pins are usually connected with General-purpose input/output (GPIO) pins of a baseboard management controller chip or input/output (I/O) pins of a complex programmable logic device in a baseboard management controller, the hardware architecture can be directly adopted without changing the hardware architecture of a server, and the implementation is simple and convenient.

The production debugging pins of the hard disk on the current equipment are usually suspended and usually comprise 4 pins. If the embodiment of the invention adopts the hard disk production debugging pin as the hard disk state pin for outputting hard disk log data, the connector with corresponding number of pins can be adopted to connect the hard disk production debugging pin to the GPIO pin of the baseboard management controller chip or the I/O pin of the complex programmable logic device.

Since the free pins of the hard disk are usually only in the interface of the hard disk of the NVMe interface, the high-speed signal cannot be suspended, and the free pins of the hard disk in the present NVMe interface are grounded through a resistor-capacitor circuit on the hard disk backboard after the hard disk is connected to the hard disk backboard. If the embodiment of the invention adopts the hard disk idle pin as the hard disk state pin for outputting hard disk log data, the connection relation between the hard disk idle pin and the hard disk backboard is changed into the connection relation between the hard disk idle pin and the hard disk backboard and the connection relation is connected to the GPIO pin of the baseboard management controller chip or the I/O pin of the complex programmable logic device.

In an out-of-band system, if the hard disk expansion card has an integrated circuit bus connected to the baseboard management controller chip, the baseboard management controller chip can access the hard disk expansion card through the integrated circuit bus, and forward commands or hard disk log data to the hard disk through the hard disk expansion card. In addition, in the baseboard management controller, the baseboard management controller chip can be connected with the complex programmable logic device through the integrated circuit bus and then connected with the hard disk state pin of the hard disk through the complex programmable logic device. Or the baseboard management controller chip can also be directly connected with a hard disk state pin of the hard disk.

In a first aspect, the present application provides a clock detection method applied to a hard disk, as shown in fig. 1, where the hard disk is in single-wire communication with a baseboard management controller.

The single-wire communication refers to that there is only one transmission channel between the hard disk and the baseboard management controller, and the single-wire communication can be realized by a single-wire connection, wherein the single-wire connection refers to that there is only one transmission line (DATA) between the hard disk and the baseboard management controller, and the line can only provide one transmission channel for transmitting the state signal of the hard disk (GND in FIG. 1 is a ground line, and is not a transmission line). Unlike the way in which a bus is provided, but a clock line, a data line, etc. are included in the bus, a single line in the present application has only one line for transmitting a hard disk state signal, and does not include any other line.

As shown in fig. 2, the clock detection method includes:

S11: receiving a communication signal sent by a hard disk through a hard disk state pin, wherein the communication signal is a signal obtained by encoding the hard disk according to a data signal and a clock signal of the hard disk, and the data signal is a signal obtained by modulating the hard disk according to hard disk log data and the hard disk state signal corresponding to the hard disk state pin;

Specifically, the clock signal is a signal corresponding to a clock source for synchronizing transmission and processing of data in the hard disk, and the data signal is a signal modulated according to hard disk log data and a hard disk state signal corresponding to a hard disk state pin, and includes hard disk state information and data content corresponding to a current log. The clock signal and the data signal are then encoded in order to convert the original clock signal and data signal into a communication signal suitable for transmission over a single line transmission channel.

The reason why the hard disk needs to encode the clock signal and the data signal and then transmit the encoded clock signal and the data signal is that in the single-wire communication mode, clock calibration cannot be performed between the transmitting end and the receiving end (i.e., between the hard disk status pin of the hard disk and the baseboard management controller), and whether the data signal is transmitted based on a correct clock cannot be determined. By encoding the clock signal and the data signal, they can be combined into one communication signal for transmission, thereby satisfying signal transmission in a single-wire communication scene.

S12: analyzing the communication signal to obtain a clock signal and a data signal;

S13: and judging whether the clock of the hard disk is accurate or not based on the clock signal.

Specifically, at the baseboard management controller end, after receiving the communication signal, the communication signal is analyzed to obtain the clock signal and the data signal, and whether the clock of the hard disk is accurate or not is judged based on the clock signal, so that the detection of the clock signal can be realized in a single-wire communication mode, and the accuracy of data transmission is ensured.

The method for judging whether the clock of the hard disk is accurate according to the clock signal can comprise the following steps: firstly, standard clock signals are stored in the baseboard management controller, frequency comparison is carried out between the received clock signals and the standard clock signals stored in the baseboard management controller, and if the two clock frequencies are similar and stable, the clock of the hard disk can be judged to be accurate; secondly, it may also be: the baseboard management controller carries out stability evaluation on the received clock signals, and judges whether the clock of the hard disk is stable or not by counting the fluctuation condition of the clock signals within a certain time, thereby indirectly judging the accuracy of the clock.

In one embodiment, parsing the communication signal to obtain a clock signal and a data signal includes:

Analyzing the communication signals to obtain at least two sign signals and data to be transmitted; the data signal comprises data to be transmitted and a sign signal with a fixed pulse width, the sign signal is used for representing the current transmission progress of the data signal, and the hard disk encodes the current clock frequency into the sign signal;

and judging whether the clock of the hard disk is accurate or not according to the pulse width corresponding to the two mark signals.

Specifically, when transmitting data signals, along with effective data to be transmitted, a plurality of flag signals are usually transmitted together with the data to be transmitted, for example, the flag signals are flag bits for indicating that the data starts to be transmitted, flag bits for indicating that the data transmission ends, data check bits and the like, and are interspersed in the transmission process of the data to be transmitted, and the flag signals are usually endowed with fixed pulse width in a communication protocol. As shown in fig. 3, the data signal indicates a start flag bit for starting transmission of data, an end flag bit for indicating the end of transmission of data, and data to be transmitted (including a plurality of data bits) is located between the start flag bit and the end flag bit, and then the clock signal may be encoded using the start flag bit and the end flag bit.

Then adaptively, the process of parsing the communication signal by the baseboard management controller includes parsing the flag signal from the communication signal, wherein the flag signal should have a fixed pulse width when the clock of the hard disk is normal. Therefore, the process of the baseboard management controller judging whether the clock of the hard disk is accurate includes: judging whether the pulse width of the mark signal is a fixed pulse width, if the pulse width is not the fixed pulse width, indicating that the pulse width is changed, judging whether the change of the pulse width is larger than a threshold value, if the change degree is larger than the threshold value, considering that the clock of the hard disk is inaccurate, and if the pulse width is unchanged, the pulse width is still the fixed pulse width, or the change degree is within the threshold value range, considering that the clock of the hard disk is accurate.

Compared with the method of independently generating the clock signal, the method has the advantages that the clock signal and the sign signal are encoded, the accuracy of the hard disk clock can be accurately estimated, the inaccurate clock condition can be timely found and corrected, the system design can be simplified, more information can be transmitted in a limited channel in a single-wire communication mode, the requirement of additional lines is reduced, and the complexity and cost of the system are reduced.

Judging whether the pulse widths corresponding to the two mark signals are within a preset range of the standard pulse widths or judging whether the difference value between the pulse widths corresponding to the two mark signals is within an error range;

If the pulse widths corresponding to the two mark signals are within a preset range of the standard pulse widths, or the difference value is within an error range, judging that the clock of the hard disk is accurate;

if the pulse width corresponding to the two sign signals is not in the preset range of the standard pulse width or the difference value is not in the error range, the clock inaccuracy of the hard disk is judged.

In this embodiment, whether the clock of the hard disk is accurate is determined according to the pulse widths corresponding to the two flag signals. Specifically, whether the pulse widths corresponding to the two flag signals are within a preset range or not may be determined, and if the pulse widths corresponding to the two flag signals are within the preset range, it may be determined that the clock of the hard disk is accurate; in contrast, if the pulse widths corresponding to the two flag signals are not within the preset range, it can be determined that the clock of the hard disk is inaccurate. The method can also judge whether the difference value of the pulse widths corresponding to the two mark signals is in an error range, and if the difference value of the pulse widths corresponding to the two mark signals is in the error range, the clock of the hard disk can be judged to be accurate; if the difference value of the pulse widths corresponding to the two sign signals is not within the error range, the clock of the hard disk can be judged to be inaccurate.

Furthermore, the method for judging the clock based on the two sign signals is provided, if a certain time interval exists between the two sign signals, whether the clock drifts in the time interval can be determined by judging whether the difference value between the two sign signals is within the error range or not. By judging whether the pulse widths of the two sign signals are within the preset range of the standard pulse width, whether drift occurs between the clock and the standard clock can be determined. In another embodiment, the baseboard management controller may further determine whether the clock is accurate by using a flag signal, where the determining manner is: the base plate management controller stores the standard pulse width of a marking signal corresponding to a standard clock, and directly determines whether the clock is accurate or not by comparing the pulse width of the marking signal in the acquired and transmitted communication signal with the standard pulse width. The method for judging whether the clock of the hard disk is accurate or not is more suitable for a scene without the standard pulse width stored in the baseboard management controller by collecting whether the difference value of pulse widths corresponding to the two mark signals is in an error range or not, and whether the clock drifts or not in the process of transmitting data to be transmitted can be directly judged by collecting twice.

In a specific embodiment, two flag bits located before and after the data to be transmitted are generally selected as two flag signals for determining whether the clock of the hard disk is accurate or not, or a time interval between two flag signals for determining whether the clock of the hard disk is accurate or not is defined to be not less than a preset time interval, so as to determine whether a drift lamp or the like occurs in the clock within this time interval.

In conclusion, the judging method can effectively detect whether the clock of the hard disk is accurate or not, so that the accuracy and the stability of data transmission are ensured. By analyzing and judging the pulse width of the marking signal, the inaccurate condition of the hard disk clock can be found in time, and a reliable clock signal reference is provided for subsequent data processing and transmission. Therefore, data transmission errors caused by inaccurate clocks can be avoided, and the reliability and stability of the system are improved.

In one embodiment, the hard disk state pin outputs a control signal of a first level in a state that the hard disk is preset, a plurality of pulse signals of a second level with preset width are inserted into the control signal, so that the control signal is divided by the pulse signals to obtain pulse widths of the first level corresponding to each data bit one by one, the current clock frequency of the control signal is encoded into the pulse signals of the second level with the preset width, a communication signal is obtained according to the pulse signals of the second level with the preset width and the pulse widths of the first levels, the data signals comprise a plurality of data bits, and the second level is opposite to the first level;

Analyzing the communication signal to obtain a clock signal and a data signal, including:

analyzing the communication signals to obtain at least two pulse signals with second level and a plurality of pulse widths with first level;

and judging whether the clock of the hard disk is accurate or not based on the pulse signals of at least two second levels.

In one embodiment, determining whether the clock of the hard disk is accurate based on the at least two pulse signals of the second level includes:

Judging whether the width difference value of the pulse signals of the two second levels is in an error range or not;

If the clock is not in the error range, the clock inaccuracy of the hard disk is judged.

Specifically, when the hard disk state pin outputs a control signal of a first level when the hard disk is in a preset state, the process of modulating the hard disk state signal and the hard disk state data by the hard disk to obtain the first signal may include: under a preset state, a plurality of pulse signals with second levels with preset widths are inserted into the control signals, so that the control signals are divided by the pulse signals to obtain pulse widths of first levels corresponding to the data bits one by one, wherein the data signals comprise a plurality of data bits, and the second levels are opposite to the first levels. That is, by inserting pulse signals of opposite second levels into constant first levels, a plurality of pulse width signals of the first levels are obtained, and thus, the hard disk log data is modulated.

Under the condition, the clock signal of the communication signal can be encoded with a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain the communication signal, the communication signal not only comprises the clock signal, but also comprises the hard disk log data and corresponding hard disk state data, the accurate transmission of the clock signal and the data signal is ensured, and the transmission of the hard disk state signal, the hard disk log data and the clock signal can be realized through the hard disk state pins. Specifically, the clock signal is transmitted by using the pulse signal, and the pulse signal of the second level with a preset width is used as the dividing signal to obtain the pulse width of the first level corresponding to each data bit. When the clock of the hard disk is accurate, the width of each pulse signal output by the hard disk should be a preset width or be within the range of the preset width. If the clock of the hard disk is inaccurate, the width of each pulse signal output deviates from the range of the preset width.

Thus, the step of the baseboard management controller determining whether the clock of the hard disk is accurate based on the clock signal may include: firstly, analyzing a communication signal to obtain at least two pulse signals with a second level, judging whether the corresponding pulse width is in an error range based on the two pulse signals, and if so, determining that a clock does not drift in the data transmission process and the clock of a hard disk is accurate; otherwise, determining that the clock drifts in the data transmission process, and the clock of the hard disk is inaccurate, and correspondingly, the transmitted data signal is inaccurate.

Analyzing the communication signal to obtain a square wave signal and a data signal, wherein the square wave frequency of the square wave signal and the clock frequency of the hard disk are in a second mapping relation;

judging whether the clock of the hard disk is accurate or not based on the clock signal;

In this embodiment, when the square wave signal corresponding to the clock signal is regenerated and encoded with the data signal and transmitted to the baseboard management controller (the combination of the square wave signal and the data signal is as shown in fig. 4, the data signal includes a start flag bit indicating the start of data transmission, an end flag bit indicating the end of data transmission, and data to be transmitted (including a plurality of data bits), the square wave signal may be inserted before the first data bit and after the last data bit of the data to be transmitted.

After receiving the communication signal, the baseboard management controller analyzes the specific steps as follows: and analyzing the received communication signal to separate a square wave signal and a data signal. Through this step, the baseboard management controller can obtain the encoded clock signal and the data signal. And judging based on the square wave signals obtained through analysis to determine whether the clock of the hard disk is accurate. By analyzing the frequency and the characteristics of the square wave signal, the baseboard management controller can evaluate the accuracy of the hard disk clock, thereby correcting any clock error or drift in time and ensuring the accuracy and the stability of data transmission.

In this embodiment, the square wave signal is shown in fig. 5, and because the square wave signal is a signal with obvious high-low level variation, the square wave signal is easy to be analyzed by the baseboard management controller, and the clock signal can be restored by detecting the frequency and the characteristics of the square wave signal, so that the accuracy of clock information is ensured. In addition, compared with other signal coding modes, the frequency of the square wave signal is relatively quick, and information of a plurality of clock cycles can be transmitted in a short time, so that the data transmission efficiency is improved, and the communication bandwidth can be further effectively saved. Furthermore, as the high and low level of the square wave signal is obviously changed, the influence of noise and interference can be better resisted, the error rate is reduced, and the reliability of data transmission is improved.

if the frequency difference value is within the preset frequency range, judging that the clock of the hard disk is accurate;

if the frequency difference value is not in the preset frequency range, the inaccuracy of the clock of the hard disk is judged.

The embodiment describes specific steps of analyzing the communication signal by the baseboard management controller and conditions of judging the accuracy of the hard disk clock. Firstly, the baseboard management controller analyzes the communication signal to obtain at least two square wave signals and a first pulse width signal, wherein the baseboard management controller needs to analyze the communication signal and extract the square wave signals and the pulse width signals contained in the communication signal so as to facilitate the subsequent clock accuracy judgment. Secondly, the baseboard management controller needs to judge whether the frequency difference value between the two square wave signals is in a preset frequency range or not; in order to judge whether the clock frequency of the hard disk is stable, the clock frequency of the hard disk can be determined to be within an expected range by comparing the frequency difference value of the square wave signals. Finally, if the frequency difference value is within the preset frequency range, the baseboard management controller judges that the clock of the hard disk is accurate; if the frequency difference value is not in the preset frequency range, judging that the clock of the hard disk is inaccurate; and the final clock accuracy judgment is carried out according to the previous frequency difference judgment result, if the frequency difference is within the preset range, the clock of the hard disk is considered to be accurate, otherwise, the clock is considered to be inaccurate.

Further, after the baseboard management controller parses the square wave signal, the method for determining whether the clock of the hard disk is accurate based on the square wave signal may include the following steps: firstly, comparing the square wave frequency of the analyzed square wave signal with a square wave reference frequency pre-stored in a baseboard management controller, and judging whether the difference value between the square wave frequency and the square wave reference frequency is within a preset range; secondly, determining a clock frequency according to the square wave frequency of the analyzed square wave signal and a second mapping relation, comparing the clock frequency with a clock reference frequency pre-stored by a baseboard management controller, and judging whether the difference value between the clock frequency and the clock reference frequency is within a preset range; thirdly, analyzing at least two square wave signals, determining square wave frequencies of the two square wave signals, and judging whether a difference value between the two square wave frequencies is within a preset range or not so as to determine whether clock drift occurs in a time period between the two square wave signals or not; fourthly, analyzing at least two square wave signals, determining square wave frequencies of the two square wave signals, determining two clock frequencies according to the analyzed square wave frequencies of the square wave signals and a second mapping relation, and judging whether the difference value between the two clock frequencies is in a preset range or not so as to determine whether the clock drifts in a time period between the two square wave signals or not.

In summary, this embodiment describes how the baseboard management controller evaluates the clock accuracy of the hard disk by analyzing the square wave signal in the communication signal, and makes a judgment according to a preset standard. The design can effectively monitor and maintain the clock state of the hard disk, and ensure the normal operation of the system and the reliable transmission of data.

In one embodiment, further comprising:

and when the clock of the hard disk is inaccurate, a feedback signal is sent to the hard disk and/or the hard disk controller through the hard disk state pin, so that the hard disk retransmits a data signal or a communication signal.

In this embodiment, when the clock of the hard disk is inaccurate, the baseboard management controller sends a feedback signal to the hard disk through the hard disk status pin to trigger the hard disk to retransmit the data signal or the communication signal. Because there is only one single wire connection between the hard disk and the baseboard management controller, strict conventions are required to be made to the data transmission time to ensure accuracy and timeliness of communication. One method of specifying time is to preset a time window in the system, within which the hard disk transmits a data signal or a communication signal. The baseboard management controller sends a feedback signal within a preset time window after receiving the data signal or the communication signal. By the method for agreeing time, the hard disk and the baseboard management controller can communicate in the agreed time, and accuracy and timeliness of data transmission are ensured. The method can effectively improve the reliability and stability of data transmission and ensure the normal operation of the system.

Still further, in one embodiment, after the baseboard management controller determines that the clock of the hard disk is inaccurate, the method further includes: an error report is generated and fed back to the hard disk controller to cause the hard disk controller to switch the hard disk or adjust the clock source of the hard disk based on the error report.

Specifically, the baseboard management controller may also generate a detailed error report after determining that the hard disk clock is inaccurate, where the error report may include a specific deviation value of the clock, time, and the like. The error report is fed back to the hard disk controller as a reference in time.

The hard disk controller can select to switch the hard disk according to the information in the error report, for example, can select to switch to the standby hard disk so as to ensure the safety and the reliability of the data; specifically, before switching the hard disk, the data on the current hard disk needs to be completely backed up to the spare hard disk, then the spare hard disk is connected to the baseboard management controller, and the transmission of the data signal is performed again.

The hard disk controller may also adjust the clock source of the hard disk based on information in the error report, such as changing control parameters of the clock source of the hard disk, or synchronizing the internal clock of the hard disk via an external clock signal. When the clock is inaccurate, the clock source is adjusted, so that the normal operation of the hard disk can be ensured, the data loss or damage is avoided, and the stability and the reliability of the hard disk are effectively improved.

In a second aspect, as shown in fig. 6, the present application further provides a clock detection method applied to single-wire communication between a hard disk, a hard disk and a baseboard management controller, the clock detection method including:

S21: encoding a clock signal and a data signal of the hard disk drive to obtain a communication signal, wherein the data signal is a signal obtained by modulating a hard disk drive according to hard disk log data and a hard disk state signal corresponding to a hard disk state pin;

In a hard disk, first, a clock signal and a data signal of the hard disk need to be acquired. The clock signal is a signal corresponding to a clock source for synchronizing data transmission and processing in the hard disk, and the data signal is a signal modulated according to hard disk log data and a hard disk state signal corresponding to a hard disk state pin, and contains hard disk state information and data content corresponding to a current log. The clock signal and the data signal are then encoded in order to convert the original clock signal and data signal into a communication signal suitable for transmission over a single line transmission channel.

Specifically, the reason why the clock signal and the data signal need to be encoded and then transmitted is that in the single-wire communication mode, clock calibration cannot be performed between the transmitting end and the receiving end (i.e., between the hard disk status pin of the hard disk and the baseboard management controller), and it cannot be determined whether the data signal is transmitted based on a correct clock. The clock signal and the data signal are encoded and can be combined into one communication signal for transmission, so that the baseboard management controller can acquire the clock signal and the data signal by analyzing the communication signal and judge whether the clock of the hard disk is accurate or not based on the clock signal, the detection of the clock signal can be realized in a single-wire communication mode, and the accuracy of data transmission is ensured.

S22: and sending the communication signal to the baseboard management controller through the hard disk state pin so that the baseboard management controller analyzes the communication signal to obtain a clock signal and a data signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal.

Specifically, at the baseboard management controller end, after receiving the communication signal, analyzing the communication signal to obtain a clock signal and a data signal, judging the clock of the hard disk based on the clock signal to determine whether the clock of the hard disk is accurate, if the clock of the hard disk is accurate, judging that the data signal transmitted by the hard disk is also accurate, otherwise, judging that the data signal transmitted by the hard disk is inaccurate.

In summary, the clock detection method of the application can realize the transmission of the hard disk log data, the hard disk state signal and the clock signal through the hard disk state pin, and can calibrate the clock of the hard disk through encoding the clock signal and the data signal and analyzing the communication signal, thereby determining whether the data signal is transmitted based on the correct clock, finding out problems in time and ensuring the accuracy of the data signal transmission.

In one embodiment, the data signal includes a flag signal for representing a current transmission progress of the data signal, and the flag signal is used for encoding a clock signal of the flag signal and the data signal to obtain a communication signal, and the method includes:

Encoding the current clock frequency of the self into the sign signal;

integrating the marking signal and the data to be transmitted to obtain a communication signal;

The baseboard management controller analyzes the communication signal to obtain a clock signal and a data signal, and judges whether the clock of the hard disk is accurate based on the clock signal, comprising:

the base plate management controller analyzes the communication signals to obtain at least two sign signals and data to be transmitted;

The embodiment further details the composition and processing method of the data signal, and the analysis and clock accuracy judging method of the communication signal by the baseboard management controller. Specifically, when transmitting data signals, along with effective data to be transmitted, a plurality of flag signals are usually transmitted together with the data to be transmitted, for example, the flag signals are flag bits for indicating that the data starts to be transmitted, flag bits for indicating that the data transmission ends, data check bits and the like, and are interspersed in the transmission process of the data to be transmitted, and the flag signals are usually endowed with fixed pulse width in a communication protocol.

As shown in fig. 3, the data signal indicates a start flag bit for starting transmission of data, an end flag bit for ending transmission of data, and data to be transmitted (including a plurality of data bits) is located between the start flag bit and the end flag bit, and the clock signal may be encoded using the start flag bit and the end flag bit.

Specifically, if the data signal in the present application includes the data to be transmitted and the flag signal with a fixed pulse width, the communication signal including the clock frequency, the flag signal and the data to be transmitted can be generated by encoding the clock signal of the data signal and the flag signal in the data signal. Encoding the current clock frequency into the flag signal ensures that the clock information can be synchronized during data transmission. The flag signal and the data to be transmitted are integrated to form a complete communication signal for transmission to the baseboard management controller over a single line transmission channel. The baseboard management controller analyzes the received communication signals, acquires at least two sign signals and data to be transmitted, judges whether the clock of the hard disk is accurate according to pulse widths corresponding to the two sign signals, and can evaluate the accuracy of the clock of the hard disk by comparing the change condition of the pulse widths, thereby ensuring the accuracy and reliability of data transmission.

That is, in the present application, a flag signal is multiplexed, and this flag signal is not only used for characterizing the progress of data transmission or checking, etc., but also used for judging whether the clock is accurate. Specifically, the flag signal should be a fixed pulse width when the clock is normal, if the pulse width is changed and the degree of change is greater than the threshold value, the clock of the hard disk is considered to be inaccurate, if the pulse width is unchanged and still is a fixed pulse width, or the degree of change is within the threshold value range, the clock of the hard disk is considered to be accurate.

inserting a plurality of pulse signals with second levels with preset widths into the control signals, dividing the control signals by the pulse signals to obtain pulse widths of first levels corresponding to the data bits one by one, wherein the data signals comprise a plurality of data bits, and the second levels are opposite to the first levels;

And encoding the clock signal, a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain a communication signal.

Under the condition, the clock signal of the communication signal can be encoded with a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain the communication signal, the communication signal not only comprises the clock signal, but also comprises the hard disk log data and corresponding hard disk state data, the accurate transmission of the clock signal and the data signal is ensured, and the transmission of the hard disk state signal, the hard disk log data and the clock signal can be realized through the hard disk state pins.

Similarly, the process of analyzing the communication signal by the baseboard management controller includes: the clock signal of the hard disk, a plurality of pulse signals of the second level and a plurality of pulse widths of the first level are analyzed from the communication signal, and the clock of the hard disk is judged based on the clock signal.

In addition, the preset state may be an on-site state or an off-site state of the hard disk, and the method may also be utilized when the first level signal is continuously output in the preset state, and the implementation manner is the same, which is not described in detail herein.

In summary, in this embodiment, the hard disk status pin of the hard disk is used to implement transmission of the hard disk status signal and the hard disk log data at the hard disk end through modulation, so that the baseboard management controller analyzes the hard disk log data according to the data signal to monitor the hard disk; furthermore, the clock signal is modulated in the pulse signal in the hard disk log data, so that the clock signal is analyzed without a clock line, and the baseboard management controller can conveniently determine whether the clock of the hard disk is accurate according to the clock signal.

In one embodiment, encoding the clock signal of the communication device with a plurality of pulse signals of a second level and a plurality of pulse widths of a first level to obtain a communication signal includes:

Encoding the current clock frequency of the communication signal into a pulse signal with a second level of a preset width, wherein the clock frequency and the preset width form a first mapping relation, and the communication signal comprises a plurality of pulse signals with the second level of the preset width and a plurality of pulse widths with the first level;

The baseboard management controller analyzes the communication signals to obtain at least two pulse signals with second level and a plurality of pulse widths with first level;

In this embodiment, the flag signal with a fixed pulse width is a pulse signal with a second level with a preset width, and the clock signal and the data signal are encoded. That is, the clock signal is transferred using this pulse signal. Specifically, a pulse signal of a second level of a preset width is used as a divided signal to obtain pulse widths of a first level corresponding to each data bit. When the clock of the hard disk is accurate, the width of each pulse signal output by the hard disk should be a preset width or be within the range of the preset width. If the clock of the hard disk is inaccurate, the width of each pulse signal output deviates from the range of the preset width.

In summary, the application provides a specific implementation manner for transmitting hard disk log data by using a hard disk state pin of a hard disk, which can realize the transmission of the hard disk log data by using the original pin of the hard disk, and further the baseboard management controller can realize the monitoring of the hard disk based on the hard disk log data. Furthermore, the application also utilizes the modulation of the hard disk log data and the hard disk state signal to compile the clock signal, thereby realizing the transmission of the hard disk log data and the judgment of the clock by utilizing the hard disk state pin of the hard disk, and further improving the accuracy of transmitting the hard disk log data.

encoding the current clock frequency of the clock signal into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relation;

inserting the square wave signal into the data signal to obtain a communication signal;

the baseboard management controller analyzes the communication signals to obtain square wave signals and data signals, and judges whether the clock of the hard disk is accurate or not based on the square wave signals.

In the above embodiment, the clock signal and the flag signal with the fixed pulse width are encoded, so that the flag signal carries the clock signal, and further, based on the flag signal, whether the clock of the hard disk is accurate can be determined.

The present embodiment aims to provide a specific step of regenerating a square wave signal corresponding to a clock signal and encoding the square wave signal and a data signal together to be transferred to a baseboard management controller side. Specifically, in this embodiment, the specific steps of encoding the clock signal and the data signal of the present embodiment to obtain the communication signal include: the current clock frequency is encoded into a square wave signal, and the frequency of the square wave signal and the clock frequency are in a second mapping relation. This means that the frequency change of the square wave signal and the change of the clock frequency form a second mapping relation, so that the clock signal can be accurately restored at the baseboard management controller according to the square wave signal and the second mapping relation. Inserting the encoded square wave signal into a data signal to form a complete communication signal together with the data signal; in this way, the clock signal and the data signal are transmitted in combination, ensuring the synchronicity of the clock information and the data information.

In this embodiment, since the square wave signal is a signal with obvious high-low level variation, it is easy to analyze in the baseboard management controller, and the clock signal can be recovered by detecting the frequency and characteristics of the square wave signal, so as to ensure the accuracy of clock information. In addition, compared with other signal coding modes, the frequency of the square wave signal is relatively quick, and information of a plurality of clock cycles can be transmitted in a short time, so that the data transmission efficiency is improved, and the communication bandwidth can be further effectively saved. Furthermore, as the high and low level of the square wave signal is obviously changed, the influence of noise and interference can be better resisted, the error rate is reduced, and the reliability of data transmission is improved.

After the baseboard management controller parses out the square wave signal, the manner of judging whether the clock of the hard disk is accurate based on the square wave signal may include the following ways: firstly, comparing the square wave frequency of the analyzed square wave signal with a square wave reference frequency pre-stored in a baseboard management controller, and judging whether the difference value between the square wave frequency and the square wave reference frequency is within a preset range; secondly, determining a clock frequency according to the square wave frequency of the analyzed square wave signal and a second mapping relation, comparing the clock frequency with a clock reference frequency pre-stored by a baseboard management controller, and judging whether the difference value between the clock frequency and the clock reference frequency is within a preset range; thirdly, analyzing at least two square wave signals, determining square wave frequencies of the two square wave signals, and judging whether a difference value between the two square wave frequencies is within a preset range or not so as to determine whether clock drift occurs in a time period between the two square wave signals or not; fourthly, analyzing at least two square wave signals, determining square wave frequencies of the two square wave signals, determining two clock frequencies according to the analyzed square wave frequencies of the square wave signals and a second mapping relation, and judging whether the difference value between the two clock frequencies is in a preset range or not so as to determine whether the clock drifts in a time period between the two square wave signals or not.

Wherein the square wave reference frequency may be set to a single line communication protocol rate of a preset multiple, such as f=100×f, where F is the square wave reference frequency and F is the single line communication protocol rate.

The above are just several ways of determining whether the clock of the hard disk is accurate based on the square wave signal provided in the present embodiment, and the implementation manner is not limited thereto.

Encoding each data bit into pulse widths corresponding to the data bits one by one to obtain a first pulse width signal, wherein the data signal comprises a plurality of data bits, and the first pulse width signal comprises pulse widths corresponding to the plurality of data bits;

Encoding the square wave signal and the first pulse width signal to obtain a communication signal;

the baseboard management controller analyzes the communication signal to obtain a square wave signal and a first pulse width signal, and judges whether the clock of the hard disk is accurate or not based on the square wave signal.

The embodiment provides a specific implementation manner for encoding a clock signal and a data signal of a hard disk to obtain a communication signal. Specifically, the data signal is a signal modulated according to the hard disk log data and the hard disk state signal, and the clock signal is encoded into a square wave signal, wherein the frequency of the square wave signal and the clock frequency are in a second mapping relation, and the encoding mode is beneficial to retaining the information of the clock frequency in the transmission process, so that the baseboard management controller can restore the accurate clock signal. And sending the communication signal to the baseboard management controller through the hard disk state pin so that the baseboard management controller analyzes the communication signal to obtain a clock signal and a data signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal.

Further, the data signal is encoded in the following manner: encoding each data bit into a pulse width corresponding to the data bit one by one to obtain a first pulse width signal; the data signal comprises a plurality of data bits, and the first pulse width signal comprises pulse widths corresponding to the plurality of data bits; the coding mode can effectively convert the data bits into pulse width information, and is convenient for analysis and identification in the transmission process. The square wave signal and the data signal are encoded in such a way that: the square wave signal and the first pulse width signal are encoded to obtain a final communication signal, and the step integrates and encodes the clock signal and the data signal into a unified communication signal for transmission on a single-wire transmission channel. The baseboard management controller analyzes the received communication signals to obtain square wave signals and first pulse width signals, judges whether the clock of the hard disk is accurate or not (and/or analyzes data signals based on the first pulse width signals) based on the square wave signals, and can accurately evaluate the accuracy of the clock of the hard disk through analysis and judgment, so that the reliability and accuracy of data transmission are ensured.

In summary, the embodiment encodes the clock signal and the data signal of the hard disk and analyzes the encoded signals at the receiving end to determine whether the clock of the hard disk is accurate, thereby solving the problem that the clock calibration cannot be performed in the single-wire communication mode. Meanwhile, the method can be effectively applied to single-wire connection between the hard disk and the baseboard management controller, and the reliability and accuracy of communication are improved.

And respectively inserting at least two square wave signals before the pulse width corresponding to the first data bit and/or after the pulse width corresponding to the last data bit and/or between the pulse widths corresponding to any two data bits to obtain a communication signal.

In this embodiment, when the square wave signal and the first pulse width signal are encoded to obtain the communication signal, at least two square wave signals are specifically inserted into specific positions in the communication signal, for example, before a pulse width corresponding to a first data bit, after a pulse width corresponding to a last data bit, and between pulse widths corresponding to any two data bits.

The square wave signal is combined with the first pulse width signal to form an optimized communication signal structure. The optimized communication signal not only contains the original square wave signal and the first pulse width signal information, but also contains the additionally inserted square wave signal, so that the transmitted data is richer and more complete.

As shown in fig. 4, the data signal includes a start flag bit indicating the start of data transmission, an end flag bit indicating the end of data transmission, and data to be transmitted (including a plurality of data bits), and a square wave signal may be inserted before the first data bit and after the last data bit of the data to be transmitted, so that the accuracy of the clock signal during the whole transmission process of the data to be transmitted may be determined by judging whether the square wave signal drifts. The shape of the square wave signal is shown in fig. 5.

After receiving the communication signal, the baseboard management controller can effectively analyze the square wave signal and the first pulse width signal, and judge the clock accuracy of the hard disk according to the information. The baseboard management controller more accurately evaluates the accuracy of the hard disk clock, thereby improving the stability and reliability of the whole system.

In a preferred embodiment, the time interval between the insertion positions of the two square wave signals is not less than a preset time interval, or the number of data bits separated between the insertion positions of the two square wave signals is not less than a preset number, so as to determine whether the clock signal drifts in the time period between the two square wave signals.

In conclusion, the embodiment further perfects the encoding and analysis processes of the communication signals in the hard disk clock detection method, improves the evaluation capability of the system on the clock accuracy, and simultaneously enhances the reliability and stability of data transmission.

In one embodiment, encoding each data bit into a pulse width corresponding to the data bit one to obtain a first pulse width signal includes:

and encoding each data bit into a pulse width with a duty ratio corresponding to the data bit one by one to obtain a first pulse width signal, wherein the duty ratio and the data bit are in a third mapping relation.

This embodiment describes the step of encoding each data bit into a pulse width that corresponds to the data bit one-to-one. Specifically, if each data bit is hexadecimal in number, that is, 16 different pulse widths are set, sixteen numbers in hexadecimal such as 0, 1, 2,3, 4,5,6,7, 8, 9, A, B, C, D, E, F, etc. can be corresponding. Then, each hexadecimal code is corresponded to the pulse width of one specific duty cycle, namely, the pulse width of 0 corresponds to one specific duty cycle, the pulse width of 1 corresponds to the other duty cycle, and the like (the pulse widths of different duty cycles correspond to different data bits in hexadecimal), and the combination of all pulse widths is the first pulse width signal. Through the encoding steps, each data bit is encoded into a pulse width signal corresponding to the data bit one by one, and the data transmission is realized through the change of the duty ratio. The baseboard management controller end can obtain corresponding data bits by analyzing the duty ratio, so that hard disk log data can be obtained, and the monitoring of the hard disk is realized.

For example, the hard disk state pin is an indicator lamp pin of the hard disk, and when the indicator lamp is in a non-preset state, the indicator lamp can flash by using the coding mode in the embodiment, and the coding mode still presents a pulse width signal with a duty ratio, so that the function of flashing the indicator lamp can be realized.

In summary, the present application can encode the hard disk log data and the hard disk status signal by the encoding method, and output the hard disk log data and the hard disk status signal to the baseboard management controller end through the hard disk status pin, so that the baseboard management controller can analyze the data, and acquire the hard disk log data and the hard disk status signal through the hard disk status pin.

And encoding each data bit into a pulse width of a preset level corresponding to the data bit, and obtaining a first pulse width signal, wherein the pulse width of the preset level and the data bit are in a fourth mapping relation.

Specifically, in this embodiment, each data bit is encoded into a pulse width of a preset level corresponding to the data bit one by one, so as to obtain a first pulse width signal. The specific steps may include: the number of data bits to be encoded is first determined, for example, each data bit of the hard disk log data is hexadecimal in digital system, that is, 16 different pulse widths are set, and sixteen numbers in hexadecimal systems such as 0, 1,2, 3,4, 5, 6, 7, 8, 9, A, B, C, D, E, F and the like can be corresponding. For example, in a rectangular wave signal with a period of 100 milliseconds, pulse widths of 42 milliseconds to 49 milliseconds and 51 milliseconds to 58 milliseconds can be designed, and one hexadecimal data corresponds to every 1 millisecond, namely 16 pulse widths correspond to sixteen numbers in hexadecimal; according to specific requirements, determining a pulse width coding mode corresponding to each data bit, coding each data bit one by one, wherein pulse width signals with high level or low level alternately appear, for example, coding data 0 into high level with a first width, coding data 1 into low level with a second width, and the like; each of the encoded data bits are combined to form a complete pulse width signal for subsequent transmission or processing.

Alternatively, the data bits may be all encoded to a high level of a corresponding width or all encoded to a low level of a corresponding width, and the data bits may be spaced by inserting opposite levels into adjacent two data bits; for example, 0 is encoded as a first pulse width, 1 is encoded as a second pulse width, 2 is encoded as a third pulse width, and 3 is encoded as a fourth pulse width. If the first to fourth pulse widths are high, inserting a low level of a certain width (for spacing two data bits) between two adjacent data bits; if the first to fourth pulse widths are low, a high level of a certain width (for spacing two data bits) is inserted between two adjacent data bits. The combination of data bits is not limited to the above, nor is the encoding scheme limited to the above examples.

For example, the hard disk state pin is an indicator lamp pin of the hard disk, and when the indicator lamp is in a non-preset state, the indicator lamp can flash by using the coding mode in the embodiment, and the coding mode still presents a pulse width signal formed by combining high and low levels, so that the function of flashing the indicator lamp can be realized. At this time, the square wave reference frequency is set to f=1/|t1-t2|, where t1 and t2 are pulse widths of two adjacent data bits, and f is the square wave reference frequency.

In summary, through the above encoding steps, each data bit may be encoded into a corresponding pulse width signal, so as to implement data transmission and processing.

In one embodiment, further comprising:

In this embodiment, once the baseboard management controller determines that the hard disk clock is inaccurate, it sends a feedback signal. Then, based on this feedback signal, the data signal or the communication signal is retransmitted. The process can ensure that the clock of the hard disk is calibrated in time, thereby ensuring the accuracy and stability of data transmission. In this example, the baseboard management controller plays an important role, and can timely detect the accuracy of the hard disk clock and send out corresponding feedback signals. After receiving the feedback signal, the system can retransmit the data signal or the communication signal according to the situation so as to ensure that the accuracy of the hard disk clock is adjusted. Therefore, even if the hard disk clock deviates, the calibration and correction can be performed in time through the baseboard management controller, and the accuracy and stability of data transmission are ensured.

Because the hard disk and the baseboard management controller are connected by a single wire, the time for transmitting data can be pre-agreed, and the baseboard management controller transmits a feedback signal within a preset time. One method of appointing time is to preset a time window in the system, and the hard disk sends data signals or communication signals in the time window. The baseboard management controller sends a feedback signal within a preset time window after receiving the data signal or the communication signal. Therefore, the hard disk and the baseboard management controller can communicate in a contracted time, and accuracy and timeliness of data transmission are ensured.

In summary, the accuracy of the hard disk clock and the stability of data transmission can be effectively ensured by the mode of the embodiment.

In a specific embodiment, the flow at the transmitting end (hard disk end) is as shown in fig. 7:

S71: starting; s72: sending a communication request; s73: transmitting a clock signal; s74: transmitting a data signal; s75: transmitting a clock signal; s76: transmitting a data end mark; s77: waiting for a check qualification signal fed back by the substrate management controller; s78: whether a check qualification signal is received or not; if yes, go to S710, otherwise go to S79; s79: retransmitting the data signal; s710: and (5) ending.

The flow at the receiving end (baseboard management controller end) is as shown in fig. 8:

S81: starting; s82: detecting a communication request signal; s83: recording a clock signal; s84: receiving a data signal and performing data analysis processing; s85: recording a clock signal; s86: receiving a data end mark; s87: comparing errors of the two clock signals; s88: whether the error is within a preset range; if yes, go to S89, otherwise go to S810; s89: sending a check qualification signal; s810: and sending a verification failure signal.

In a third aspect, the present application also provides a clock detection system, as shown in fig. 9, for single-wire communication between a hard disk and a baseboard management controller, the clock detection system comprising:

The encoding unit 91 is configured to encode a clock signal and a data signal of the encoding unit to obtain a communication signal, where the data signal is a signal obtained by modulating a hard disk according to hard disk log data and a hard disk state signal corresponding to a hard disk state pin;

The sending unit 92 is configured to send the communication signal to the baseboard management controller through the hard disk status pin, so that the baseboard management controller analyzes the communication signal to obtain a clock signal and a data signal, and determine whether the clock of the hard disk is accurate based on the clock signal.

In one embodiment, the data signal includes a flag signal for representing a current transmission progress of the data signal, and the encoding unit 91 includes:

the first coding unit is used for coding the current clock frequency of the first coding unit into the mark signal;

The integration unit is used for integrating the marking signal and the data to be transmitted to obtain a communication signal;

In one embodiment, the hard disk state pin outputs a control signal of a first level when the hard disk is in a preset state; the encoding unit 91 includes:

The pulse inserting unit is used for inserting a plurality of pulse signals with second levels with preset widths into the control signals so as to divide the control signals by utilizing the pulse signals to obtain pulse widths of first levels corresponding to the data bits one by one, wherein the data signals comprise a plurality of data bits, and the second levels are opposite to the first levels;

and the second coding unit is used for coding the clock signal of the second coding unit, a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain a communication signal.

In one embodiment, the second encoding unit is specifically configured to encode a current clock frequency of the second encoding unit into a pulse signal with a second level of a preset width, where the clock frequency and the preset width form a first mapping relationship, and the communication signal includes a plurality of pulse signals with the second level of the preset width and a plurality of pulse widths with the first level;

In one embodiment, the encoding unit 91 includes:

The third coding unit is used for coding the current clock frequency of the third coding unit into a square wave signal, and the frequency of the square wave signal and the clock frequency are in a second mapping relation;

The square wave inserting unit is used for inserting the square wave signal into the data signal to obtain a communication signal;

In one embodiment, the encoding unit 91 includes:

The fourth coding unit is used for coding each data bit into pulse widths corresponding to the data bits one by one to obtain a first pulse width signal, wherein the data signal comprises a plurality of data bits, and the first pulse width signal comprises pulse widths corresponding to the plurality of data bits;

The fifth coding unit is used for coding the square wave signal and the first pulse width signal to obtain a communication signal;

In one embodiment, the fifth encoding unit is specifically configured to insert at least two square wave signals before the pulse width corresponding to the first data bit and/or after the pulse width corresponding to the last data bit and/or between the pulse widths corresponding to any two data bits, respectively, so as to obtain the communication signal.

In one embodiment, the fourth encoding unit is specifically configured to encode each data bit into a pulse width with a duty ratio corresponding to the data bit one to one, so as to obtain a first pulse width signal, where the duty ratio and the data bit are in a third mapping relationship.

In one embodiment, the fourth encoding unit is specifically configured to encode each data bit into a pulse width of a preset level corresponding to the data bit, so as to obtain a first pulse width signal, where the pulse width of the preset level and the data bit are in a fourth mapping relationship.

In one embodiment, further comprising:

The feedback unit is used for receiving a feedback signal sent by the baseboard management controller after the baseboard management controller judges that the clock of the hard disk is inaccurate;

For the description of the clock detection system, please refer to the above embodiment, and the description of the present application is omitted herein.

In a fourth aspect, the present application also provides a clock detection system, as shown in fig. 10, applied to a baseboard management controller, where the baseboard management controller communicates with a hard disk in a single line, the clock detection system includes:

A receiving unit 101, configured to receive a communication signal sent by the hard disk through a hard disk status pin, where the hard disk encodes a signal obtained by encoding a data signal and a clock signal thereof during the communication signal;

the parsing unit 102 is configured to parse the communication signal to obtain a clock signal and a data signal;

And a judging unit 103 for judging whether the clock of the hard disk is accurate based on the clock signal.

In one embodiment, the parsing unit 102 is specifically configured to parse the communication signal to obtain at least two flag signals and data to be transmitted; the data signal comprises data to be transmitted and a sign signal with a fixed pulse width, the sign signal is used for representing the current transmission progress of the data signal, and the hard disk encodes the current clock frequency into the sign signal;

the judging unit 103 is specifically configured to judge whether the clock of the hard disk is accurate according to the pulse widths corresponding to the two flag signals.

In one embodiment, the judging unit 103 is specifically configured to judge whether the pulse widths corresponding to the two flag signals are within a preset range of the standard pulse widths, or whether the difference between the pulse widths corresponding to the two flag signals is within an error range; if the pulse widths corresponding to the two mark signals are within a preset range of the standard pulse widths, or the difference value is within an error range, judging that the clock of the hard disk is accurate; if the pulse width corresponding to the two sign signals is not in the preset range of the standard pulse width or the difference value is not in the error range, the clock inaccuracy of the hard disk is judged.

The analyzing unit 102 is specifically configured to analyze the communication signal to obtain at least two pulse signals of a second level and a plurality of pulse widths of a first level;

The judging unit 103 is specifically configured to judge whether the clock of the hard disk is accurate based on the pulse signals of at least two second levels.

In one embodiment, the judging unit 103 is specifically configured to judge whether the difference between the widths of the pulse signals of the two second levels is within the error range; if the clock is within the error range, judging that the clock of the hard disk is accurate; if the clock is not in the error range, the clock inaccuracy of the hard disk is judged.

In one embodiment, the parsing unit 102 is specifically configured to parse the communication signal to obtain a square wave signal and a data signal, where a square wave frequency of the square wave signal and a clock frequency of the hard disk are in a second mapping relationship;

the judging unit 103 is specifically configured to judge whether the clock of the hard disk is accurate based on the square wave signal.

In one embodiment, the determining unit 103 is specifically configured to determine that the frequency difference between the two square wave signals is within a preset frequency range; if the frequency difference value is within the preset frequency range, judging that the clock of the hard disk is accurate; if the frequency difference value is not in the preset frequency range, the inaccuracy of the clock of the hard disk is judged.

In one embodiment, further comprising:

and the feedback sending unit is used for sending a feedback signal to the hard disk through the hard disk state pin when the clock of the hard disk is inaccurate, so as to trigger the hard disk to retransmit a data signal or a communication signal.

In a fifth aspect, the present application further provides an electronic device, as shown in fig. 11, including:

A memory 111 for storing a computer program;

The processor 112 is configured to implement the steps of the clock detection method as described above when executing the computer program.

For the description of the electronic device, please refer to the above embodiment, and the description of the present application is omitted herein.

In a sixth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a clock detection method as described above.

For the description of the computer-readable storage medium, refer to the above embodiments, and the disclosure is not repeated here.

In a seventh aspect, the present application further provides a server, including a hard disk and a baseboard management controller, where the hard disk is connected with the baseboard management controller by a single wire, and there is only one transmission channel between the hard disk and the baseboard management controller by the single wire;

The hard disk is used for realizing the step of the clock detection method applied to the hard disk;

the baseboard management controller is used for realizing the steps of the clock detection method applied to the baseboard management controller.

For the description of the server, refer to the above embodiment, and the description of the present application is omitted herein.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock detection method applied to a baseboard management controller, wherein the baseboard management controller communicates with a hard disk in a single line, the clock detection method comprising:

analyzing the communication signals to obtain at least two sign signals and data to be transmitted; the data signal comprises the data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used for representing the current transmission progress of the data signal, and the hard disk encodes the current clock frequency into the flag signal;

Judging whether the clock of the hard disk is accurate or not according to pulse widths corresponding to the two marking signals;

The hard disk state pin outputs a control signal of a first level in a state that the hard disk is preset, a plurality of pulse signals of a second level with preset width are inserted into the control signal, the control signal is divided by the pulse signals to obtain pulse widths of the first level corresponding to each data bit one by one, the current clock frequency of the control signal is encoded into the pulse signals of the second level with the preset width, the communication signals are obtained according to the pulse signals of the second level with the preset width and the pulse widths of the first level, and the data signals comprise a plurality of data bits, and the second level is opposite to the first level;

2. The method for detecting a clock according to claim 1, wherein determining whether the clock of the hard disk is accurate according to pulse widths corresponding to the two flag signals comprises:

3. The clock detection method of claim 1, wherein determining whether the clock of the hard disk is accurate based on at least two of the pulse signals of the second level comprises:

4. The clock detection method of claim 1, wherein parsing the communication signal to obtain the clock signal and the data signal comprises:

5. The method of claim 4, wherein determining whether the clock of the hard disk is accurate based on the square wave signal comprises:

6. The clock detection method as recited in any one of claims 1-5, further comprising:

7. A clock detection method applied to a hard disk, wherein the hard disk is in single-wire communication with a baseboard management controller, the clock detection method comprising:

The communication signal is sent to the baseboard management controller through a hard disk state pin, so that the baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and whether the clock of the hard disk is accurate or not is judged based on the clock signal;

The data signal comprises data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used for representing the current transmission progress of the data signal, and the clock signal and the data signal of the data signal are encoded to obtain a communication signal, and the method comprises the following steps:

Encoding the current clock frequency of the self into the sign signal;

The hard disk state pin outputs a control signal of a first level when the hard disk is in a preset state; encoding the clock signal and the data signal of the self to obtain a communication signal, including:

Under the preset state, a plurality of pulse signals with preset widths and second levels are inserted into the control signals, so that the control signals are divided by the pulse signals, and pulse widths of the first levels, which are in one-to-one correspondence with the data bits, are obtained; the data signal includes a plurality of the data bits, the second level being opposite the first level;

the current clock frequency of the communication signal is encoded into a pulse signal with a second level of the preset width, a first mapping relation is formed between the clock frequency and the preset width, and the communication signal comprises a plurality of pulse signals with the second level of the preset width and a plurality of pulse widths with the first level.

8. The method of claim 7, wherein the baseboard management controller analyzing the communication signal to obtain the clock signal and the data signal, and determining whether the clock of the hard disk is accurate based on the clock signal, comprises:

9. The clock detection method of claim 7, wherein encoding the own clock signal and data signal to obtain the communication signal comprises:

10. The clock detection method of claim 7, wherein encoding the own clock signal and data signal to obtain the communication signal comprises:

11. The clock detection method of claim 10, wherein encoding the square wave signal and the first pulse width signal to obtain the communication signal comprises:

12. The clock detection method of claim 10, wherein encoding each data bit into a pulse width corresponding to the data bit one to obtain a first pulse width signal, comprises:

13. The clock detection method of claim 10, wherein encoding each data bit into a pulse width corresponding to the data bit one to obtain a first pulse width signal, comprises:

14. The clock detection method as recited in any one of claims 7-13, further comprising:

15. A clock detection system for use with a baseboard management controller in single-wire communication with a hard disk, the clock detection system comprising:

a judging unit, configured to judge whether the clock of the hard disk is accurate based on the clock signal;

The analyzing unit is specifically used for analyzing the communication signals to obtain at least two sign signals and data to be transmitted; the data signal comprises the data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used for representing the current transmission progress of the data signal, and the hard disk encodes the current clock frequency into the flag signal;

The judging unit is specifically used for judging whether the clock of the hard disk is accurate or not according to pulse widths corresponding to the two marking signals;

The analysis unit is specifically used for analyzing the communication signals to obtain at least two pulse signals with the second level and a plurality of pulse widths with the first level;

and the judging unit is specifically used for judging whether the clock of the hard disk is accurate or not based on at least two pulse signals with the second level.

16. A clock detection system for single-wire communication between a hard disk and a baseboard management controller, the clock detection system comprising:

The sending unit is used for sending the communication signal to the baseboard management controller through a hard disk state pin so that the baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and judging whether the clock of the hard disk is accurate or not based on the clock signal;

The data signal comprises data to be transmitted and a flag signal with fixed pulse width, the flag signal is used for representing the current transmission progress of the data signal, and the coding unit comprises:

the integrating unit is used for integrating the marking signal and the data to be transmitted to obtain the communication signal;

The hard disk state pin outputs a control signal of a first level when the hard disk is in a preset state; an encoding unit comprising:

the second coding unit is used for coding the current clock frequency of the communication signal into a pulse signal with a second level of the preset width, wherein the clock frequency and the preset width form a first mapping relation, and the communication signal comprises a plurality of pulse signals with the second level of the preset width and a plurality of pulse widths with the first level.

17. An electronic device, comprising:

A memory for storing a computer program;

Processor for implementing the steps of the clock detection method according to any one of claims 1-6 or the steps of the clock detection method according to any one of claims 7-14 when executing the computer program.

18. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the clock detection method according to any of claims 1-6 or the steps of the clock detection method according to any of claims 7-14.

19. The server is characterized by comprising a hard disk and a baseboard management controller, wherein the hard disk is connected with the baseboard management controller in a single line, and only one transmission channel is arranged between the hard disk and the baseboard management controller through the single line;

The baseboard management controller is configured to implement the steps of the clock detection method according to any one of claims 1 to 6, and the hard disk is configured to implement the steps of the clock detection method according to any one of claims 7 to 14.