CN117970686A

CN117970686A - Display panel and display device

Info

Publication number: CN117970686A
Application number: CN202410390248.7A
Authority: CN
Inventors: 蓝天; 李泽尧; 崔见玉; 朱先飞; 叶利丹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2024-04-02
Filing date: 2024-04-02
Publication date: 2024-05-03
Anticipated expiration: 2044-04-02
Also published as: CN117970686B

Abstract

The application provides a display panel and a display device. According to the embodiment of the application, the display switch in the first pixel unit and the black inserting switch in the second pixel unit are coupled with the same first grid line in each row of pixel units, and the black inserting switch in the first pixel unit and the display switch in the second pixel unit are coupled with the same second grid line, so that the grid lines (namely, the first grid line or the second grid line) in the embodiment of the application can be used as the display grid lines and the black inserting grid lines at the same time, the number of the grid lines can be reduced, the number of driving units for driving the grid lines can be reduced, and the design of narrow frames is facilitated on the basis of realizing black inserting display.

Description

Display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In order to solve the problem of smear phenomenon when a display panel switches dynamic pictures, black insertion is generally performed in a display gap of a frame of picture to finish initialization before displaying a next frame of picture, so as to reduce or eliminate visual residues of human eyes on a previous frame of display picture, thereby achieving the purposes of eliminating smear, improving dynamic definition, improving dynamic response and the like, and improving the dynamic display quality of an LCD (Liquid CRYSTAL DISPLAY).

On the basis of the existing display panel, in order to realize the self-black insertion technology, a double Gate (Gate electrode) wiring is needed, half of the wiring is used for display scanning driving, and the newly added half of the wiring is used for black insertion scanning driving.

Disclosure of Invention

The application mainly solves the technical problem of providing a display panel and a display device, and solves the problem that the self-black-inserting technology is not beneficial to realizing a narrow frame in the prior art.

In order to solve the technical problems, the first technical scheme provided by the application is as follows: provided is a display panel including:

the pixel units are arranged in an array manner, and the pixel units in each row of pixel units are respectively defined as a first pixel unit and a second pixel unit; each pixel unit comprises a display switch and a black insertion switch;

a gate line group including a first gate line and a second gate line; each grid line group is arranged corresponding to a row of pixel units and is electrically connected with the pixel units;

in each row of pixel units, a display switch in a first pixel unit and a black inserting switch in a second pixel unit are coupled with the same first gate line, and the black inserting switch in the first pixel unit and the display switch in the second pixel unit are coupled with the same second gate line.

In each pixel unit, the display switches and the black inserting switches are distributed along the column direction of the pixel unit, or the display switches and the black inserting switches are distributed along the row direction of the pixel unit; the distribution directions of the display switch and the black inserting switch in the first pixel unit are opposite to the distribution directions of the display switch and the black inserting switch in the second pixel unit.

The display panel further comprises at least one scanning driving circuit, wherein the scanning driving circuit is used for scanning the first gate lines line by line; and/or the scanning driving circuit is used for scanning the second gate lines line by line; the scanning driving circuit scans m rows of first gate lines at the same time;

In the first grid lines of the multiple rows, the working time sequence of the first grid line of the (m+i) th row lags behind the working time sequence of the first grid line of the (i) th row, and the lag time is a preset time length;

in the same gate line group, the working time sequence of the second gate line lags behind the working time sequence of the first gate line, and the lag time is n times of preset time length;

wherein n is greater than 1 and is an odd number, m is greater than or equal to 1, and i is greater than or equal to 1.

In the same gate line group, the working time sequence of the second gate line lags the working time sequence of the first gate line, and the lag time length is at least half frame time.

The display panel further comprises a data line, and the pixel unit further comprises a pixel electrode, a pixel capacitor, a storage capacitor, a color film substrate side common electrode and an array substrate side common electrode; the input end of the display switch is electrically connected with the data line, the output end of the display switch is electrically connected with the pixel electrode, and the control end of the display switch is electrically connected with one of the first gate line and the second gate line in the corresponding gate line group; the input end of the black inserting switch is electrically connected with the pixel electrode, the output end of the black inserting switch is electrically connected with the common electrode at the side of the array substrate, and the control end of the black inserting switch is electrically connected with the other one of the first gate line and the second gate line in the corresponding gate line group; one end of the pixel capacitor is electrically connected with the pixel electrode, and the other end of the pixel capacitor is electrically connected with the common electrode on the color film substrate side; one end of the storage capacitor is electrically connected with the pixel electrode, and the other end of the storage capacitor is electrically connected with the common electrode on the side of the array substrate.

The display panel also comprises a data line and a plurality of pixel groups, wherein the pixel groups comprise a first pixel unit and a second pixel unit which are adjacent and arranged side by side; the pixel groups are repeatedly arranged along the row direction of the pixel units and are repeatedly arranged along the column direction of the pixel units; the first pixel units and the second pixel units which are positioned in different pixel groups and are adjacently arranged share the same data line.

The polarity distribution pattern of the pixel electrodes of the pixel units in the display panel comprises at least one of column inversion, row inversion, single-point inversion, multi-point inversion and frame inversion.

The display panel further comprises a data line and a plurality of pixel groups; the pixel groups are repeatedly arranged along the row direction of the pixel units and are repeatedly arranged along the column direction of the pixel units; the pixel group comprises a first pixel group and a second pixel group which are sequentially arranged side by side, the first pixel group comprises a plurality of first pixel units arranged side by side, the second pixel group comprises a plurality of second pixel units arranged side by side, and the first pixel units in the first pixel group are arranged in one-to-one correspondence with the second pixel units in the second pixel group; in the pixel groups, the data lines connected with the first pixel units in the first pixel group are electrically connected with the data lines connected with the corresponding second pixel units in the second pixel group.

In each column of pixel units, the polarities of the pixel electrodes of the pixel units are the same; in each row of pixel units, the polarities of the pixel electrodes of two adjacent pixel units are opposite; the pixel units electrically connected with the data lines are the same in corresponding pixel colors.

In order to solve the technical problems, a second technical scheme provided by the application is as follows: a display device is provided, wherein the display device comprises a main board and the display panel.

The application has the beneficial effects that: the application provides a display panel and a display device, wherein the display panel comprises a plurality of pixel units and grid line groups which are arranged in an array manner. The plurality of pixel units in each row of pixel units are respectively defined as a first pixel unit and a second pixel unit. Each pixel unit includes a display switch and a black insertion switch. The gate line group includes a first gate line and a second gate line. Each gate line group is arranged corresponding to a row of pixel units and is electrically connected. In each row of pixel units, a display switch in a first pixel unit and a black inserting switch in a second pixel unit are coupled with the same first gate line, and the black inserting switch in the first pixel unit and the display switch in the second pixel unit are coupled with the same second gate line. According to the embodiment of the application, the display switch in the first pixel unit and the black inserting switch in the second pixel unit are coupled with the same first grid line in each row of pixel units, and the black inserting switch in the first pixel unit and the display switch in the second pixel unit are coupled with the same second grid line, so that the grid lines (namely, the first grid line or the second grid line) in the embodiment of the application can be used as the display grid lines and the black inserting grid lines at the same time, the number of the grid lines can be reduced, the number of driving units for driving the grid lines can be reduced, and the design of narrow frames is facilitated on the basis of realizing black inserting display.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without any inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a first embodiment of a display panel according to the present application;

FIG. 2 is a schematic diagram of a connection structure of an embodiment of a pixel unit according to the present application;

fig. 3 is a schematic structural diagram of a second embodiment of a display panel according to the present application;

FIG. 4 is a timing diagram of an embodiment of a signal line according to the present application;

FIG. 5 is a timing diagram of one embodiment of a gate line according to the present application;

fig. 6 is a schematic structural diagram of a third embodiment of a display panel according to the present application;

FIG. 7 is a schematic diagram of a display panel according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an embodiment of a display device provided by the present application.

Reference numerals illustrate:

100. A display panel; 10. a pixel unit; 11. a first pixel unit; 12. a second pixel unit; t1, a display switch; t2, a black inserting switch; clc, pixel capacitance; cst, storage capacitor; p, pixel electrode; a-com, an array substrate side common electrode; CF-com, color film substrate side common electrode; 13. a pixel group; 131. a first pixel group; 132. a second pixel group; 20. a gate line group; gate1/Gate 1-2/Gate1-3/Gate1-4, a first Gate line; gate2/Gate2-1/Gate2-2/Gate2-3/Gate2-4, a second Gate line; 30. a scan driving circuit; 31. a first driving circuit; 32. a second driving circuit; data, data lines; STV, frame start signal line; STV1, first frame start signal line; STV2, second frame start signal line; CK. A clock signal line; CK1, a first clock signal line; CK2, a second clock signal line; CK3, a third clock signal line; CK4, fourth clock signal line; t, presetting time length; 200. a main board; 300. a display device; r, red; G. green; B. blue.

Detailed Description

The following describes embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a first embodiment of a display panel according to the present application, and fig. 2 is a schematic structural diagram of a connection structure of an embodiment of a pixel unit according to the present application.

The present application provides a display panel 100. The display panel 100 includes a plurality of pixel units 10 and gate line groups 20 arranged in an array. The plurality of pixel units 10 in each row of pixel units 10 are defined as a first pixel unit 11 and a second pixel unit 12, respectively. Each pixel unit 10 includes a display switch T1 and a black insertion switch T2. The Gate line group 20 includes a first Gate line Gate1 and a second Gate line Gate2. Each gate line group 20 is disposed and electrically connected to a row of pixel cells 10. In each row of pixel units 10, the display switch T1 in the first pixel unit 11 and the black inserting switch T2 in the second pixel unit 12 are coupled to the same first Gate line Gate1, and the black inserting switch T2 in the first pixel unit 11 and the display switch T1 in the second pixel unit 12 are coupled to the same second Gate line Gate2.

In the embodiment of the application, in each row of pixel units 10, the display switch T1 in the first pixel unit 11 and the black inserting switch T2 in the second pixel unit 12 are coupled to the same first Gate line Gate1, and the black inserting switch T2 in the first pixel unit 11 and the display switch T1 in the second pixel unit 12 are coupled to the same second Gate line Gate2, so that the Gate lines (i.e., the first Gate line Gate1 or the second Gate line Gate 2) in the embodiment of the application can be used as the display Gate lines and the black inserting Gate lines at the same time, and the number of Gate lines can be reduced without adding a new double of Gate lines for black inserting display, thereby reducing the number of driving units for driving the Gate lines, and being beneficial to realizing narrow frame design on the basis of realizing black inserting display.

Specifically, in the prior art, the display panel 100 using the black insertion technology generally includes double gate lines, one half of which is used for electrically connecting with the display switch T1 of the pixel unit 10 to control the pixel unit 10 to display a normal picture, and the other half of which is used for electrically connecting with the black insertion switch T2 of the pixel unit 10 to control the pixel unit 10 to display a black picture, so as to implement black insertion display. That is, in the prior art, the display panel 100 needs to increase the number of driving units driving the gate lines by one time, which is not beneficial to the design of the narrow frame. In the embodiment of the application, the first Gate line Gate1 and the second Gate line Gate2 are electrically connected with the display switch T1 of a part of the pixel units 10 and also electrically connected with the black inserting switch T2 of a part of the pixel units 10, so that in each row of the pixel units 10, a part of the pixel units 10 display a normal picture, and the other part of the pixel units 10 display a black picture, and black inserting display can be realized without adding a new double of Gate lines for black inserting display, thereby being beneficial to the design of a narrow frame.

It should be noted that, in the embodiment of the present application, the structure of the first pixel unit 11 and the structure of the second pixel unit 12 are substantially similar, and the difference is that: the arrangement of the display switch T1 and the black insertion switch T2 in the first pixel unit 11 is different from the arrangement of the display switch T1 and the black insertion switch T2 in the second pixel unit 12.

Each pixel unit 10 corresponds to one pixel color, and the pixel color corresponding to the pixel unit 10 is not limited herein, and is selected according to practical requirements.

The plurality of pixel units 10 in each row of pixel units 10 are defined as a first pixel unit 11 and a second pixel unit 12, respectively, and it is understood that each row of pixel units 10 includes the first pixel unit 11 and the second pixel unit 12.

It should be noted that, in the embodiment of the present application, the display switch T1 and the black inserting switch T2 of the pixel unit 10 are both transistors, and the conductivity types of the transistors are the same, so that when the display switch T1 in the first pixel unit 11 is turned on in each row of the pixel units 10, the black inserting switch T2 in the second pixel unit 12 can be turned on, thereby implementing black inserting display of the second pixel unit 12, and when the display switch T1 in the second pixel unit 12 is turned on, the black inserting switch T2 in the first pixel unit 11 can be turned on, thereby implementing black inserting display of the first pixel unit 11.

Specifically, the display switch T1 and the black insertion switch T2 are both N-type transistors. In other embodiments, the display switch T1 and the black insertion switch T2 may be P-type transistors.

The display panel 100 further includes a Data line Data for providing a Data voltage to the pixel unit 10. The pixel unit 10 further includes a pixel electrode P, a pixel capacitor Clc, a storage capacitor Cst, a color film substrate side common electrode CF-com, and an array substrate side common electrode a-com. The input terminal of the display switch T1 is electrically connected to the Data line Data, the output terminal of the display switch T1 is electrically connected to the pixel electrode P, and the control terminal of the display switch T1 is electrically connected to one of the first Gate line Gate1 and the second Gate line Gate2 in the corresponding Gate line group 20. The Data voltage output from the Data line Data is transmitted to the pixel electrode P through the display switch T1 to charge the pixel electrode P. The input end of the black insertion switch T2 is electrically connected to the pixel electrode P, the output end of the black insertion switch T2 is electrically connected to the array substrate side common electrode a-com, and the control end of the black insertion switch T2 is electrically connected to the other of the first Gate line Gate1 and the second Gate line Gate2 in the corresponding Gate line group 20. One end of the pixel capacitor Clc is electrically connected to the pixel electrode P, and the other end of the pixel capacitor Clc is electrically connected to the color film substrate-side common electrode CF-com. One end of the storage capacitor Cst is electrically connected to the pixel electrode P, and the other end of the storage capacitor Cst is electrically connected to the array substrate side common electrode a-com.

Liquid crystal molecules are arranged between each pixel electrode P and each color film substrate side common electrode CF-com, and when a potential difference exists between the pixel electrode P and the corresponding color film substrate side common electrode CF-com, an electric field is generated, and the electric field drives the corresponding liquid crystal molecules to deflect, so that the pixel unit 10 displays a normal picture. When the potential between the pixel electrode P and the corresponding color film substrate side common electrode CF-com is the same, the corresponding liquid crystal molecules are not deflected, and the pixel unit 10 displays a black picture.

Specifically, in the pixel unit 10, when the display switch T1 is turned on and the black insertion switch T2 is turned off, a potential difference exists between the common electrode CF-com on the color film substrate side and the pixel electrode P to drive the pixel unit 10 to display a normal picture. When the display switch T1 is turned off and the black insertion switch T2 is turned on, the potential between the common electrode CF-com on the color film substrate side and the pixel electrode P is the same to drive the pixel unit 10 to display a black picture, thereby realizing black insertion display.

In this embodiment, the column direction of the pixel unit 10 is the extending direction of the Data line Data.

In each Gate line group 20, the first Gate line Gate1 and the second Gate line Gate2 are spaced apart and insulated, so as to avoid the short circuit of the first Gate line Gate1 and the second Gate line Gate2, which affects the normal display of the pixel unit 10.

In this embodiment, in the same Gate line group 20, the first Gate line Gate1 and the second Gate line Gate2 are respectively located at two opposite sides of the corresponding row of pixel units 10 along the column direction of the pixel units 10, so that the display switch T1 in the pixel unit 10 is electrically connected to the adjacent Gate line, and the black insertion switch T2 in the pixel unit 10 is electrically connected to the adjacent Gate line, which is beneficial to reducing the connection wires.

Further, in each pixel unit 10, the display switch T1 and the black insertion switch T2 are distributed along the column direction of the pixel unit 10. The distribution directions of the display switch T1 and the black insertion switch T2 in the first pixel unit 11 are opposite to the distribution directions of the display switch T1 and the black insertion switch T2 in the second pixel unit 12. The distribution manner is beneficial to reducing the connection wiring between the display switch T1 and the grid line and the connection wiring between the black inserting switch T2 and the grid line.

Specifically, in each row of the pixel units 10, the display switch T1 of the first pixel unit 11 is disposed near the first Gate line Gate1, the black insertion switch T2 of the first pixel unit 11 is disposed near the second Gate line Gate2, the display switch T1 of the second pixel unit 12 is disposed near the second Gate line Gate2, and the black insertion switch T2 of the second pixel unit 12 is disposed near the first Gate line Gate 1.

Referring to fig. 1 to 3, fig. 3 is a schematic structural diagram of a display panel according to a second embodiment of the present application.

In other embodiments, in the same Gate line group 20, the first Gate line Gate1 and the second Gate line Gate2 may be located on the same side of the corresponding row of pixel units 10 along the column direction of the pixel units 10, and the display switch T1 and the black insertion switch T2 in the pixel units 10 may be distributed along the row direction of the pixel units 10 to reduce the connection wires with the Gate lines. The display switches T1 and the black insertion switches T2 are distributed along the row direction of the pixel unit 10. The distribution directions of the display switch T1 and the black insertion switch T2 in the first pixel unit 11 are opposite to the distribution directions of the display switch T1 and the black insertion switch T2 in the second pixel unit 12.

The display panel 100 further includes at least one scan driving circuit 30, the scan driving circuit 30 being for scanning the first Gate line Gate1 line by line; and/or the scan driving circuit 30 is used to scan the second Gate line Gate2 line by line.

That is, when the scan driving circuit 30 is one, the scan driving circuit 30 is used to scan the first Gate line Gate1 line by line and scan the second Gate line Gate2 line by line. That is, each row of gate lines is driven unilaterally. The Gate lines in the embodiment of the present application represent a first Gate line Gate1 and a second Gate line Gate2.

When the number of the scan driving circuits 30 is plural, each row of gate lines may be driven on one side, or each row of gate lines may be driven on both sides. When driving each row of Gate lines on a single side, one scan driving circuit 30 is used for scanning the first Gate line Gate1 row by row, and the other scan driving circuit 30 is used for scanning the second Gate line Gate2 row by row. When each row of gate lines is driven in a bilateral manner, two ends of each row of gate lines are respectively connected with a scanning driving circuit 30, that is, two scanning driving circuits 30 scan one row of gate lines at the same time.

It should be understood that the design of the single-side driving gate lines is more advantageous for the design of the narrow frame due to the fewer scan driving circuits 30 than the design of the double-side driving gate lines. Compared with the mode of unilaterally driving the gate lines, the design mode of bilateral driving the gate lines can better reduce the voltage drop problem caused by wiring load, so that the capability of driving the gate lines is better, the display quality of the display panel 100 can be better improved, and the display panel is suitable for large-size panels.

The specific configuration of the scan driving circuit 30 is not limited herein, and is selected according to actual requirements.

In the present embodiment, the number of the scanning driving circuits 30 is two, and the two scanning driving circuits 30 are respectively represented as a first driving circuit 31 and a second driving circuit 32. The first driving circuit 31 and the second driving circuit 32 are respectively located at opposite sides of each row of the pixel units 10 in the row direction of the pixel units 10. The first driving circuit 31 is used for scanning the first Gate line Gate1 line by line, and the second driving circuit 32 is used for scanning the second Gate line Gate2 line by line.

Referring to fig. 1 to 5, fig. 4 is a timing chart of an embodiment of a signal line provided by the present application, and fig. 5 is a timing chart of an embodiment of a gate line provided by the present application.

Further, the scan driving circuit 30 scans the m rows of the first Gate lines Gate1 at the same time.

In the multiple rows of first Gate lines Gate1, the working time sequence of the (m+i) th row of first Gate lines Gate1 lags the working time sequence of the (i) th row of first Gate lines Gate1, and the lag time is a preset time length.

In the same Gate line group 20, the operation timing of the second Gate line Gate2 lags behind the operation timing of the first Gate line Gate1 by a predetermined time period n times. Wherein n is greater than 1 and is an odd number, m is greater than or equal to 1, and i is greater than or equal to 1.

In this timing design manner, the working timing sequence of the first Gate line Gate1 and the working timing sequence of the second Gate line Gate2 are prevented from overlapping in time sequence, which results in the wrong flushing of the pixel electrode P, so that the display switch T1 and the black insertion switch T2 in the single pixel unit 10 are turned on simultaneously, and the normal display of the pixel unit 10 is affected. If the display data are simultaneously turned on, the display data are cleaned by the black inserted data, and the display data cannot be normally displayed.

The single scan driving circuit 30 may scan one row of the first Gate lines Gate1 at the same time, or may drive a plurality of rows of the first Gate lines Gate1 at the same time. The scan driving circuit 30 includes a plurality of scan driving units (not shown) in cascade, and the hierarchical relationship of the plurality of scan driving units in the scan driving circuit 30 is not particularly limited, so long as the timing between the gate lines is ensured as described above.

When the single scan driving circuit 30 scans the plurality of rows of the first Gate lines Gate1 at the same time, it is possible to realize a display of a high brush with a low brush driving. For example, as shown in fig. 5, control DLG (Dual line Gate) is implemented, in which the first Gate lines Gate1-1 and the second Gate lines Gate1-2 are simultaneously scanned, and the timing of the first Gate lines Gate1-1 and the timing of the second Gate lines Gate1-2 are the same, so that the timing of the first Gate lines Gate2-1 and the timing of the second Gate lines Gate2-2 are the same in the second Gate lines Gate 2. Of the plurality of rows of first Gate lines Gate1, the timing of the third row of first Gate lines Gate1-3 is the same as the timing of the fourth row of first Gate lines Gate 1-4; in the multiple rows of second Gate lines Gate2, the time sequence of the third row of second Gate lines Gate2-3 is the same as the time sequence of the fourth row of second Gate lines Gate2-4, the working time sequence of the third row of first Gate lines Gate1-3 lags the working time sequence of the first row of first Gate lines Gate1-1 by a preset time length t, the working time sequence of the first row of second Gate lines Gate2-1 lags the working time sequence of the first row of first Gate lines Gate1-1 by n times of the preset time length t, and so on. It should be understood that, in this case, the hierarchical relationship of the plurality of scan driving units in the same scan driving circuit 30 needs to be defined by a multiple of 2.

Further, the display panel 100 further includes a frame start signal line STV for supplying a frame start signal to the scan driving circuit 30, and a clock signal line CK. The clock signal line CK is used to transmit a clock signal to the scan driving circuit 30, and the scan driving circuit 30 is used to scan the gate lines line by line according to the clock signal. The frame start signal also serves as a trigger signal for the clock signal.

In this embodiment, the number of clock signal lines CK is four, and the four clock signal lines CK are respectively represented as a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4. The operation timing of the third clock signal line CK3 lags the operation timing of the first clock signal line CK1, and the lag time is a preset time t. The operation timing of the fourth clock signal line CK4 lags the operation timing of the second clock signal line CK2, and the lag time is a preset time t. The operation timing of the second clock signal line CK2 lags behind the operation timing of the first clock signal line CK1 by a predetermined time period t of n times.

It should be understood that in other embodiments, the clock signal lines CK may be more.

The two frame start signal lines STV are respectively indicated as a first frame start signal line STV1 and a second frame start signal line STV2. The frame start signal supplied from the first frame start signal line STV1 serves as a trigger signal of the first clock signal line CK1, and the frame start signal supplied from the second frame start signal line STV2 serves as a trigger signal of the second clock signal line CK 2. That is, the operation timing of the second frame start signal line STV2 lags the operation timing of the first frame start signal line STV1, and the lag time is n times the preset time t.

In the embodiment of the application, a frame start signal line STV is additionally added to distinguish the time sequence of the first Gate line Gate1 from the time sequence of the second Gate line Gate2, so that black insertion display of the display panel 100 can be realized, and the abnormality caused by mutual hierarchical transmission of the first Gate line Gate1 and the second Gate line Gate2 is avoided.

In one embodiment, in the same Gate line group 20, the operation timing of the second Gate line Gate2 lags behind the operation timing of the first Gate line Gate1, and the lag time is at least half a frame time, so that black insertion is achieved under the condition that normal display of the pixel unit 10 is not affected, and a suitable black insertion amount is achieved to improve the display quality of the display panel 100. When the lag time is less than the half frame time, the insufficient charging time of the pixel electrode P may affect the display effect of the display panel 100.

The display panel 100 further includes a plurality of pixel groups 13, where the pixel groups 13 include a first pixel unit 11 and a second pixel unit 12 disposed adjacent to each other and side by side. The pixel groups 13 are repeatedly arranged in the row direction of the pixel units 10 and are repeatedly arranged in the column direction of the pixel units 10. The first pixel unit 11 and the second pixel unit 12 located in different pixel groups 13 and adjacently disposed share the same Data line Data.

That is, in the row direction of the pixel units 10, the first pixel units 11 and the second pixel units 12 are alternately arranged in order; in the column direction of the pixel units 10, the pixel units 10 are repeatedly arranged.

Specifically, in the same Gate line group 20, the first Gate line Gate1 provides a high potential, the second Gate line Gate2 provides a low potential, the display switch T1 in the first pixel unit 11 is turned on, and the black insertion switch T2 in the first pixel unit 11 is turned off, so that the first pixel unit 11 displays a normal screen; the black insertion switch T2 in the second pixel unit 12 is turned on, and the display switch T1 is turned off, so that the first pixel unit 11 displays a normal picture, and the second pixel unit 12 displays a black picture to realize black insertion display of the second pixel unit 12. In contrast, in the same Gate line group 20, the second Gate line Gate2 provides a high potential, the first Gate line Gate1 provides a low potential, the second pixel unit 12 displays a normal screen, and the first pixel unit 11 displays a black screen to implement black insertion display of the first pixel unit 11, so as to complete normal display and black insertion display of all the pixel units 10 in one row of pixel units 10.

The arrangement manner of the pixel units 10 in this embodiment can reduce the number of Data lines Data, thereby reducing COF (Chip On Film) number and further reducing cost.

The polarity distribution pattern of the pixel electrodes P of the plurality of pixel units 10 in the display panel 100 includes at least one of column inversion, row inversion, single dot inversion, multi-dot inversion, and frame inversion.

Specifically, in the present embodiment, in each column of the pixel units 10, the polarities of the pixel electrodes P of the adjacent two pixel units 10 are opposite; in each row of the pixel cells 10, the polarities of the pixel electrodes P of the two pixel cells 10 sharing the same Data line Data are opposite.

Referring to fig. 1, fig. 2, fig. 6 and fig. 7, fig. 6 is a schematic structural diagram of a third embodiment of a display panel according to the present application, and fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application.

The third embodiment of the display panel 100 provided by the present application is substantially similar to the first embodiment of the display panel 100 provided by the present application, except that: the display panel 100 includes a plurality of pixel groups 13, and the pixel groups 13 are repeatedly arranged along a row direction of the pixel units 10 and are repeatedly arranged along a column direction of the pixel units 10. The pixel group 13 includes a first pixel group 131 and a second pixel group 132 disposed side by side in this order.

Specifically, in the present embodiment, the display panel 100 includes a plurality of pixel groups 13, and the pixel groups 13 are repeatedly arranged in the row direction of the pixel units 10 and are repeatedly arranged in the column direction of the pixel units 10. The pixel group 13 includes a first pixel group 131 and a second pixel group 132 that are sequentially arranged side by side, the first pixel group 131 includes a plurality of first pixel units 11 that are arranged side by side, the second pixel group 132 includes a plurality of second pixel units 12 that are arranged side by side, and the first pixel units 11 in the first pixel group 131 are arranged in one-to-one correspondence with the second pixel units 12 in the second pixel group 132. In the pixel group 13, the Data line Data connected to the first pixel unit 11 in the first pixel group 131 is electrically connected to the Data line Data connected to the corresponding second pixel unit 12 in the second pixel group 132.

That is, in the row direction of the pixel unit 10, the first pixel groups 131 and the second pixel groups 132 are alternately arranged in order.

Further, in each column of the pixel units 10, the polarities of the pixel electrodes P of the pixel units 10 are the same; in each row of pixel cells 10, the polarities of the pixel electrodes P of two adjacent pixel cells 10 are opposite. It can be understood that the polarity distribution pattern of the pixel electrodes P of the plurality of pixel units 10 in the display panel 100 is column inversion. The pixel units 10 electrically connected to each other by the Data lines Data are identical in corresponding pixel color so as to control the display condition of the pixel units 10 of the same pixel color.

As shown in fig. 7, in a specific embodiment, the first pixel group 131 includes six first pixel units 11 sequentially arranged side by side, and the colors of the pixels corresponding to the six first pixel units 11 sequentially arranged side by side are sequentially red (R), green (G), blue (B), red (R), green (G), and blue (B). In the first pixel group 131, the polarities of the pixel electrodes P of the first pixel units 11 having the same pixel color are opposite. Similarly, the second pixel group 132 includes six second pixel units 12 sequentially arranged side by side, and the pixel colors corresponding to the six second pixel units 12 sequentially arranged side by side are sequentially red (R), green (G), blue (B), red (R), green (G), and blue (B). In the second pixel group 132, the polarities of the pixel electrodes P of the second pixel units 12 having the same pixel color are opposite. That is, in each pixel group 13, the f-th column Data line Data and the f+6-th column Data line Data are electrically connected, and f is less than or equal to 6.

It should be appreciated that more pixel cells 10 may be included in each pixel group 13.

Compared with the first embodiment of the display panel 100 provided by the present application, the present embodiment can also reduce the number of gate lines, so that the number of driving units for driving the gate lines can be reduced, and the design of a narrow frame is facilitated on the basis of implementing black insertion display. Second, the present embodiment can further reduce the COF number to further reduce the cost.

It should be understood that, in each row of pixel units 10, the Data lines Data connected to the first pixel units 11 in one pixel group 13 may be electrically connected to the Data lines Data connected to the corresponding first pixel units 11 in a different pixel group 13, so that the COF number may be further reduced.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a display device according to an embodiment of the application.

The embodiment of the application provides a display device 300. The display device 300 includes the main board 200 and the display panel 100 in the above-described embodiment. The main board 200 is electrically connected to the display panel 100, and the main board 200 is used for transmitting various required signals to the display panel 100 to control the display panel 100 to display images. For example, a clock signal (CK), a common voltage signal (Vss), a power supply voltage signal (VDD), and the like required for the scan driving circuit, and a Data signal (Data) and the like required for the Data line.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The foregoing is only the embodiments of the present application, and therefore, the patent protection scope of the present application is not limited thereto, and all equivalent structures or equivalent flow changes made by the content of the present specification and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A display panel, comprising:

A gate line group including a first gate line and a second gate line; each grid line group is arranged corresponding to one row of pixel units and is electrically connected with the pixel units;

In each row of the pixel units, a display switch in the first pixel unit and a black inserting switch in the second pixel unit are coupled with the same first gate line, and the black inserting switch in the first pixel unit and the display switch in the second pixel unit are coupled with the same second gate line.

2. The display panel according to claim 1, wherein in each of the pixel units, the display switches and the black insertion switches are distributed along a column direction of the pixel unit, or the display switches and the black insertion switches are distributed along a row direction of the pixel unit; the distribution directions of the display switch and the black inserting switch in the first pixel unit are opposite to the distribution directions of the display switch and the black inserting switch in the second pixel unit.

3. The display panel according to claim 2, further comprising at least one scan driving circuit for scanning the first gate lines line by line; and/or the scanning driving circuit is used for scanning the second gate lines line by line; the scanning driving circuit scans m rows of the first gate lines at the same time;

In the multiple rows of the first gate lines, the working time sequence of the first gate line in the (m+i) th row lags the working time sequence of the first gate line in the (i) th row, and the lag time is a preset time length;

In the same gate line group, the working time sequence of the second gate line lags behind the working time sequence of the first gate line, and the lag time is n times of the preset time length;

4. The display panel of claim 3, wherein the operation timing of the second gate line is delayed from the operation timing of the first gate line in the same gate line group, and the delay period is at least half a frame time.

5. The display panel according to claim 2, further comprising a data line, wherein the pixel unit further comprises a pixel electrode, a pixel capacitor, a storage capacitor, a color film substrate side common electrode, and an array substrate side common electrode; the input end of the display switch is electrically connected with the data line, the output end of the display switch is electrically connected with the pixel electrode, and the control end of the display switch is electrically connected with one of the first gate line and the second gate line in the corresponding gate line group; the input end of the black inserting switch is electrically connected with the pixel electrode, the output end of the black inserting switch is electrically connected with the common electrode on the side of the array substrate, and the control end of the black inserting switch is electrically connected with the other one of the first gate line and the second gate line in the corresponding gate line group; one end of the pixel capacitor is electrically connected with the pixel electrode, and the other end of the pixel capacitor is electrically connected with the common electrode on the color film substrate side; one end of the storage capacitor is electrically connected with the pixel electrode, and the other end of the storage capacitor is electrically connected with the common electrode on the side of the array substrate.

6. The display panel of claim 2, further comprising a data line and a plurality of pixel groups, the pixel groups including a first pixel unit and a second pixel unit disposed adjacent and side by side; the pixel groups are repeatedly arranged along the row direction of the pixel units and are repeatedly arranged along the column direction of the pixel units; the first pixel units and the second pixel units which are positioned in different pixel groups and are adjacently arranged share the same data line.

7. The display panel of claim 6, wherein the polarity distribution pattern of the pixel electrodes of the plurality of pixel units in the display panel comprises at least one of column inversion, row inversion, single dot inversion, multi-dot inversion, and frame inversion.

8. The display panel of claim 2, further comprising a data line and a plurality of pixel groups; the pixel groups are repeatedly arranged along the row direction of the pixel units and are repeatedly arranged along the column direction of the pixel units; the pixel group comprises a first pixel group and a second pixel group which are sequentially arranged side by side, the first pixel group comprises a plurality of first pixel units arranged side by side, the second pixel group comprises a plurality of second pixel units arranged side by side, and the first pixel units in the first pixel group are arranged in one-to-one correspondence with the second pixel units in the second pixel group; in the pixel group, the data lines connected with the first pixel units in the first pixel group are electrically connected with the data lines connected with the corresponding second pixel units in the second pixel group.

9. The display panel of claim 8, wherein in each column of the pixel units, the polarities of the pixel electrodes of the pixel units are the same; in each row of the pixel units, the polarities of the pixel electrodes of two adjacent pixel units are opposite; and the pixel colors corresponding to the pixel units electrically connected with each other by the data lines are the same.

10. A display device comprising a main board and the display panel of any one of claims 1 to 9.