CN102081270A - Liquid crystal display device and driving method thereof - Google Patents
Liquid crystal display device and driving method thereof Download PDFInfo
- Publication number
- CN102081270A CN102081270A CN 201110044836 CN201110044836A CN102081270A CN 102081270 A CN102081270 A CN 102081270A CN 201110044836 CN201110044836 CN 201110044836 CN 201110044836 A CN201110044836 A CN 201110044836A CN 102081270 A CN102081270 A CN 102081270A
- Authority
- CN
- China
- Prior art keywords
- liquid crystal
- black plug
- film transistor
- thin film
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses an array substrate of a liquid crystal display device and a driving method thereof. The array substrate comprises a first pixel, a second pixel, a third pixel and a fourth pixel. Each pixel comprises a display thin film transistor and a black frame insertion thin film transistor and corresponding display thin film transistors and black frame insertion thin film transistors are connected to a same scan line. Therefore, when a scan line is opened, normal display pictures and black frame insertion pictures can be filled simultaneously for different pixels. The liquid crystal display device shortens the charging time while realizing black frame insertion and prevents the problem of display dynamic picture ghosting.
Description
[technical field]
The present invention relates to a kind of liquid crystal indicator and driving method thereof, especially relate to a kind of liquid crystal indicator and driving method thereof that can insert black picture.
[background technology]
Along with the arriving in HDTV epoch, the application of liquid crystal indicator is more and more universal, thereby liquid crystal indicator utilizes the rotation of electric field controls liquid crystal molecule and produces different transmittance display images.Liquid crystal indicator comprises the array base palte that is positioned at infrabasal plate and the colored filter substrate that is positioned at upper substrate, and wherein array base palte comprises and is used to drive this LCD drive circuits.
Fig. 1 is the circuit block diagram of the array base palte 70 of prior art liquid crystal indicator, as shown in Figure 1, array base palte 70 comprises: source electrode driver 701 (source driver), gate drivers 702 (gate driver), multi-strip scanning line XL1, XL2 ..., XLn (n＞2), many data line YL1, YL2 ..., YLm (m＞2), a plurality of thin film transistor (TFT)s (TFT) 703, a plurality of liquid crystal capacitances 704, and a plurality of memory capacitance 705; Gate drivers 702 and multi-strip scanning line XL1, XL2 ..., XLn connects, be used for the sweep trace XL1 on the array base palte 70 is driven to XLn; Source electrode driver and many data line YL1, YL2 ..., YLm connects, be used for the data line YL1 on the array base palte 70 of liquid crystal indicator is driven to YLm.
Wherein thin film transistor (TFT) 703 comprises a grid, one source pole and a drain, and grid is connected with sweep trace, and source electrode is connected with data line, and drain is connected with liquid crystal capacitance 704.Liquid crystal capacitance 704 is made of a pixel electrode, a common electrode and liquid crystal layer, and wherein liquid crystal layer is folded between this pixel electrode and the common electrode.
When operate as normal, gate drivers 702 with control signal (high level signal) input in regular turn sweep trace XL1, XL2 ..., XLn, thereby open corresponding thin film transistor (TFT) 703, meanwhile source electrode driver 701 with data-signal via data line YL1, YL2 ..., YLm inputs to corresponding pixel electrode, after thin film transistor (TFT) 703 ended, pixel electrode entered voltage and keeps (holding).Wherein pixel electrode and common electrode form an electric field, utilize the rotation of liquid crystal molecule in this electric field controls liquid crystal layer and produce different transmittances, have realized the picture demonstration thus.
Yet, because the material behavior (specific inductive capacity of the liquid crystal molecule of liquid crystal layer in the above-mentioned liquid crystal capacitance 704, viscosity, elastic modulus) and the voltage maintenance type of drive of liquid crystal indicator, can make above-mentioned liquid crystal indicator that smear problem is arranged when showing dynamic menu.
In order to overcome above-mentioned demonstration dynamic menu smear problem, prior art has disclosed the driving method of the black picture (black frame) of a kind of insertion in conjunction with above-mentioned liquid crystal indicator.It generally is by the frequency that improves picture frame (Frame) black picture to be inserted between a last picture frame normal pictures and next the picture frame normal pictures; yet; insert the duration of charging (charging time) that the method for black picture data signal has shortened thin film transistor (TFT) in each picture frame by improving the picture frame frequency; thereby can shorten the time that data-signal inputs to pixel electrode; thereby cause the problem of pixel electrode undercharge easily, and then influence us and want picture displayed.
[summary of the invention]
In order to overcome problems of the prior art, the invention provides a kind of array base palte and driving method thereof of liquid crystal indicator.
The invention provides a kind of array base palte of liquid crystal indicator, comprising: first picture element, second picture element, the 3rd picture element and the 4th picture element.Wherein, first picture element comprises: first liquid crystal capacitance and first memory capacitance, and wherein first liquid crystal capacitance, one end links to each other with first memory capacitance, one end, and the first liquid crystal capacitance other end links to each other with the first memory capacitance other end and is connected to common electric voltage Vcom end; First shows thin film transistor (TFT), and first shows that the source electrode of thin film transistor (TFT) is connected to a data line, and drain connects an end of first liquid crystal capacitance and an end of first memory capacitance, and grid is connected to second sweep trace; The first black plug thin film transistor (TFT), the source electrode of the first black plug thin film transistor (TFT) connects the first black plug voltage input end, drain connects an end of above-mentioned first liquid crystal capacitance and an end of first memory capacitance, and also is connected to the first demonstration drain of film transistor, and grid is connected to the 4th sweep trace.Second picture element comprises: second liquid crystal capacitance and second memory capacitance, and wherein second liquid crystal capacitance, one end links to each other with second memory capacitance, one end, and the second liquid crystal capacitance other end links to each other with the second memory capacitance other end and is connected to common electric voltage Vcom end; Second shows thin film transistor (TFT), and second shows that the source electrode of thin film transistor (TFT) is connected to data line, and drain connects an end of above-mentioned second liquid crystal capacitance and an end of second memory capacitance, and grid is connected to three scan line; The second black plug thin film transistor (TFT), the source electrode of the second black plug thin film transistor (TFT) connects the second black plug voltage input end, the drain end connects an end of second liquid crystal capacitance and an end of second memory capacitance, and also is connected to the second demonstration drain of film transistor, and grid is connected to first sweep trace.The 3rd picture element comprises: the 3rd liquid crystal capacitance and the 3rd memory capacitance, and wherein the 3rd liquid crystal capacitance one end links to each other with the 3rd memory capacitance one end, and the 3rd liquid crystal capacitance other end links to each other with the 3rd memory capacitance other end and is connected to common electric voltage Vcom end; The 3rd shows thin film transistor (TFT), and the 3rd shows that the source electrode of thin film transistor (TFT) is connected to data line, and drain connects an end of above-mentioned the 3rd liquid crystal capacitance and an end of the 3rd memory capacitance, and grid is connected to the 4th sweep trace; The 3rd black plug thin film transistor (TFT), the source electrode of the 3rd black plug thin film transistor (TFT) connects one the 3rd black plug voltage input end, drain connects an end of above-mentioned the 3rd liquid crystal capacitance and an end of the 3rd memory capacitance, and also is connected to the 3rd demonstration drain of film transistor, and grid is connected to the 6th sweep trace.The 4th picture element comprises: the 4th liquid crystal capacitance and the 4th memory capacitance, and wherein the 4th liquid crystal capacitance one end links to each other with the 4th memory capacitance one end, and the 4th liquid crystal capacitance other end links to each other with the 4th memory capacitance other end and is connected to common electric voltage Vcom end; The 4th shows thin film transistor (TFT), and the 4th shows that the source electrode of thin film transistor (TFT) is connected to this data line, and drain connects an end of above-mentioned the 4th liquid crystal capacitance and an end of the 4th memory capacitance, and grid is connected to the 5th sweep trace; The 4th black plug thin film transistor (TFT), the source electrode of the 4th thin film transistor (TFT) connects the 4th black plug voltage input end, drain connects an end of the 4th liquid crystal capacitance and an end of the 4th memory capacitance, and also is connected to the 4th demonstration drain of film transistor, and grid is connected to this three scan line.
In one of the present invention embodiment, array base palte more comprises a black plug boost line, and this black plug boost line and this data line are provided with at interval.The black plug boost line comprises odd number black plug boost line and even number black plug boost line, and odd number black plug boost line is connected to the first and the 3rd black plug voltage input end, and even number black plug boost line is connected to this second and the 4th black plug voltage input end.
In one of the present invention embodiment, odd number black plug boost line is connected common electric voltage Vcom end with even number black plug auxiliary series.
In one of the present invention embodiment, odd number black plug boost line is connected high level or low level end with even number black plug auxiliary series.
In one of the present invention embodiment, array base palte also comprises a common line, and this common line is connected to this first, second, third and the 4th black plug voltage input end respectively.
In one of the present invention embodiment, the first black plug voltage input end is connected to described the 4th sweep trace, this second black plug voltage input end connects described first sweep trace, the 3rd black plug voltage input end is connected to described the 6th sweep trace, and the 4th black plug voltage input end is connected to described three scan line.
The present invention also provides a kind of driving method of array base palte of liquid crystal indicator, comprise: during first sequential, drive most bar second sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, first liquid crystal capacitance of first pixel is charged into normal voltage, simultaneously, the 3rd liquid crystal capacitance of the 3rd pixel is charged into black voltage; During second sequential, drive most articles of three scan lines in regular turn to open corresponding thin film transistor (TFT), therefore, second liquid crystal capacitance of second pixel is charged into normal voltage, and simultaneously, the 4th liquid crystal capacitance of the 4th pixel is charged into black plug voltage; During the 3rd sequential, drive most articles the 4th sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, the 3rd liquid crystal capacitance of the 3rd pixel is charged into normal voltage, and simultaneously, first liquid crystal capacitance of first pixel is charged into black plug voltage; During the 4th sequential, drive most articles the 5th sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, the 4th liquid crystal capacitance of the 4th pixel is charged into normal voltage, and simultaneously, second liquid crystal capacitance of second pixel is charged into black plug voltage.
In one of the present invention embodiment, during first sequential, during second sequential, during the 3rd sequential and the summation during the 4th sequential equal 16.67 milliseconds.
In one of the present invention embodiment, equal in fact during first sequential, during second sequential, during the 3rd sequential with the time during the 4th sequential.
According to the above, the present invention is provided with two thin film transistor (TFT)s in a pixel, a thin film transistor (TFT) is used for controlling charging into of normal display voltage, the another one thin film transistor (TFT) is used for controlling charging into of black plug voltage, and, a pixel being carried out normal voltage when charging into, simultaneously the another one pixel is charged into black plug voltage.And, in the driving method of the array base palte of liquid crystal indicator of the present invention, half the time pixel at a picture frame remains normal display voltage, remain black plug voltage in other half the time pixel, therefore the present invention realizes inserting does not need to increase frequency when deceiving picture, therefore, the time of a picture frame of liquid crystal indicator of the present invention does not reduce, therefore, total duration of charging, (charging time) can not reduce yet, the problem of the picture element duration of charging deficiency that case is mentioned before therefore can not occurring.In addition, because the present invention realizes having inserted black picture, therefore the problem of dynamic menu smear can not appear showing in liquid crystal indicator of the present invention.
[description of drawings]
Fig. 1 is the circuit block diagram of the array base palte of prior art liquid crystal indicator.
Fig. 2 is the electrical block diagram of the array base palte of first embodiment of the invention liquid crystal indicator.
Fig. 3 is the detailed circuit diagram of a picture element unit of first embodiment of the invention.
Fig. 4 is the process flow diagram of the array base palte driving method of first embodiment of the invention liquid crystal indicator.
Fig. 5 is the drive waveforms figure of the array base palte of first embodiment of the invention liquid crystal indicator.
Fig. 6 a is the charging effect figure of pixel during first sequential.
Fig. 6 b is the charging effect figure of pixel during second sequential.
Fig. 6 c is the charging effect figure of pixel during the 3rd sequential.
Fig. 6 d is the charging effect figure of pixel during the 4th sequential.
Fig. 7 is the electrical block diagram of the array base palte of second embodiment of the invention liquid crystal indicator.
Fig. 8 is the detailed circuit diagram of a picture element unit of second embodiment of the invention.
Fig. 9 is the electrical block diagram of the array base palte of third embodiment of the invention liquid crystal indicator.
Figure 10 is the detailed circuit diagram of a picture element unit of third embodiment of the invention.
[embodiment]
The present invention is described in detail below in conjunction with drawings and Examples.
First embodiment
See also Fig. 2, Fig. 2 is the electrical block diagram of the array base palte 10 of first embodiment of the invention liquid crystal indicator.This array base palte 10 comprises: gate drivers 102, source electrode driver 101, the sweep trace SL0 that most bars are parallel to each other, SL1, SL2 ..., SL4n-1 (n is a positive integer), the data line DL1 that most bars are parallel to each other, DL2, ..., DLm (m is a positive integer), the black plug boost line Y1 that most bars are parallel to each other, Y2 ..., Ym, most picture element unit that comprise the first picture element P1, the second picture element P2, the 3rd picture element P3 and the 4th picture element P4, and a black appliances pressure side 107.Wherein, most bar sweep trace SL0, SL1 ..., SL4n-1 is connected to gate drivers 102, is used for transmitting the control signal voltage of gate drivers 102 outputs; Plurality of data lines DL1, DL2 ..., DLm is connected to source electrode driver 101, is used for the normal pictures display voltage of transmission sources driver 101 output; Most bar black plug boost line Y1, Y2 ..., Ym be divided into odd number black plug boost line Y1, Y3, Y5 ... and even number black plug boost line Y2, Y4, Y6 ..., all be connected to a black appliances pressure side 107, be used for transmitting the needed black plug voltage of black plug picture of black appliances pressure side 107 outputs, and, black plug boost line Y1, Y2 ..., Ym and data line DL1, DL2 ..., the parallel to each other and alternately arrangement of DLm, and both respectively with sweep trace SL0, SL1 ..., SL4n-1 is arranged in a crossed manner and be electrically insulated; The first picture element P1 of picture element unit, the second picture element P2, the 3rd picture element P3 and the 4th picture element P4 are surrounded by sweep trace and data line and black plug boost line respectively, and the first picture element P1, the second picture element P2 the 3rd picture element P3 link to each other with sweep trace, data line and black plug boost line respectively with the 4th picture element P4.
The circuit connecting relation of a plurality of picture elements unit that is made of the first picture element P1, the second picture element P2, the 3rd picture element P3 and the 4th picture element P4 is similar, therefore, will be that example describes its electrical connection in detail with a picture element unit below.Fig. 3 is sweep trace SL4i+1 (being defined as second sweep trace), sweep trace SL4i+2 (being defined as three scan line), SL4i+3 (being defined as the 4th sweep trace), SL4i+4 (being defined as the 5th sweep trace), data line DLj, (i is a natural number for black plug boost line Yj and black plug boost line Yj+1, j is a positive integer) detailed circuit diagram of a picture element unit being surrounded, and sweep trace SL4i (being defined as first sweep trace) is for being positioned at a sweep trace and adjacent with it of sweep trace SL4i+1 front, and sweep trace SL4i+5 (being defined as the 6th sweep trace) is for being positioned at a sweep trace and adjacent with it of sweep trace SL4i+4 back.Please merge and consult Fig. 2 and Fig. 3, in the present embodiment, the first picture element P1 and the 3rd picture element P3 are the picture element on the data line DLj left side, the second picture element P2 and the 4th picture element P4 are the picture element (consulting Fig. 3) on data line DLj the right, but, the invention is not restricted to this, the first picture element P1 and the 3rd picture element P3 are the picture element on data line DLj the right, and the second picture element P2 and the 4th picture element P4 are that the picture element on the data line DLj left side is also passable.
The first picture element P1 comprises that first liquid crystal capacitance 104, first memory capacitance 105, first show thin film transistor (TFT) 103a, the first black plug thin film transistor (TFT) 103b, and one first black plug voltage input end 106.Wherein, one end of first liquid crystal capacitance 104 links to each other with an end of first memory capacitance 105, and be connected to first jointly and show the thin film transistor (TFT) 103a and the first black plug thin film transistor (TFT) 103b, an other end of first liquid crystal capacitance 104 links to each other with an other end of first memory capacitance 105, and the other end that should link to each other is connected to the Vcom of energising pressure altogether end jointly.First shows that the grid of thin film transistor (TFT) 103a is connected to sweep trace SL4i+1, and source electrode is connected to data line DLj, and drain is connected to first liquid crystal capacitance 104 and first memory capacitance, 105 common ends that link to each other.The grid of the first black plug thin film transistor (TFT) 103b is connected to sweep trace SL4i+3, source electrode is connected to the first black plug voltage input end 106, drain and first shows that the drain of thin film transistor (TFT) 103a links to each other, and it is connected to first liquid crystal capacitance 104 and first memory capacitance, 105 common ends that link to each other jointly.The first black plug voltage input end 106 links to each other with black plug boost line Yj, goes up the drain of the black plug voltage of transmission to the first black plug thin film transistor (TFT) 103b to transmit black plug boost line Yj.In addition, in the present embodiment, odd number black plug boost line comprises black plug boost line Yj, and even number black plug boost line comprises black plug boost line Yj+1.
The second picture element P2 comprises that second liquid crystal capacitance 204, second memory capacitance 205, second show the thin film transistor (TFT) 203a and the second black plug thin film transistor (TFT) 203b, and one second black plug voltage input end 206.Wherein, one end of second liquid crystal capacitance 204 links to each other with an end of second memory capacitance 205, and be connected to second jointly and show the thin film transistor (TFT) 203a and the second black plug thin film transistor (TFT) 203b, an other end of second liquid crystal capacitance 204 links to each other with an other end of second memory capacitance 205, and the other end that should link to each other is connected to the Vcom of energising pressure altogether end jointly.Second shows that the grid of thin film transistor (TFT) 203a is connected to sweep trace SL4i+2, and source electrode is connected to data line DLj, and drain is connected to second liquid crystal capacitance 204 and second memory capacitance, 205 common ends that link to each other.The grid of the second black plug thin film transistor (TFT) 203b is connected to sweep trace SL4i, source electrode is connected to the second black plug voltage input end 206, drain and second shows that the drain of thin film transistor (TFT) 203a links to each other, and it is connected to second liquid crystal capacitance 204 and second memory capacitance, 205 common ends that link to each other jointly.The second black plug voltage input end 206 links to each other with black plug boost line Yj+1, goes up the drain of the black plug voltage of transmission to the second black plug thin film transistor (TFT) 203b to transmit black plug boost line Yj+1.
The 3rd picture element P3 comprises that the 3rd liquid crystal capacitance 304, the 3rd memory capacitance the 305, the 3rd show thin film transistor (TFT) 303a, the 3rd black plug thin film transistor (TFT) 303b, and one the 3rd black plug voltage input end 306.Wherein, one end of the 3rd liquid crystal capacitance 304 links to each other with an end of the 3rd memory capacitance 305, and be connected to the 3rd jointly and show thin film transistor (TFT) 303a and the 3rd black plug thin film transistor (TFT) 303b, an other end of the 3rd liquid crystal capacitance 304 links to each other with an other end of the 3rd memory capacitance 305, and the other end that should link to each other is connected to the Vcom of energising pressure altogether end jointly.The 3rd shows that the grid of thin film transistor (TFT) 303a is connected to sweep trace SL4i+3, and source electrode is connected to data line DLj, and drain is connected to the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 common ends that link to each other.The grid of the 3rd black plug thin film transistor (TFT) 303b is connected to sweep trace SL4i+5, source electrode is connected to the 3rd black plug voltage input end 306, drain and the 3rd shows that the drain of thin film transistor (TFT) 303a links to each other, and it is connected to the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 common ends that link to each other jointly.The 3rd black plug voltage input end 306 links to each other with black plug boost line Yj, to transmit the drain that black plug boost line Yj goes up black plug voltage to the three black plug thin film transistor (TFT) 303b that transmit.
The 4th picture element P4 comprises that the 4th liquid crystal capacitance 404, the 4th memory capacitance the 405, the 4th show thin film transistor (TFT) 403a and the 4th black plug thin film transistor (TFT) 403b, and one the 4th black plug voltage input end 406.Wherein, one end of the 4th liquid crystal capacitance 404 links to each other with an end of the 4th memory capacitance 405, and be connected to the 4th jointly and show thin film transistor (TFT) 403a and the 4th black plug thin film transistor (TFT) 403b, an other end of the 4th liquid crystal capacitance 404 links to each other with an other end of the 4th memory capacitance 405, and the other end that should link to each other is connected to the Vcom of energising pressure altogether end jointly.The 4th shows that the grid of thin film transistor (TFT) 403a is connected to sweep trace SL4i+4, and source electrode is connected to data line DLj, and drain is connected to the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 common ends that link to each other.The grid of the 4th black plug thin film transistor (TFT) 403b is connected to sweep trace SL4i+2, source electrode is connected to the 4th black plug voltage input end 406, drain and the 4th shows that the drain of thin film transistor (TFT) 403a links to each other, and it is connected to the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 common ends that link to each other jointly.The 4th black plug voltage input end 406 links to each other with black plug boost line Yj+1, to transmit the drain that black plug boost line Yj+1 goes up black plug voltage to the four black plug thin film transistor (TFT) 403b that transmit.
Continuation is in conjunction with Fig. 2 and Fig. 3, and gate drivers 102 shows that to first thin film transistor (TFT) 103a, the first black plug thin film transistor (TFT) 103b, second show that thin film transistor (TFT) 203a, the second black plug thin film transistor (TFT) 203b, the 3rd show that thin film transistor (TFT) 303a, the 3rd black plug thin film transistor (TFT) 303b, the 4th show that thin film transistor (TFT) 403a, the 4th black plug thin film transistor (TFT) 403b control its unlatching or close being used for by sweep trace SL4i, SL4i+1, SL4i+2, SL4i+3, SL4i+4, SL4i+5 transmission of control signals voltage.When first shows that thin film transistor (TFT) 103a, second shows that thin film transistor (TFT) 203a, the 3rd shows that thin film transistor (TFT) 303a or the 4th shows that thin film transistor (TFT) 403a is unlocked, first liquid crystal capacitance 104 and first memory capacitance 105, second liquid crystal capacitance 204 and second memory capacitance 205, the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 or the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 are charged into (charging) data line DLj and are gone up the display voltage of transmitting, and are promptly charged into the required voltage of normal display frame to be used for showing normal pictures; As the first black plug thin film transistor (TFT) 103b, the second black plug thin film transistor (TFT) 203b, when the 3rd black plug thin film transistor (TFT) 303b or the 4th black plug thin film transistor (TFT) 403b are unlocked, first liquid crystal capacitance 104 and first memory capacitance 105, second liquid crystal capacitance 204 and second memory capacitance 205, the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 or the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 are respectively by the first black plug input end 106, the second black plug input end 206, the 3rd black plug input end 306 or the 4th black plug input end 406 are charged into the black plug voltage that transmits on the black plug boost line, are promptly charged into the required black plug voltage of black picture to be used for showing black picture.When thin film transistor (TFT) was closed, first liquid crystal capacitance 104 and first memory capacitance 105, second liquid crystal capacitance 204 and second memory capacitance 205, the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 or the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 entered voltage and keep the stage (holding time).
In the present embodiment, liquid crystal indicator is normal black pattern (Normally Black), black appliances pressure side 107 is transfused to common electric voltage Vcom, therefore the black plug input end is common electric voltage Vcom by the voltage that the black plug boost line receives, thereby when liquid crystal capacitance and memory capacitance were charged into common electric voltage Vcom on the black plug input end, liquid crystal indicator can show black picture.But the invention is not restricted to this, in other embodiments, when liquid crystal indicator also can be for normal white mode (Normally White), black appliances pressure side 107 is connected to high level or low level end, be transfused to high level or low level, therefore the black plug input end is high level or low level by the voltage that the black plug boost line receives, thereby when liquid crystal capacitance and memory capacitance were charged into high level on the black plug input end or low level, liquid crystal indicator can show black picture.
The driving method of the array base palte 10 of present embodiment liquid crystal indicator below will be described, for a better understanding of the present invention, in the present embodiment with most bar sweep trace SL0, SL1 ..., SL4n-1 is divided into 4 groups: first group of sweep trace comprise SL1, SL2 ..., SL4n-3, second group of sweep trace comprise SL2, SL6 ..., SL4n-2, the 3rd group of sweep trace comprise SL3, SL7 ..., SL4n-1, the 4th group of sweep trace comprise SL0, SL4 ..., SL4n-4, and it is similar to be positioned at same group sweep trace circuit connecting relation.Thereby in the superincumbent single picture element unit, sweep trace SL4i+1, SL4i+5 belong to first group of sweep trace, and sweep trace SL4i+2 belongs to second group of sweep trace, and sweep trace SL4i+3 belongs to the 3rd group of sweep trace, and sweep trace SL4i, SL4i+4 belong to the 4th group of sweep trace.
Fig. 4 is the process flow diagram of array base palte 10 driving methods of liquid crystal indicator, Fig. 5 is the drive waveforms figure of the array base palte 10 of liquid crystal indicator, please consult Fig. 2, Fig. 4, Fig. 5 simultaneously, with the driving method of the array base palte 10 of the liquid crystal indicator that is used for describing present embodiment.A picture frame (Frame) t0-t0 ' time period of liquid crystal indicator is divided into during 4 sequential: t3-t0 ' (consulting Fig. 5) during t2-t3 and the 4th sequential during t1-t2, the 3rd sequential during t0-t1, second sequential during first sequential, and four times that the sequential period average distributes a picture frame.In the present embodiment, the frequency of liquid crystal indicator is 60Hz, and promptly the length of t0-t0 ' time period is 16.67ms, and therefore, the time span during each sequential is 4.17 (16.67/4) ms.But the present invention do not limit what this, the frequency of liquid crystal indicator is that 120Hz, 240Hz etc. also are fine.
When during first sequential after t0 begins constantly, first group of sweep trace SL1, SL5, ..., SL4n-3 opened in regular turn in the t0-t1 time period, promptly at first sweep trace SL1 opens a duration of charging (charging time), sweep trace SL1 closes to enter the retention time (holding time) then, then sweep trace SL5 opens a duration of charging, sweep trace SL5 closes to enter the retention time then, the rest may be inferred, to the last first group of sweep trace SL4n-3 opens a duration of charging, sweep trace SL4n-3 closes to enter the retention time constantly at t1 then, finishes constantly at t1 during first sequential; Then begin constantly at t1 during second sequential, second group of sweep trace SL2, SL6, ..., SL4n-2 opened in regular turn in the t1-t2 time period, promptly at first sweep trace SL2 opens a duration of charging in the back constantly at t1, sweep trace SL2 closes to enter the retention time then, then sweep trace SL6 opens a duration of charging, sweep trace SL6 closes to enter the retention time then, the rest may be inferred, to the last second group of sweep trace SL4n-2 opens a duration of charging, sweep trace SL4n-2 closes to enter the retention time constantly at t2 then, finishes constantly at t2 during second sequential; Then begin constantly at t2 during the 3rd sequential, same the 3rd group of sweep trace SL3, SL7 ..., SL4n-1 opens in regular turn in the t2-t3 time period, close constantly at t3 during the 3rd sequential then; Begin constantly at t3 during last the 4th sequential, same the 4th group of sweep trace SL0, SL4 ..., SL4n-4 opens in regular turn in the t3-t0 ' time period, constantly close at t0 ' during the 4th sequential then.This picture frame finishes constantly at t0 ', and next picture frame is carved beginning at this moment.
More than briefly introduced the driving method of sweep trace, promptly sweep trace SL0, SL1 ..., SL4n-1 is divided into 4 groups and drives in regular turn, describes the driving method of the array base palte 10 of liquid crystal indicator in detail below in conjunction with Fig. 3.See also Fig. 3, Fig. 4 and Fig. 5, in a picture frame, at first carry out step S10, during first sequential after t0 begins constantly, first group of sweep trace SL1, SL5 ..., SL4n-3 opens in regular turn.After 4i+1 bar sweep trace SL4i+1 is unlocked, first of the first pixel P1 (being positioned at the capable pixel of 2i+1) that links to each other with sweep trace SL4i+1 shows that thin film transistor (TFT) 103a is switched on, therefore, the normal display voltage that j bar data line DLj transmits is filled in first liquid crystal capacitance 104 and first memory capacitance 105 of the first pixel P1 that links to each other with sweep trace SL4i+1, and the first pixel P1 that promptly links to each other with sweep trace SL4i+1 is charged into normal display voltage; Simultaneously, the 3rd pixel P3 that links to each other with sweep trace SL4i+1 (not showing among Fig. 3), i.e. the 3rd pixel P3 (being positioned at the capable pixel of 2i) in the lastrow pixel of the first pixel P1, the 3rd black plug thin film transistor (TFT) 303b (not illustrating among Fig. 3) also be switched on simultaneously, therefore, the black plug voltage Vcom of the auxiliary black plug line Yj transmission of j bar is filled into the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 of the 3rd pixel P3 that links to each other with sweep trace SL4i+1 by the 3rd black plug input end 306.Sweep trace SL4i+1 is after continuing a duration of charging, and sweep trace SL4i+1 is closed, and the current potential that first pixel P1 that links to each other with sweep trace SL4i+1 and the 3rd pixel P3 enter normal pictures and black picture respectively keeps the stage.Carry out the driving of follow-up first group of sweep trace then.Can know that thus during first sequential, the first pixel P1 is charged into normal display voltage, simultaneously, the 3rd pixel P3 is charged into black plug voltage Vcom, and its design sketch is asked for an interview Fig. 6 a.
Carry out step S20 then, during second sequential after t1 begins constantly, second group of sweep trace SL2, SL6 ..., SL4n-2 opens in regular turn.After 4i+2 bar sweep trace SL4i+2 is unlocked, second of the second pixel P2 (being positioned at the capable pixel of 2i+1) that links to each other with sweep trace SL4i+2 shows that thin film transistor (TFT) 203a is switched on, therefore, the normal display voltage that j bar data line DLj transmits is filled in second liquid crystal capacitance 204 and second memory capacitance 205 of the second pixel P2 that links to each other with sweep trace SL4i+2, and the second pixel P2 that promptly links to each other with sweep trace SL4i+2 is charged into normal display voltage; Simultaneously, the 4th pixel P4 that links to each other with sweep trace SL4i+2, i.e. the 4th pixel P4 (being positioned at the capable pixel of 2i+2) in the next line pixel of the second pixel P2, the 4th black plug thin film transistor (TFT) 403b also be switched on, therefore, the black plug voltage Vcom that the auxiliary black plug line Yj+1 of j+1 bar transmits is filled into the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 of the 4th pixel P4 that links to each other with sweep trace SL4i+2 by the 4th black plug input end 406, and the 4th pixel P4 that promptly links to each other with sweep trace SL4i+2 is charged into black plug voltage Vcom.Sweep trace SL4i+2 is after continuing a duration of charging, and sweep trace SL4i+2 is closed, and the current potential that second pixel P2 that links to each other with sweep trace SL4i+2 and the 4th pixel P4 enter normal pictures and black picture respectively keeps the stage.Carry out the driving of follow-up second group of sweep trace then.Can know that thus during second sequential, the second pixel P2 is charged into normal display voltage, simultaneously, the 4th pixel P4 is charged into black plug voltage Vcom, and its design sketch is asked for an interview Fig. 6 b.
Carry out step S30 once more, during the 3rd sequential after t2 begins constantly, the 3rd group of sweep trace SL3, SL7 ..., SL4n-1 opens in regular turn.After 4i+3 bar sweep trace SL4i+3 is unlocked, the 3rd of the 3rd pixel P3 (being positioned at the capable pixel of 2i+2) that links to each other with sweep trace SL4i+3 shows that thin film transistor (TFT) 303a is switched on, therefore, the normal display voltage that j bar data line DLj transmits is filled into the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305 of the 3rd pixel P3 that links to each other with sweep trace SL4i+3, and the 3rd pixel P3 that promptly links to each other with sweep trace SL4i+3 is charged into normal display voltage; Simultaneously, the first pixel P1 that links to each other with sweep trace SL4i+3, the i.e. first pixel P1 (being positioned at the capable pixel of 2i+1) in the lastrow pixel of the 3rd pixel P3, the first black plug thin film transistor (TFT) 103b also be switched on, therefore, the black plug voltage Vcom that j bar black plug boost line Yj transmits is filled into the first liquid crystal capacitance 104a and the first memory capacitance 105a of the first pixel P1 that links to each other with sweep trace SL4i+3 by the first black plug input end 106, the first pixel P1 that promptly links to each other with sweep trace SL4i+3 is charged into black plug voltage Vcom, therefore, before the normal display voltage that (step S10) is input to the first pixel P1 that links to each other with sweep trace SL4i+1 during first sequential was replaced by black plug voltage Vcom, therefore, during the time that the first pixel P1 that links to each other with sweep trace SL4i+1 (being the first pixel P1 that links to each other with sweep trace SL4i+1) remains normal display voltage is two sequential: during first sequential and during second sequential, be the half the time of a picture frame.Sweep trace SL4i+3 is after continuing a duration of charging, and sweep trace SL4i+3 is closed, link to each other with sweep trace SL4i+3 the 3rd pixel P3 and the first pixel P1 enter the current potential maintenance stage respectively.Carry out the driving of follow-up the 3rd group of sweep trace then.Can know that thus during the 3rd sequential, the 3rd pixel P3 is charged into normal display voltage, simultaneously, the first pixel P1 is charged into black plug voltage, and its design sketch is asked for an interview Fig. 6 c.
Carry out step S40 at last, during the 4th sequential after t3 begins constantly, the 4th group of sweep trace SL0, SL4 ..., SL4n-4 opens in regular turn.After 4i+4 bar sweep trace SL4i+4 is unlocked (for more convenient and intuitively the statement, replace SL4i to be described with the 4th group SL4i+4), the 4th of the 4th pixel P4 (being positioned at the capable pixel of 2i+2) that links to each other with sweep trace SL4i+4 shows that thin film transistor (TFT) 403a is switched on, therefore, the normal display voltage that j bar data line DLj transmits is filled into the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405 of the 4th pixel P4 that links to each other with sweep trace SL4i+4, the 4th pixel P4 that promptly links to each other with sweep trace SL4i+4 is charged into normal display voltage, therefore, before the black plug voltage Vcom that (step S20) is input to the 4th pixel P4 that links to each other with sweep trace SL4i+2 during second sequential was replaced by normal display voltage, therefore, during the time that the 4th pixel P4 that links to each other with sweep trace SL4i+2 remains black plug voltage Vcom is two sequential: during second sequential and during the 3rd sequential, be the half the time of a picture frame; Simultaneously, the second pixel P2 that links to each other with sweep trace SL4i+4 (if existence), the i.e. second pixel P2 (being positioned at the capable pixel of 2i+3) in the next line pixel of the 4th pixel P4, the second black plug thin film transistor (TFT) 203b (not illustrating among Fig. 3) also be switched on, the second black plug thin film transistor (TFT) 203b of the second pixel P2 that links to each other with sweep trace SL4i+4 also is switched on, therefore, the black plug voltage Vcom that j+1 bar black plug boost line Yj+1 transmits is filled in second liquid crystal capacitance 204 and second memory capacitance 205 of the second pixel P2 that links to each other with sweep trace SL4i+4 by the second black plug input end 206, and the second pixel P2 that promptly links to each other with sweep trace SL4i+4 is charged into black plug voltage Vcom.Sweep trace SL4i+4 is after continuing a duration of charging, and sweep trace SL4i+4 is closed, and the 4th pixel P4 that links to each other with sweep trace SL4i+4 and the second pixel P2 enter current potential respectively and keep the stage.Carry out the driving of follow-up the 4th group of sweep trace then.Can know that thus during the 4th sequential, the 4th pixel P2 is charged into normal display voltage, simultaneously, the second pixel P2 is charged into black plug voltage Vcom, and its design sketch is asked for an interview Fig. 6 d.After t0 ' finished constantly, next picture frame began at t0 ' according to above-mentioned driving method constantly during the 4th sequential.
By above driving method as can be known, during first sequential the first pixel P1 is charged into normal display voltage, those first pixels P1 is charged into black plug voltage during the 3rd sequential, then, during first sequential of next picture frame, again those first pixels P1 is charged into normal display voltage, circulation according to this, therefore, the first pixel P1 is remaining normal display voltage during first sequential He during second sequential, remaining black plug voltage during the 3rd sequential He during the 4th sequential, promptly the first pixel P1 remains normal display voltage at the half the time of a picture frame, remains black plug voltage at the other half the time of a picture frame; Equally, during second sequential second pixel P2 is charged into normal display voltage, those second pixels P2 is charged into black plug voltage during the 4th sequential, then, during second sequential of next picture frame, again those second pixels P2 is charged into normal display voltage, circulation according to this, therefore, the second pixel P2 is remaining normal display voltage during second sequential He during the 3rd sequential, remaining black plug voltage during the 4th sequential and during first sequential of next picture frame, promptly the second pixel P2 remains normal display voltage at the half the time of a picture frame, remains black plug voltage at the other half the time of a picture frame; Equally, the 3rd pixel P3 is remaining normal display voltage during the 3rd sequential He during the 4th sequential, remaining black plug voltage during first sequential He during second sequential, promptly the 3rd pixel P3 remains normal display voltage at the half the time of a picture frame, remains black plug voltage at the other half the time of a picture frame; Equally, the 4th pixel P4 is remaining normal display voltage during the 4th sequential and during first sequential of next picture frame, remaining black plug voltage during second sequential He during the 3rd sequential, promptly the 4th pixel P4 remains normal display voltage at the half the time of a picture frame, other half the time at a picture frame remains black plug voltage, therefore, the present invention is by the design to liquid crystal display structure and driving method thereof, all picture elements half the time in a picture frame in the array base palte 10 is used for showing that normal picture shows, half the time is used for showing black picture in addition, therefore, the present invention need not increase the insertion that the picture frame frequency just can realize black picture.
In sum, the present invention is provided with two thin film transistor (TFT)s in a pixel, a thin film transistor (TFT) is used for controlling charging into of normal display voltage, the another one thin film transistor (TFT) is used for controlling charging into of black plug voltage, and, a pixel being carried out normal voltage when charging into, simultaneously the another one pixel is charged into black plug voltage.And, in the driving method of the array base palte of liquid crystal indicator of the present invention, half the time pixel at a picture frame remains normal display voltage, remain black plug voltage in other half the time pixel, therefore the present invention realizes inserting does not need to increase frequency when deceiving picture, therefore, the time of a picture frame of liquid crystal indicator of the present invention does not reduce, therefore, total duration of charging, (charging time) can not reduce yet, the problem of the picture element duration of charging deficiency that case is mentioned before therefore can not occurring.
Second embodiment
Fig. 7 is the electrical block diagram of the array base palte 20 of second embodiment of the invention liquid crystal indicator, Fig. 8 is the detailed circuit diagram of a picture element unit of present embodiment, the electrical block diagram of Fig. 7 and Fig. 8 is similar to the electrical block diagram of Fig. 2 and Fig. 3 respectively, therefore, components identical symbology components identical.The difference of the present embodiment and first embodiment is the electric connection setting of the first black plug input end 116, the second black plug input end 216, the 3rd black plug input end 316 and the 4th black plug input end 416.
Particularly, see also Fig. 7, in the present embodiment, liquid crystal indicator is normal white mode (Normally White), and the array base palte 20 of liquid crystal indicator does not have the black plug boost line of embodiment 1, therefore, in the present embodiment can not be by the black plug boost line through black plug input end input black plug voltage.Please merge and consult Fig. 7 and Fig. 8, the source electrode of the first black plug thin film transistor (TFT) 103b of the first picture element P1 links to each other with the first black plug input end 116, and the grid of the first black plug thin film transistor (TFT) 103b and the first black plug input end 116 all are connected to same sweep trace SL4i+3, and drain is connected to first liquid crystal capacitance 104 and first memory capacitance 105.The source electrode of the second black plug thin film transistor (TFT) 203b of the second picture element P2 links to each other with the second black plug input end 216, and the grid of the second black plug thin film transistor (TFT) 203b and the second black plug input end 216 all are connected to same sweep trace SL4i, and drain is connected to second liquid crystal capacitance 204 and second memory capacitance 205.The source electrode of the 3rd black plug thin film transistor (TFT) 303b of the 3rd picture element P3 links to each other with the 3rd black plug input end 316, and the grid of the 3rd black plug thin film transistor (TFT) 303b and the 3rd black plug input end 316 all are connected to same sweep trace SL4i+5, and drain is connected to the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305.The source electrode of the 4th black plug thin film transistor (TFT) 403b of the 4th picture element P4 links to each other with the 4th black plug input end 416, and the grid of the 4th black plug thin film transistor (TFT) 403b and the 4th black plug input end 416 all are connected to same sweep trace SL4i+2, and drain is connected to the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405.Therefore, when the first black plug thin film transistor (TFT) 103b, the second black plug thin film transistor (TFT) 203b, the 3rd black plug thin film transistor (TFT) 303b and the 4th black plug thin film transistor (TFT) 403b are switched on, corresponding liquid crystal electric capacity and memory capacitance are charged into the cut-in voltage that transmits on the sweep trace by the black plug input end, because liquid crystal indicator is normal white mode (Normally White), therefore, after liquid crystal capacitance and memory capacitance are charged into the cut-in voltage that transmits on the sweep trace, corresponding pixel is shown as black, has therefore realized the insertion of black picture.
In addition, the driving method of the array base palte 20 of present embodiment liquid crystal indicator is similar to the driving method of first embodiment, just black plug voltage is not to be input to liquid crystal capacitance and memory capacitance by the black plug boost line through the black plug input end, but be input to liquid crystal capacitance and memory capacitance through the black plug input end by sweep trace, therefore do not repeat them here, equally, the liquid crystal indicator of present embodiment does not need to increase frequency when realizing inserting black picture, therefore, total duration of charging, (charging time) can not reduce, the problem of the picture element duration of charging deficiency that case is mentioned before therefore can not occurring.
The 3rd embodiment
Fig. 9 is the electrical block diagram of the array base palte 30 of third embodiment of the invention liquid crystal indicator, Figure 10 is the detailed circuit diagram of a picture element unit of present embodiment, the electrical block diagram of Fig. 9 and Figure 10 is similar to the electrical block diagram of Fig. 2 and Fig. 3 respectively, therefore, components identical symbology components identical.The difference of the present embodiment and first embodiment is the electric connection setting of the first black plug input end 126, the second black plug input end 226, the 3rd black plug input end 326 and the 4th black plug input end 426.
See also Fig. 9, in the present embodiment, liquid crystal indicator is normal black pattern (Normally Black), and the array base palte 30 of liquid crystal indicator does not have the black plug boost line of embodiment 1, therefore, in the present embodiment can not be by the black plug boost line through black plug input end input black plug voltage.The array base palte 30 of liquid crystal indicator comprise most bar common electrode lines V0, V1 ..., V2n-2, and the voltage that transmits on the common electrode lines is common electric voltage Vcom, be connected to common electric voltage Vcom end jointly, prior art person should be appreciated that this majority bar common electrode lines V1, V2 ..., V2n-1 is connected to the other end of storage capacitors, therefore do not repeat them here.In the present embodiment because liquid crystal indicator be often to deceive pattern, therefore, can utilize common electrode wire V0, V1 ..., the common electric voltage Vcom of the last transmission of V2n-2 realizes the input of black plug voltage.
Particularly, please merge and consult Fig. 9 and Figure 10, the grid of the first black plug thin film transistor (TFT) 103b of the first picture element P1 is connected to sweep trace SL4i+3, source electrode links to each other with the first black plug input end 126, and the first black plug input end 126 is connected to common electrode lines V2i, and drain is connected to first liquid crystal capacitance 104 and first memory capacitance 105; The grid of the second black plug thin film transistor (TFT) 203b of the second picture element P2 is connected to corresponding sweep trace SL4i, source electrode is connected to the second black plug input end 226, and the second black plug input end 226 is connected to common electrode lines V2i, and drain is connected to second liquid crystal capacitance 204 and second memory capacitance 205; The grid of the 3rd black plug thin film transistor (TFT) 303b of the 3rd picture element P3 is connected to sweep trace SL4i+5, source electrode links to each other with the 3rd black plug input end 326, and the 3rd black plug input end 326 is connected to common electrode lines V2i+1, and drain is connected to the 3rd liquid crystal capacitance 304 and the 3rd memory capacitance 305; The grid of the 4th black plug thin film transistor (TFT) 403b of the 4th picture element P4 is connected to corresponding sweep trace SL4i+2, source electrode is connected to the 4th black plug input end 426, and the 4th black plug input end 426 is connected to common electrode lines V2i+1, and drain is connected to the 4th liquid crystal capacitance 404 and the 4th memory capacitance 405.Therefore, as the first black plug thin film transistor (TFT) 103b, the second black plug thin film transistor (TFT) 203b, when the 3rd black plug thin film transistor (TFT) 303b or the 4th black plug thin film transistor (TFT) 403b are switched on, corresponding liquid crystal electric capacity and memory capacitance are charged into common electrode lines V2i+1 by the black plug input end respectively and are gone up the common electric voltage Vcom that carries, because liquid crystal indicator is normal black pattern (Normally Black), therefore, after liquid crystal capacitance and memory capacitance are charged into the common electric voltage Vcom that transmits on the common electrode wire, corresponding pixel is shown as black, therefore realizes the insertion of black picture.
In addition, the driving method of the array base palte 30 of present embodiment liquid crystal indicator is similar to the driving method of first embodiment, just black plug voltage is not to be input to liquid crystal capacitance and memory capacitance by the black plug boost line through the black plug input end, but be input to liquid crystal capacitance and memory capacitance through the black plug input end by common electrode wire, therefore do not repeat them here.Equally, the liquid crystal indicator of present embodiment does not need to increase frequency when realizing inserting black picture, and therefore, total duration of charging, (charging time) can not reduce, the problem of the picture element duration of charging deficiency that case is mentioned before therefore can not occurring.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. the array base palte of a liquid crystal indicator comprises:
One first picture element comprises:
One first liquid crystal capacitance and one first memory capacitance, wherein this first liquid crystal capacitance, one end links to each other with this first memory capacitance, one end, and this first liquid crystal capacitance other end links to each other with this first memory capacitance other end and is connected to common electric voltage Vcom end;
One first shows thin film transistor (TFT), and the source electrode of this first demonstration thin film transistor (TFT) is connected to a data line, and drain connects an end of above-mentioned this first liquid crystal capacitance and an end of this first memory capacitance, and grid is connected to one second sweep trace (SL4i+1);
One first black plug thin film transistor (TFT), the source electrode of this first black plug thin film transistor (TFT) connects one first black plug voltage input end, drain connects an end of above-mentioned this first liquid crystal capacitance and an end of this first memory capacitance, and also be connected to first and show drain of film transistor, grid is connected to one the 4th sweep trace (SL4i+3);
One second picture element comprises:
One second liquid crystal capacitance and one second memory capacitance, wherein this second liquid crystal capacitance, one end links to each other with this second memory capacitance, one end, and this second liquid crystal capacitance other end links to each other with this second memory capacitance other end and is connected to common electric voltage Vcom end;
One second shows thin film transistor (TFT), and the source electrode of this second demonstration thin film transistor (TFT) is connected to this data line, and drain connects an end of above-mentioned this second liquid crystal capacitance and an end of this second memory capacitance, and grid is connected to a three scan line (SL4i+2);
One second black plug thin film transistor (TFT), the source electrode of this second black plug thin film transistor (TFT) connects one second black plug voltage input end, drain connects an end of this second liquid crystal capacitance and an end of this second memory capacitance, and also be connected to second and show drain of film transistor, grid is connected to one first sweep trace (SL4i);
One the 3rd picture element comprises:
One the 3rd liquid crystal capacitance and one the 3rd memory capacitance, wherein the 3rd liquid crystal capacitance one end links to each other with the 3rd memory capacitance one end, and the 3rd liquid crystal capacitance other end links to each other with the 3rd memory capacitance other end and is connected to common electric voltage Vcom end;
One the 3rd shows thin film transistor (TFT), and the 3rd shows that the source electrode of thin film transistor (TFT) is connected to this data line, and drain connects an end of above-mentioned the 3rd liquid crystal capacitance and an end of the 3rd memory capacitance, and grid is connected to the 4th sweep trace (SL4i+3);
One the 3rd black plug thin film transistor (TFT), the source electrode of the 3rd black plug thin film transistor (TFT) connects one the 3rd black plug voltage input end, drain connects an end of above-mentioned the 3rd liquid crystal capacitance and an end of the 3rd memory capacitance, and also be connected to the 3rd and show drain of film transistor, grid is connected to one the 6th sweep trace (SL4i+5);
One the 4th picture element comprises:
One the 4th liquid crystal capacitance and one the 4th memory capacitance, wherein the 4th liquid crystal capacitance one end links to each other with the 4th memory capacitance one end, and the 4th liquid crystal capacitance other end links to each other with the 4th memory capacitance other end and is connected to common electric voltage Vcom end;
One the 4th shows thin film transistor (TFT), and the 4th shows that the source electrode of thin film transistor (TFT) is connected to this data line, and drain connects an end of above-mentioned the 4th liquid crystal capacitance and an end of the 4th memory capacitance, and grid is connected to one the 5th sweep trace (SL4i+4);
One the 4th black plug thin film transistor (TFT), the source electrode of the 4th thin film transistor (TFT) connects one the 4th black plug voltage input end, drain connects an end of the 4th liquid crystal capacitance and an end of the 4th memory capacitance, and also be connected to the 4th and show drain of film transistor, grid is connected to this three scan line (SL4i+2).
2. the array base palte of liquid crystal indicator as claimed in claim 1, wherein this array base palte more comprises a black plug boost line, this black plug boost line and this data line are provided with at interval.
3. the array base palte of liquid crystal indicator as claimed in claim 2, wherein this black plug boost line comprises odd number black plug boost line and even number black plug boost line, this odd number black plug boost line is connected to this first and the 3rd black plug voltage input end, and this even number black plug boost line is connected to this second and the 4th black plug voltage input end.
4. the array base palte of liquid crystal indicator as claimed in claim 3, wherein this odd number black plug boost line is connected common electric voltage Vcom end with even number black plug auxiliary series.
5. the array base palte of liquid crystal indicator as claimed in claim 3, wherein this odd number black plug boost line is connected high level or low level end with even number black plug auxiliary series.
6. the array base palte of liquid crystal indicator as claimed in claim 1, wherein this array base palte also comprises a common line, this common line is connected to this first, second, third and the 4th black plug voltage input end respectively.
7. the array base palte of liquid crystal indicator as claimed in claim 1, wherein this first black plug voltage input end is connected to described the 4th sweep trace (SL4i+3), this second black plug voltage input end connects the described first sweep trace SL4i, the 3rd black plug voltage input end is connected to described the 6th sweep trace (SL4i+5), and the 4th black plug voltage input end is connected to described three scan line (SL4i+2).
8. the driving method of the array base palte of liquid crystal indicator according to claim 1 comprises:
During one first sequential, drive most bar second sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, first liquid crystal capacitance of first pixel is charged into normal voltage, and simultaneously, the 3rd liquid crystal capacitance of the 3rd pixel is charged into black voltage;
During one second sequential, drive most articles of three scan lines in regular turn to open corresponding thin film transistor (TFT), therefore, second liquid crystal capacitance of second pixel is charged into normal voltage, and simultaneously, the 4th liquid crystal capacitance of the 4th pixel is charged into black plug voltage;
During one the 3rd sequential, drive most articles the 4th sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, the 3rd liquid crystal capacitance of the 3rd pixel is charged into normal voltage, and simultaneously, first liquid crystal capacitance of first pixel is charged into black plug voltage;
During one the 4th sequential, drive most articles the 5th sweep traces in regular turn to open corresponding thin film transistor (TFT), therefore, the 4th liquid crystal capacitance of the 4th pixel is charged into normal voltage, and simultaneously, second liquid crystal capacitance of second pixel is charged into black plug voltage.
9. the driving method of the array base palte of liquid crystal indicator as claimed in claim 8, wherein during this first sequential, during second sequential, during the 3rd sequential and the summation during the 4th sequential equal 16.67 milliseconds.
10. the driving method of the array base palte of liquid crystal indicator as claimed in claim 8, wherein during this first sequential, equal in fact during second sequential, during the 3rd sequential with the time during the 4th sequential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100448368A CN102081270B (en) | 2011-02-23 | 2011-02-23 | Liquid crystal display device and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100448368A CN102081270B (en) | 2011-02-23 | 2011-02-23 | Liquid crystal display device and driving method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102081270A true CN102081270A (en) | 2011-06-01 |
| CN102081270B CN102081270B (en) | 2012-07-18 |
Family
ID=44087316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100448368A Expired - Fee Related CN102081270B (en) | 2011-02-23 | 2011-02-23 | Liquid crystal display device and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102081270B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819157A (en) * | 2012-08-06 | 2012-12-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| US9097950B2 (en) | 2012-08-06 | 2015-08-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and apparatus having the liquid crystal display panel |
| CN105554423A (en) * | 2013-04-24 | 2016-05-04 | 青岛海信电器股份有限公司 | Display device and television |
| CN105676511A (en) * | 2016-04-01 | 2016-06-15 | 京东方科技集团股份有限公司 | Display panel and driving method thereof as well as display device |
| CN108319049A (en) * | 2018-02-11 | 2018-07-24 | 武汉华星光电技术有限公司 | Liquid crystal display and liquid crystal display driving method |
| CN111025711A (en) * | 2020-01-02 | 2020-04-17 | 京东方科技集团股份有限公司 | Waveguide display liquid crystal driving circuit, liquid crystal display device and driving method |
| WO2020192056A1 (en) * | 2019-03-26 | 2020-10-01 | Boe Technology Group Co., Ltd. | Array substrate, display apparatus, and method of driving array substrate |
| CN113066436A (en) * | 2021-03-26 | 2021-07-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel, control method thereof and display device |
| CN117970686A (en) * | 2024-04-02 | 2024-05-03 | 惠科股份有限公司 | Display panel and display device |
| CN118016025A (en) * | 2024-04-09 | 2024-05-10 | 惠科股份有限公司 | Display panel, driving method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050088386A1 (en) * | 2003-10-28 | 2005-04-28 | Chien-Hsien Kao | [liquid crystal display panel and driving circuit thereof] |
| TW200725534A (en) * | 2005-12-23 | 2007-07-01 | Innolux Display Corp | Method for driving liquid crystal display panel |
| CN101620353A (en) * | 2008-07-03 | 2010-01-06 | Nec液晶技术株式会社 | Liquid crystal display device and driving method of the same |
-
2011
- 2011-02-23 CN CN2011100448368A patent/CN102081270B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050088386A1 (en) * | 2003-10-28 | 2005-04-28 | Chien-Hsien Kao | [liquid crystal display panel and driving circuit thereof] |
| TW200725534A (en) * | 2005-12-23 | 2007-07-01 | Innolux Display Corp | Method for driving liquid crystal display panel |
| CN101620353A (en) * | 2008-07-03 | 2010-01-06 | Nec液晶技术株式会社 | Liquid crystal display device and driving method of the same |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819157A (en) * | 2012-08-06 | 2012-12-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| US9097950B2 (en) | 2012-08-06 | 2015-08-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and apparatus having the liquid crystal display panel |
| CN102819157B (en) * | 2012-08-06 | 2016-01-13 | 深圳市华星光电技术有限公司 | Display panels and display device |
| CN105554423A (en) * | 2013-04-24 | 2016-05-04 | 青岛海信电器股份有限公司 | Display device and television |
| CN105554423B (en) * | 2013-04-24 | 2019-08-02 | 青岛海信电器股份有限公司 | A kind of display device and television set |
| US10228606B2 (en) | 2016-04-01 | 2019-03-12 | Boe Technology Group Co., Ltd. | Display panel comprising liquid crystal molecules that are driven to create a right-angle liquid crystal prism and display apparatus and driving method thereof |
| CN105676511A (en) * | 2016-04-01 | 2016-06-15 | 京东方科技集团股份有限公司 | Display panel and driving method thereof as well as display device |
| CN108319049A (en) * | 2018-02-11 | 2018-07-24 | 武汉华星光电技术有限公司 | Liquid crystal display and liquid crystal display driving method |
| CN108319049B (en) * | 2018-02-11 | 2020-11-24 | 武汉华星光电技术有限公司 | Liquid crystal display and driving method thereof |
| WO2020192056A1 (en) * | 2019-03-26 | 2020-10-01 | Boe Technology Group Co., Ltd. | Array substrate, display apparatus, and method of driving array substrate |
| US11056057B2 (en) | 2019-03-26 | 2021-07-06 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate, display apparatus, and method of driving array substrate |
| CN111025711A (en) * | 2020-01-02 | 2020-04-17 | 京东方科技集团股份有限公司 | Waveguide display liquid crystal driving circuit, liquid crystal display device and driving method |
| CN113066436A (en) * | 2021-03-26 | 2021-07-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel, control method thereof and display device |
| CN117970686A (en) * | 2024-04-02 | 2024-05-03 | 惠科股份有限公司 | Display panel and display device |
| CN118016025A (en) * | 2024-04-09 | 2024-05-10 | 惠科股份有限公司 | Display panel, driving method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102081270B (en) | 2012-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102081270B (en) | Liquid crystal display device and driving method thereof | |
| US9483991B2 (en) | Liquid crystal display device and driving method thereof | |
| JP5951251B2 (en) | Display device | |
| CN1979318B (en) | Liquid crystal display | |
| US9865218B2 (en) | Display device | |
| US6822718B2 (en) | Liquid crystal display | |
| US8248357B2 (en) | Pixel driving circuit and a display device having the same | |
| CN102201209A (en) | Display device and driving method thereof | |
| JP5004415B2 (en) | Liquid crystal display device and driving method thereof | |
| CN106233367B (en) | Active-matrix substrate and the display device for having it | |
| JP2005292831A (en) | Liquid crystal display | |
| CN103293729A (en) | Liquid crystal display device, method of driving liquid crystal display device, and electronic apparatus | |
| CN106710560A (en) | Driving circuit for display panel and display device | |
| CN101601081A (en) | Liquid crystal indicator and driving method thereof | |
| US9886928B2 (en) | Gate signal line drive circuit | |
| CN101620353B (en) | Liquid crystal display device and driving method of the same | |
| KR20110075924A (en) | Liquid crystal display device | |
| KR101026809B1 (en) | Impulsive driving liquid crystal display and driving method thereof | |
| CN106502015B (en) | A kind of array substrate and its driving method, display device | |
| CN103426415A (en) | Drive circuit of liquid crystal display panel and waveform driving approach | |
| CN101546542B (en) | Liquid crystal display device, liquid crystal display method, display control device, and display control method | |
| CN101882430A (en) | Method for driving liquid crystal display device | |
| CN102763031B (en) | Liquid-crystal display device | |
| WO2009148006A1 (en) | Display device | |
| KR101147424B1 (en) | Display and method of operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120718 Termination date: 20210223 |