CN117936577A - GaN HEMT device with ohmic contact interface passivation layer and preparation method thereof - Google Patents
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Abstract
The present disclosure provides a GaN HEMT device with an ohmic contact interface passivation layer and a method for manufacturing the same, the GaN HEMT device comprising: a substrate layer (1); a buffer layer (2) grown on the upper surface of the substrate layer (1); the heterojunction structure layer (3) grows on the upper surface of the buffer layer (2), and two symmetrical epitaxial grooves are formed in the edge of the upper surface of the heterojunction structure layer (3); the contact resistance structure layer (4) grows in the epitaxial groove, and the thickness of the contact resistance structure layer is larger than the depth of the epitaxial groove, and the contact resistance structure layer sequentially comprises a material layer (41), a passivation layer (42) and a source drain metal layer (43) from bottom to top; and the grid metal layer (5) is grown on the upper surface of the heterojunction structure layer (3) and is positioned between the contact resistance structure layers (4). The present disclosure can reduce the metal-induced bandgap intermediate state density in the material layer (41) and passivate dangling bonds at the interface, mitigate the pinning effect of interface states on the fermi level, thereby reducing ohmic contact resistance, and realize a GaN-based HEMT with low ohmic contact resistance.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a GaN HEMT device with an ohmic contact interface passivation layer and a preparation method thereof.
Background
Gallium nitride (GaN) is taken as a member of a third-generation semiconductor material system, and has the unique advantages of adjustable wide band gap, high breakdown electric field, high saturation speed and the like; meanwhile, the High Electron Mobility Transistor (HEMT) can effectively exert the characteristics of a GaN material, and realize a high-performance high-frequency power device, so that the GaN-based HEMT becomes a research hot spot. However, with the development of the preparation technology of the GaN HEMT device, the key size of the GaN HEMT device is continuously reduced, and a series of factors restricting the improvement of the HEMT performance appear.
On the one hand, according to the small signal model of the GaN HEMT, the current gain cut-off frequency of the HEMT high-frequency performance is determined to be inversely related to the parasitic charge delay in the device, and the parasitic charge delay is proportional to the ohmic contact resistance of the device, namely, the higher the ohmic contact resistance is, the longer the parasitic charge delay of the HEMT is, and the more serious the current gain cut-off frequency is reduced. Meanwhile, ohmic contact resistance also restricts current output and voltage distribution of HEMTs, thereby affecting power performance. The effect of ohmic contact resistance on device performance is not negligible. On the other hand, with the improvement of requirements on high-frequency performance, integration level and the like of the device, the critical dimension of the GaN-based HEMT device is continuously reduced, and the contact area and the distance between the structures are also smaller and smaller. Consistent with Moore's law prediction, ohmic contact resistance in a device is inversely related to the square of the device size, and if not optimized, high ohmic contact resistance can seriously affect the device performance when the device size is small, resulting in reduced power performance, increased parasitic delay, degraded high frequency performance, and the like of HEMTs.
Disclosure of Invention
First, the technical problem to be solved
In view of the above, the present disclosure provides a GaN HEMT device with an ohmic contact interface passivation layer and a method for manufacturing the same, which are used to at least partially solve the problems of reduced power performance, increased parasitic delay, and degraded high frequency performance of HEMTs generated by high ohmic contact resistance in the current devices.
(II) technical scheme
To achieve the above object, a first aspect of the present disclosure provides a GaN HEMT device having an ohmic contact interface passivation layer, comprising: a substrate layer; a buffer layer grown on the upper surface of the substrate layer; the heterojunction structure layer grows on the upper surface of the buffer layer, and two symmetrical epitaxial grooves are formed at the edge of the upper surface of the heterojunction structure layer; the contact resistance structure layer is grown in the epitaxial groove, and the thickness of the contact resistance structure layer is larger than the depth of the epitaxial groove, and the contact resistance structure layer sequentially comprises a material layer, a passivation layer and a source drain metal layer from bottom to top; and the gate metal layer is grown on the upper surface of the heterojunction structure layer and is positioned between the contact resistance structure layers.
According to an embodiment of the present disclosure, the heterojunction structure layer sequentially comprises, from bottom to top: a channel layer, an insertion layer, a barrier layer and a cap layer.
According to an embodiment of the disclosure, the gate metal layer is a stripe structure.
According to an embodiment of the present disclosure, the material layer is an n-doped gallium nitride-based material.
According to an embodiment of the present disclosure, the depth of the epitaxial trench is less than the thickness of the heterojunction structure layer.
According to an embodiment of the present disclosure, the thickness of the material layer is greater than the depth of the epitaxial trench.
According to an embodiment of the present disclosure, the thickness of the buffer layer is 0nm to 100um.
According to the embodiment of the disclosure, the thickness of the channel layer is 0nm-100um, the thickness of the insertion layer is 0nm-50nm, the thickness of the barrier layer is 0nm-50nm, and the thickness of the cap layer is 0nm-50nm.
According to an embodiment of the disclosure, the thickness of the material layer is 0nm-100um, and the thickness of the passivation layer is 0nm-5nm.
The second aspect of the present disclosure provides a method for manufacturing a GaN HEMT device with an ohmic contact interface passivation layer, comprising: sequentially epitaxially depositing a buffer layer and a heterojunction structure layer on the upper surface of the substrate layer; etching the edge of the upper surface of the heterojunction structure layer to form two symmetrical epitaxial grooves; cleaning the surface of the epitaxial groove, and depositing a contact resistance structure layer in the epitaxial groove, wherein the thickness of the contact resistance structure layer is larger than the depth of the epitaxial groove, and the contact resistance structure layer sequentially comprises a material layer, a passivation layer and a source drain metal layer from bottom to top; and depositing a gate metal layer on the upper surface of the heterojunction structure layer and between the contact resistance structure layers.
(III) beneficial effects
The GaN HEMT device with the ohmic contact interface passivation layer and the preparation method thereof are provided, the interface passivation layer structure is innovatively added between the material layer and the source-drain metal layer, the metal-induced band gap intermediate state density in the material layer is reduced, dangling bonds at the interface are passivated, and the pinning effect of the interface state on the Fermi level is lightened, so that the aim of reducing the ohmic contact resistance is achieved, and the gallium nitride high-electron mobility transistor with low ohmic contact resistance is realized.
Drawings
Fig. 1 schematically illustrates a structural schematic diagram of a GaN HEMT device with an ohmic contact interface passivation layer provided by an embodiment of the present disclosure;
fig. 2 schematically illustrates a graph of contact resistance versus a regrown ohmic contact structure having a passivation layer structure and a passivation layer-free structure provided by embodiments of the present disclosure.
Reference numerals illustrate:
1-a substrate layer;
2-a buffer layer;
A 3-heterojunction structure layer;
31-a channel layer;
32-an interposer;
33-a barrier layer;
34-cap layer;
4-a contact resistance structure layer;
41-a material layer;
42-a passivation layer;
43-source drain metal layer;
5-gate metal layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Fig. 1 schematically illustrates a structural diagram of a GaN HEMT device with an ohmic contact interface passivation layer provided by an embodiment of the disclosure.
As shown in fig. 1, the GaN HEMT device with ohmic contact interface passivation layer includes: the semiconductor device comprises a substrate layer 1, a buffer layer 2, a heterojunction structure layer 3, a channel layer 31, an insertion layer 32, a barrier layer 33, a cap layer 34, a contact resistance structure layer 4, a material layer 41, a passivation layer 42, a source-drain metal layer 43 and a gate metal layer 5.
In the embodiment of the present disclosure, the buffer layer 2 is grown on the upper surface of the substrate layer 1; the heterojunction structure layer 3 grows on the upper surface of the buffer layer 2, and two symmetrical epitaxial grooves are formed at the edge of the upper surface of the heterojunction structure layer 3; the contact resistance structure layer 4 grows in the epitaxial groove, has a thickness larger than the depth of the epitaxial groove, and sequentially comprises a material layer 41, a passivation layer 42 and a source drain metal layer 43 from bottom to top; and a gate metal layer 5 grown on the upper surface of the heterojunction structure layer 3 and positioned between the contact resistance structure layers 4.
Aiming at the problem of the ohmic contact resistance in the GaN HEMT device with the ohmic contact interface passivation layer, the passivation layer 42 structure is introduced at the ohmic contact interface by combining the interface physical mechanism from the energy band structure of the ohmic contact interface. By selecting the material of the passivation layer 42 with a proper energy band structure and the proper thickness of the passivation layer 42, the metal-induced band gap intermediate state density in the material layer 41 is reduced, and the dangling bonds at the interface are passivated, so that the pinning effect of the interface state on the fermi level is reduced, the aim of reducing the ohmic contact resistance is fulfilled, and the low ohmic contact resistance structure is realized.
Alternatively, the material type of the substrate layer 1 includes, but is not limited to, one or more of SiC, sapphire, si, gaN, thereby providing more possibilities for the device, and a suitable substrate may be selected according to the specific application requirements. By means of the substrate layer 1, the growth of other layers can be better controlled, defects and impurities can be reduced, and the quality can be improved. Meanwhile, the stress distribution of other layers can be optimized, the stress concentration is reduced, and the stability and the reliability of the device are improved.
Optionally, a nucleation layer can be added between the substrate layer 1 and the buffer layer 2, and the nucleation layer has the main function of controlling the nucleation process of material growth and promoting more uniform, ordered and consistent growth of the material on the substrate.
In the embodiments of the present disclosure, the material type of the buffer layer 2 includes, but is not limited to, alN or GaN, and has a thickness of 0nm to 100um. By selecting a material of the buffer layer 2 with a suitable energy level, the energy level matching between the heterojunction structure layer 3 and the substrate layer 1 can be adjusted, thereby optimizing the electron transport characteristics of the transistor. Meanwhile, the carrier concentration of the heterojunction can be adjusted by selecting proper material and thickness of the buffer layer, so that the conductive characteristic of the transistor is further optimized.
In the embodiment of the present disclosure, the heterojunction structure layer 3 sequentially includes, from bottom to top: an insertion layer 32 may be added between the channel layer 31 and the barrier layer 33, and a cap layer 34 may be added above the barrier layer 33.
Further, the material type of the channel layer 31 includes, but is not limited to, gaN, alGaN or InGaN, and has a thickness of 0nm to 100um. The type of material of the interposer 32 includes, but is not limited to, alN, siN, or InN, and has a thickness of 0nm to 50nm. The type of material of the barrier layer 33 includes, but is not limited to AlN, inAlN, alGaN or InGaN, with a thickness of 0nm-50nm. The type of material of cap layer 34 includes, but is not limited to, gaN, alN, or SiN, and has a thickness of 0nm-50nm.
Specifically, the channel layer 31 causes electrons to accumulate near the interface of the channel layer 31 due to piezoelectric polarization and spontaneous polarization effects of the upper barrier layer 33 to form one or more two-dimensional electron gas channels, which are thin, have little thickness, but have high areal density and mobility. At the same time, the interposer 32 also provides a portion of the polarization effect while reducing interlayer stress and electron scattering and improving mobility.
The depth of the epitaxial groove is smaller than the thickness of the heterojunction structure layer 3, the depth range is 0-100um, and meanwhile, all other areas outside the device area are integrally etched, so that the height of the epitaxial groove is reduced by about 50nm, and the device is prevented from leaking to the periphery.
The heterojunction structure layer 3 can provide an effective electron transport channel. In the GaN HEMT device with the ohmic contact interface passivation layer, electrons are mainly transported in the channel layer 31, and by optimizing the material and energy level structure of the channel layer 31, the transport behavior of the electrons can be controlled, so that efficient electron injection and collection are realized. The barrier layer 33 plays a role in modulating an electric field in the heterojunction structure layer, and the electric field distribution can be changed by adjusting the thickness of the barrier layer 33, so that the transmission behavior of electrons is further affected. The insertion layer 32 can improve the interface quality between the channel layer 31 and the barrier layer 33, reduce the interface state density, and reduce the influence of interface scattering on electron transport, thereby improving the performance and stability of the transistor. Finally, cap layer 34 may protect barrier layer 33 from environmental effects, such as oxidation and corrosion. Meanwhile, the cap layer 34 can passivate the surface of the heterojunction structure layer 3, so that the surface state density is reduced, the surface leakage current is reduced, and the reliability and the stability of the transistor are improved.
Further, the contact resistance structure layer 4 is a low ohmic contact resistance structure layer and is prepared in an epitaxial groove formed by etching the heterojunction structure layer 3 as a source and drain structure of the GaN HEMT device having an ohmic contact interface passivation layer.
In the disclosed embodiment, material layer 41 is a regrown high concentration n-doped gallium nitride-based material, the material types include, but are not limited to GaN, alGaN, inGaN, thickness 0nm-100um, n-doped concentration 1e15cm -3-1e20cm-3, this concentration range is selected to provide greater flexibility for material layer 41, and suitable concentrations may be selected to optimize specific or primary performance of the device according to practical requirements. Meanwhile, when the thickness of the material layer 41 is smaller than the depth of the epitaxial groove, there may occur a case where the metal and material layer 41 is in a longitudinal direction or the material layer 41 is in poor contact with the two-dimensional electron gas in a lateral direction, and thus, the thickness of the material layer 41 is greater than the depth of the epitaxial groove.
Passivation layer 42 is formed on the surface of material layer 41 by methods including, but not limited to, surface treatment, deposition, epitaxy, sputtering, etc., of a material type including, but not limited to AlN, siN, tiO 2、Ga2O3、Al2O3 or TiN, 0nm to 5nm thick.
By introducing the passivation layer 42 over the material layer 41, the passivation layer 42 can realize low-resistance ohmic contact with the material layer 41 and the source-drain metal layer 43, reducing parasitic resistance in the transistor, which contributes to improving current driving capability of the transistor and reducing power consumption, thereby realizing a transistor having a passivation layer structure with low ohmic contact resistance.
Source drain metal layer 43 is deposited on passivation layer 42 and the types of materials include, but are not limited to, alloys of Ti/Au, al/Au, ti/Al/Ti/Au, ti/Al/Ni/Au, and the like. The source drain metal layer 43 forms an ohmic contact with the underlying passivation layer 42 and material layer 41.
The source drain metal layer 43 serves as a main current output and collection electrode of the transistor, and enables efficient and stable current transport, and electrons are led out from the inside of the transistor and transferred to an external circuit. Meanwhile, the source-drain metal layer 43 serves as a connection point between the transistor and an external circuit, enabling efficient integration of the transistor and the external circuit.
In the disclosed embodiment, the gate metal layer 5 is a bar-shaped structure, the cross section of which includes but is not limited to T-shape, square shape and other polygons, and the material types include but are not limited to Ni/Au, pt/Au, mo/Au, ni/Al/Ti/Au and other alloys. The gate metal layer 5 and the top layer structure of the heterojunction structure layer 3 form a Schottky barrier, the Schottky barrier can control the injection and transmission behaviors of electrons, and the effective regulation and control of the switching characteristics of the transistor can be realized by adjusting the height and the width of the barrier.
The embodiment of the disclosure provides a preparation method of a GaN HEMT device with an ohmic contact interface passivation layer, which specifically comprises S1-S4.
In operation S1, a buffer layer 2 and a heterojunction structure layer 3 are epitaxially deposited in this order on the upper surface of a substrate layer 1.
In operation S2, at the edge of the upper surface of the heterojunction structure layer 3, two epitaxial trenches are formed symmetrically.
In operation S3, the surface of the epitaxial trench is cleaned, and a contact resistance structure layer 4 is deposited in the epitaxial trench, wherein the thickness of the contact resistance structure layer 4 is greater than the depth of the epitaxial trench, and the contact resistance structure layer comprises a material layer 41, a passivation layer 42 and a source drain metal layer 43 from bottom to top.
Wherein passivation layer structure 42 is formed on the surface of the high concentration n-doped GaN-based material layer by methods including, but not limited to, surface annealing treatment, atomic layer deposition, MOCVD/MBE epitaxy, etc.
In operation S4, a gate metal layer 5 is deposited on the upper surface of the heterojunction structure layer 3 and between the contact resistance structure layers 4.
Example 1:
The substrate layer 1 is 2 inches in size and the material is sapphire. The material of the buffer layer 2 is Fe doped high-resistance GaN with the thickness of 200nm. The heterojunction structure layer 3 includes a channel layer 31, an insertion layer 32, a barrier layer 33, and a cap layer 34. Wherein the material of the channel layer 31 is GaN and the thickness is 2um. The material of the insertion layer 32 was AlN, and the thickness was 2nm. The material of the barrier layer 33 was in0.22al0.78n and the thickness was 6nm. The cap layer 34 is made of GaN and has a thickness of 2nm.
And etching the heterostructure layer 3 by adopting an ICP method to form a source/drain region epitaxial groove, wherein the depth is 70nm.
A gate metal layer 5 is deposited on the heterojunction structure layer 3, the material is Ni/Au, and the thickness is 80nm/120nm.
After cleaning the surface of the epitaxial groove, a material layer 41 is selectively grown in the epitaxial groove along the epitaxial growth direction to serve as a source-drain region of the GaN HEMT device with the ohmic contact interface passivation layer, the thickness is 90nm, and the doping concentration is 1e19cm -3.
An ohmic contact interface passivation layer 42 is obtained on the material layer 41 through surface air annealing and oxidation at 800 ℃, and the material of the passivation layer 42 is Ga 2O3, and the thickness is 1.5nm.
Alternatively, a Ga2O3 interface passivation layer 42 structure is grown on the material layer 41 by ALD epitaxy to a thickness of 1-2nm.
Alternatively, the structure of the TiO 2 interface passivation layer 42 is obtained by depositing a thin layer of metal Ti on the material layer 41 and then air oxidizing treatment, and the thickness is 1-2nm.
Alternatively, the structure of the TiO 2 interface passivation layer 42 is obtained by ALD epitaxial growth on the material layer 41, with a thickness of 1-2nm.
A source drain metal layer 43 is deposited on the passivation layer 42, and the material is Ti/Au, and the thickness is 70nm/130nm.
Fig. 2 schematically illustrates a graph of contact resistance versus a regrown ohmic contact structure having a passivation layer structure and a passivation layer-free structure provided by embodiments of the present disclosure.
As shown in fig. 2, by surface air oxidation treatment of the material layer 41, the contact resistance of the regrown ohmic contact structure of the Ga 2O3 passivation layer 42 having a thickness of 1-2nm is significantly reduced compared with the contact resistance of the regrown ohmic contact structure of the conventional interface-free passivation layer 42 structure, in which the contact resistance of the regrown ohmic contact structure having the passivation layer 42 is 0.01-0.035 Ω·mm, compared with the contact resistance of the conventional interface-free passivation layer 42 structure, in which 0.04-0.07 Ω·mm.
According to the GaN HEMT device with the ohmic contact interface passivation layer and the preparation method thereof, the process treatment is carried out on the existing device structure, on the basis of reducing the GaN HEMT ohmic contact resistance through the regrowth process, the ohmic contact resistance of the GaN HEMT device is further reduced through adding the passivation layer with the energy band structure and the proper thickness on the ohmic contact interface, so that a small-size device with lower parasitic resistance is realized, parasitic delay and output resistance are reduced, and the GaN HEMT device with the ohmic contact interface passivation layer with better power performance and high-frequency performance is obtained.
Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.
While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.
Claims (10)
1. A GaN HEMT device having an ohmic contact interface passivation layer, comprising:
a substrate layer (1);
A buffer layer (2) grown on the upper surface of the substrate layer (1);
The heterojunction structure layer (3) grows on the upper surface of the buffer layer (2), and two symmetrical epitaxial grooves are formed at the edge of the upper surface of the heterojunction structure layer (3);
The contact resistance structure layer (4) is grown in the epitaxial groove, and the thickness of the contact resistance structure layer is larger than the depth of the epitaxial groove, and the contact resistance structure layer sequentially comprises a material layer (41), a passivation layer (42) and a source-drain metal layer (43) from bottom to top;
and a gate metal layer (5) grown on the upper surface of the heterojunction structure layer (3) and positioned between the contact resistance structure layers (4).
2. The GaN HEMT device with ohmic contact interface passivation layer according to claim 1, wherein the heterojunction structure layer (3) comprises, in order from bottom to top:
A channel layer (31), an insertion layer (32), a barrier layer (33) and a cap layer (34).
3. The GaN HEMT device with ohmic contact interface passivation layer according to claim 2, wherein the gate metal layer (5) is a stripe-shaped structure.
4. The GaN HEMT device with ohmic contact interface passivation layer of claim 1, wherein the material layer (41) is an n-doped gallium nitride-based material.
5. The GaN HEMT device with ohmic contact interface passivation layer of claim 1, wherein the depth of the epitaxial trench is less than the thickness of the heterojunction structure layer (3).
6. The GaN HEMT device with ohmic contact interface passivation layer of claim 1, wherein the thickness of the material layer (41) is greater than the depth of the epitaxial trench.
7. The GaN HEMT device with ohmic contact interface passivation layer according to claim 1, wherein the buffer layer (2) has a thickness of 0nm-100um.
8. The GaN HEMT device with ohmic contact interface passivation layer of claim 2, wherein the channel layer (31) has a thickness of 0nm-100um, the insertion layer (32) has a thickness of 0nm-50nm, the barrier layer (33) has a thickness of 0nm-50nm, and the cap layer (34) has a thickness of 0nm-50nm.
9. The GaN HEMT device of claim 1 with ohmic contact interface passivation layer, wherein the material layer (41) has a thickness of 0nm-100um and the passivation layer (42) has a thickness of 0nm-5nm.
10. The preparation method of the GaN HEMT device with the ohmic contact interface passivation layer is characterized by comprising the following steps of:
A buffer layer (2) and a heterojunction structure layer (3) are sequentially epitaxially deposited on the upper surface of the substrate layer (1);
etching the edge of the upper surface of the heterojunction structure layer (3) to form two symmetrical epitaxial grooves;
Cleaning the surface of the epitaxial groove, and depositing a contact resistance structural layer (4) in the epitaxial groove, wherein the thickness of the contact resistance structural layer (4) is larger than the depth of the epitaxial groove, and the contact resistance structural layer sequentially comprises a material layer (41), a passivation layer (42) and a source-drain metal layer (43) from bottom to top;
a gate metal layer (5) is deposited on the upper surface of the heterojunction structure layer (3) and between the contact resistance structure layers (4).
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| CN202410070130.6A CN117936577A (en) | 2024-01-17 | 2024-01-17 | GaN HEMT device with ohmic contact interface passivation layer and preparation method thereof |
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| CN202410070130.6A Pending CN117936577A (en) | 2024-01-17 | 2024-01-17 | GaN HEMT device with ohmic contact interface passivation layer and preparation method thereof |
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| Country | Link |
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| CN (1) | CN117936577A (en) |
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