CN117936480A - 电子封装以及用于制造电子封装的方法 - Google Patents
电子封装以及用于制造电子封装的方法 Download PDFInfo
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Abstract
本申请提供一种电子封装。该电子封装包括基底,所述基底包括第一区域和第二区域;第一组电子部件,所述第一电子部件安装在所述基底的第一区域;第二组电子部件,所述第二电子部件安装在所述基底的第二区域;密封层,所述密封层设置在所述基底上并密封所述第一组电子部件和所述第二组电子部件;一组互连部件,所述互连部件设置在所述基底的所述第二区域,以及延伸穿过密封层,其中,所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件;以及连接器,所述连接器安装在所述密封层和通过所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件。
Description
技术领域
本申请总体上涉及半导体技术,更具体地,涉及一种电子封装以及用于制造电子封装的方法。
背景技术
近年来,使用毫米波信号(例如,具有24GHz到60GHz或更高频率)的无线通信面临着复杂的挑战,因为电子封装通常受成本、尺寸、重量以及性能规范的限制。因此,将带有系统和天线的5G天线封装(AIP)集成在一个封装中已被应用到手机或其他便携式多媒体设备中。然而,这种5G AIP需要更小的接口间距、更多的接口引脚数、更小的厚度以及更高级别的系统基础封装内的集成。
因此,需要一种制造具有改进集成度的电子封装的工艺。
发明内容
本申请的一个目的是提供一种改进集成度的电子封装的制造方法。
根据本申请实施例的一个方面,提供一种电子封装,包括基底,所述基底包括第一区域和第二区域;第一组电子部件,所述第一电子部件安装在所述基底的第一区域;第二组电子部件,所述第二电子部件安装在所述基底的第二区域;密封层,所述密封层设置在所述基底上并密封所述第一组电子部件和所述第二组电子部件;一组互连部件,所述互连部件设置在所述基底的所述第二区域,以及延伸穿过密封层,其中,所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件;以及连接器,所述连接器安装在所述密封层和通过所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件。
根据本申请实施例的一个方面,提供一种用于制造电子封装的方法,包括提供基底,所述基底包括第一区域和第二区域;将第一组电子部件安装在所述基底的第一区域;将第二组电子部件安装在所述基底的第二区域;将一组互连部件安装在所述基底的所述第二区域;在所述基底上形成密封层以密封所述第一组电子部件、所述第二组电子部件以及所述一组互连部件;形成穿过所述密封层的一组开口以露出所述一组互连部件;以及将连接器安装在所述一组互连部件上,其中所述连接器具有一组端子,所述端子分别与一组开口对齐,使得所述连接器通过所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件。
应当理解,前面的一般描述和下面的详细描述都只是示例性和说明性的,而不是对本发明的限制。此外,并入并构成本说明书一部分的附图说明了本发明的实施例并且与说明书一起用于解释本发明的原理。
附图说明
本文引用的附图构成说明书的一部分。附图中所示的特征仅图示了本申请的一些实施例,而不是本申请的所有实施例,除非详细描述另有明确说明,并且说明书的读者不应做出相反的暗示。
图1示出了传统电子封装100的立体图;
图2示出了根据本申请的实施例电子封装200的剖视图;
图3A至图3J示出了根据本申请的实施例制造一种电子封装方法的各个步骤;
图4A示出了根据本申请的实施例电子封装400的立体图;
图4B示出了如图4A所示的电子封装400移除连接器的立体图;
图5和图6示出了根据本申请的实施例的电子封装500和600的俯视图;
图7是根据本发明实施例的电子封装的制造方法流程图。
在整个附图中将使用相同的附图标记来表示相同或相似的部分。
具体实施方式
本申请示例性实施例的以下详细描述参考了形成描述的一部分的附图。附图示出了其中可以实践本申请的具体示例性实施例。包括附图在内的详细描述足够详细地描述了这些实施例,以使本领域技术人员能够实践本申请。本领域技术人员可以进一步利用本申请的其他实施例,并在不脱离本申请的精神或范围的情况下进行逻辑、机械等变化。因此,以下详细描述的读者不应以限制性的方式解释该描述,并且仅以所附权利要求限定本申请的实施例的范围。
在本申请中,除非另有明确说明,否则使用单数包括了复数。在本申请中,除非另有说明,否则使用“或”是指“和/或”。此外,使用术语“包括”以及诸如“包含”和“含有”的其他形式的不是限制性的。此外,除非另有明确说明,诸如“元件”或“部件”之类的术语覆盖了包括一个单元的元件和部件,以及包括多于一个子单元的元件和部件。此外,本文使用的章节标题仅用于组织目的,不应解释为限制所描述的主题。
如本文所用,空间上相对的术语,例如“下方”、“下面”、“上方”、“上面”、“上”、“上侧”、“下侧”、“左侧”、“右侧”、“水平”、“竖直”、“侧边”等等,可以在本文中使用,以便于描述如附图中所示的一个元件或特征与另一元件或特征的关系。除了图中描绘的方向之外,空间相对术语旨在涵盖设备在使用或操作中的不同方向。该器件可以以其他方式定向(旋转90度或在其他方向),并且本文使用的空间相关描述符同样可以相应地解释。应该理解,当一个元件被称为“连接到”或“耦接到”另一个元件时,它可以直接连接到或耦接到另一个元件,或者可以存在中间元件。
图1示出了传统的电子封装100。如图1所示,电子封装100包括基底101和安装在基底101上的多个电子部件(未示出)。密封层105形成在基底101上方以密封多个电子部件。电子封装100还包括连接器102,例如板对板连接器,其安装在基底101上并通过基底101内部的互连部件与由密封层105密封的其他电子部件电耦接。连接器102用于将电子封装100与电子封装100外部的其他电子器件电耦接。
如图1所示,连接器102与多个电子部件并排设置于基底101上,该排列方式所占用的空间较大,不适用于智能手机等先进电子系统。为了解决上述问题,本申请的发明人构思了一种电子封装的新设计,其中连接器可以堆叠在安装在基底上的一些较小的电子部件上,这可以减小电子封装的尺寸并使得制造的电子封装更紧凑。
图2示出了根据本申请实施例的电子封装200的剖视图。
如图2所示,电子封装200包括基底201。在一些实施例中,基底201可以是印刷电路板(PCB)并且可以包括再分布结构(RDS),其具有一个或多个介电层和一个或多个导电层,该导电层位于并穿过该电路板的介电层。该导电层可以定义焊盘、迹线和插座,电信号或电压可以通过它们在RDS上水平和垂直分布。在一些实施例中,RDS可以包括形成在基底201的顶面和底面两者或任一者上的多个导电图案。
多个电子部件安装在基底201上。在一些实施例中,多个电子部件可以包括一个或多个半导体芯片、半导体器件和/或分立器件。例如,电子部件可以包括数字信号处理器(DSP)、微控制器、微处理器、网络处理器、电源管理处理器、音频处理器、视频处理器、RF电路、无线基带系统。芯片(SoC)处理器、传感器、存储控制器、存储器件、专用集成电路等。电子部件也可以是无源器件,例如电容器、电感器或电阻器。
如图2所示,该多个电子部件包括第一组电子部件203和第二组电子部件204,两者均被密封层205密封。具体地,基底201包括第一区域2011和第二区域2012。第一组电子部件203安装在基底201的第一区域2011上,而第二组电子部件204安装在基底201的第二区域2012上。在本示例中,第一组电子部件203包括两个有源器件,例如RF集成电路(IC)芯片和电源管理IC芯片,它们具有更大的外形尺寸,而第二组电子部件204可以包括两个无源器件,例如电容器,它们具有更小的外形尺寸。由于第一组电子部件203高于第二组电子部件204,因此在第一区域2011中的密封层205的一部分可以比在第二区域2012中的密封层205的其他部分厚。此外,第一区域2011和第二区域2012之间的过渡区域可以形成在基底上,其可以包括在密封层205中的斜面或台阶。
如前所述,密封层205在第一区域2011中的厚度可以大于在第二区域2012中的厚度。因此,可以在第二区域2012中的密封层205上方形成间隙,这提供了空间用于容纳和安装在第二电子部件204上的连接器202,例如,板对板连接器。如图2所示,一组互连部件206安装在基底201的第二区域2012上,它们从基底201的顶面穿过密封层205基本上延伸到密封层205的顶面。具体地,一组互连部件206可以包括第一组互连部件2061和第二组互连部件2062。第一组互连部件2061形成在第二组电子部件204周围并且与基底201接触。此外,第二组互连部件2062分别堆叠在第一组互连部件2061上,并从第二区域2012中的密封层205中露出。第一组互连部件2061和第二组互连部件2062均通过在基底201的互连结构电耦接地连接第一组电子部件203和第二组电子部件204,以允许连接器202和基底201上的电子部件之间的电耦接。在实施例中,互连部件206的高度高于第二组电子部件204,因为需要互连部件206穿过密封层从而使连接器可以被安装在电子封装上,并与互连部件206连接。
该组互连部件206由导电材料制成,例如焊球、导电柱、铜柱、导电球或铜球,但本公开的方面不限于此。尽管互连部件206在图2所示的示例中被呈现为焊球,但是可以存在其他示例,其中一个或多个焊球可以是例如其他导电球、或导电柱、或导电端。该组互连部件206以任何适当的排列方式设置在第二组电子部件204周围。在图2所示的例子中,当从基底201的顶部观察时,多个焊球被排列成椭圆形状。在一些实施例中,互连部件206可以包括Sn、Ni、Al、Cu、Au、Ag或其他合适的中的一种或多种导电材料。第一组互连部件2061和第二组互连部件2062可以由相同材料或不同材料制成。
仍然参考图2,连接器202通过一组互连部件206和基底201内的互连结构电耦接到第一组电子部件203和第二组电子部件204。具体地,密封层205中的一组开口可以通过激光烧蚀形成,其中第一组互连部件2061可以在激光烧蚀之后露出来,然后将第二组互连部件安装在第一组互连部件2061上。连接器202包括一组端子,它们分别与第二组互连部件2062对齐。也就是说,互连部件206的布局或排列可以与连接器202的端子的布局或排列相同。这样,当连接器202安装在基底201上时,连接器202可以电耦接到第一组电子组件203和第二组电子部件204。在一些实施例中,互连部件的数量可以基于连接器的端子的数量来确定。
而且,电子封装200还可以包括屏蔽层207,其通常覆盖密封层205。在一些实施例中,在屏蔽层207中进一步形成一组开口,与密封层205中的一组开口对齐。因此,该组互连部件206可以延伸穿过密封层205和屏蔽层207以允许与连接器202连接。可以理解,屏蔽层207中的开口应该足够大,使得屏蔽层207可以不与任何互连部件206接触。在一些实施例中,屏蔽层207可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。在一些实施例中,屏蔽层207可以是羰基铁、不锈钢、镍银、低碳钢、硅铁钢、箔片、导电树脂、炭黑、铝片或其他能够还原的金属和导电材料,从而减少EMI、RFI和其他设备间干扰的影响。
此外,电子封装200还可以包括多个天线模块,例如贴片天线,其可以嵌入在基底201的背面(未示出)。在一些实施例中,多个天线模块可以形成在基底201中,而其他导电层位于基底201内。进一步地,如图2所示,多个介电构件208(208a、208b、208c、208d、208e)分别设置在基底201的背面并靠近多个天线模块,以改善多个天线模块中的射频(RF)信号通信。具体地,介电构件208(208a、208b、208c、208d、208e)可以增加多个天线模块的斜角发射和接收面积。此外,入射到介电构件208的RF信号可以根据介电构件208的介电常数Dk发生折射,这提高了天线模块的发射和接收率或增益。在一些实施例中,每个介电构件208可以具有半球形状、半椭圆形状、透镜形状或矩形形状。介电构件的形状可以根据RF信号的折射/衍射/反射特性的优化、高度标准、结构粘附稳定性和其他特性而变化。如图2所示,介电构件208(208a、208b、208c、208d、208e)呈现为矩形,但本公开的方面不限于此。
参考图3A至图3J,根据本申请的实施例说明了用于制造电子封装的方法300的各个步骤。例如,方法300可用于制造图2所示的电子封装200,在下文中,参考图3A至图3J将更详细地介绍该方法。
如图3A所示,提供基底301。之后,参考图3B所示,在基底301的背面嵌入多个天线模块,例如贴片天线(未示出),多个介电构件308a、308b、308c、308d和308e形成在多个天线模块上。在一些实施例中,每个介电构件可以通过切割介电块、将介电粉末注入模具中的固化工艺或通过介电透镜的中间切割来形成。在一些实施例中,介电构件可由具有高介电常数Dk的材料形成,例如味之素堆积膜(ABF)、环氧树脂模塑料(EMC)、聚丙二醇(PPG)、玻璃、陶瓷、硅、覆铜板(CCL)、石英和特氟隆(Teflon)。
如图3C所示,将包括第一组电子部件303和第二组电子部件304的多个电子部件安装在基底301的上表面。第一组电子部件303高于第二组电子部件304。然后,将第一组焊球3061设置在第二组电子部件304周围,第一组焊球3061的高度低于第二组电子部件304。或者,第一组焊球3061可以由导电柱或其他合适的导电结构代替,如图3D所示。
如图3E所示,在基底上形成第一组焊球后,可形成密封层以密封基底及其上设置的各种元件。具体地,电子封装可以放置在底部模具310和顶部模具309之间。可以理解的是,模具309和310的侧壁并未示出。由此在底部模具309和顶部模具310之间形成腔室,在该腔室中可以执行密封层的模制工艺。顶部模具309可压靠底部模具310以形成模腔3091,例如,通过夹持以避免基底301在顶部模具309和底部模具310之间的相对移动。可以在适当的温度和压力下将密封材料注入模腔3091中以在基底上形成密封层。然后将密封材料固化例如,在热固化过程中形成如图3F所示的密封层305,可以理解的是,在第一区域3011中的密封层305的部分比在第二区域3012中的密封层305的其他部分厚,使得电子部件可以被密封层305适当地保护。
参考图3G,在密封层305上形成屏蔽层307,其中屏蔽层307为共形EMI屏蔽层,防止电子封装中的高频器件辐射或传输电磁噪声。特别地,形成EMI屏蔽层307以覆盖密封层305并向下延伸至基底301的侧壁。在一些实施例中,可以使用溅射或其他合适的金属沉积工艺来形成屏蔽层307。
之后,如图3H所示,通过激光烧蚀在第二区域3012内的密封层305的部分中形成对应于第一组焊球3061的一组开口311。然后附加导电填充料,例如将第二组焊球3062分别填充于一组开口311内,以将互连部件306升高至大体上高于密封层305和EMI屏蔽层307。具体而言,一组开口311中的每一个开口都可被烧蚀为碗形凹槽,该碗形凹槽为从密封层305的顶面凹陷入密封层305内的一定距离。该凹槽应该足够宽以将第二组焊球3062插入到开口311中,并且可以避免第二组焊球焊球3062和EMI屏蔽层307之间不需要的连接。可以理解的是,开口311可以形成为其他可选的形状,例如梯形。在一些实施例中,凹槽足够宽,可以使得在第二组焊球3062的露出部分与开口的侧壁之间存在间隙。在一些替代实施例中,开口311可以通过蚀刻、机械钻孔或任何其他合适的技术形成。在插入开口之后,焊球3062可以通过例如回流工艺与相应的焊球3061结合。
如图3I所示,连接器302安装在密封层305上方的第一区域中,并且连接器302的一组端子分别与第二组焊球3062对齐。在回流工艺之后,连接器302可以用第二组焊球3062固定,从而成为电子封装的一部分。
作为一些可选实施例中,可能需要散热盖以将热量从电子封装传递到周围环境。如图3J所示,可在第一区域3011的EMI屏蔽层307上附接散热盖313进行散热,并在散热盖313与EMI屏蔽层307之间涂敷导热材料314,稍后固化,从而作为热界面层314。
图4A示出了根据本申请实施例的电子封装400的立体图,而图4B示出为了便于说明,移除了连接器的电子封装400。从图4A可知,与图1所示的电子封装100相比,在将连接器402堆叠在安装在基底401上的一部分电子部件上之后,电子封装400的尺寸要小得多,因为连接器402不占用基底401上的额外空间。电子封装400的整体高度通常也不会增加,因为连接器402通常与它旁边的密封层405齐平。可以理解的是,如果选择了具有更大厚度的某种类型的连接器,则连接器402可以略高于密封剂层405的顶面,然而,连接器402的至少一部分可以嵌入密封层405内。
图4B示出了在将连接器附接到基底上之前的电子封装400的立体图。可以看出,第二组焊球4062或其他类似的互连部件从基底的第二区域中的密封层405露出。第二组焊球4062的排列可以与连接器的端子排列相同
在一些实施例中,尤其是当电子封装包括诸如电源电路IC芯片之类的大功率电子部件时,在运行期间可能会产生大量热量,尤其是在高功率电子部件的位置。因此,电子封装可能需要适当的散热装置,例如散热盖。图5和6示出了根据本申请的一些其他实施例的电子封装500和600的俯视图。
如图5所示,散热盖514附接在第一区域5011中的电子封装500的密封层上,用于散热。散热盖514通常可以覆盖整个第一区域5011,而不延伸到安装连接器502的第二区域5012中。
同样地,如图6所示,两个散热盖615附接在电子封装600的密封层上用于散热。在两个散热盖615下方,可以将两个各自的功率电路IC芯片安装在电子封装600的基底上。散热盖615因此可以帮助散发其下方的IC芯片产生的热量。此外,对于其他一些可能不会产生大量热量的小型电子部件或低功耗IC芯片,可能不需要专门的散热盖。
参照图7,其示出了根据本申请的实施例的用于制作电子封装的方法700的流程图。
如图7所示,方法700可以从方框710开始,提供分别在基底的第一区域的第一组电子部件和在基底的第二区域的第二组电子部件。然后,在方框720,将一组互连部件安装在基底的第二区域上。在方框730,在基底上形成密封层以密封第一组电子部件和第二组电子部件。在方框740,形成穿过密封层的一组开口以露出该组互连部件。在方框750,将连接器安装在互连部件上,使得连接器通过该组互连部件电耦接到第一组电子部件和第二组电子部件。
本文的讨论包括许多说明性的附图,这些附图显示了半导体器件的各个部分及其制造方法。为了说明清楚起见,这些图并未显示每个示例组件的所有方面。本文提供的任何示例器件和/或方法可以与本文提供的任何或所有其他器件和/或方法共享任何或所有特征。可以理解,在器件或方法中一者的上下文中描述的实施例对于其他器件或方法类似地有效。类似地,在器件的上下文中描述的实施例对于方法同样有效,反之亦然。在一个实施例的上下文中描述的特征可以相应地适用于其他实施例中相同或相似的特征。在一个实施例的上下文中描述的特征可以相应地适用于其他实施例,即使在这些其他实施例中没有明确描述。此外,在一个实施例的上下文中针对一个特征描述的增加和/或组合和/或替代可以相应地适用于其他实施例中的相同或相似特征。
本文已经参照附图描述了各种实施例。然而,显然可以对其进行各种修改和改变,并且可以实施另外的实施例,而不背离如所附权利要求中阐述的本发明的更广泛范围。此外,通过考虑说明书和本文公开的本发明的一个或多个实施例的实践,其他实施例对于本领域技术人员将是明显的。因此,本申请和本文中的实施例旨在仅被认为是示例性的,本发明的真实范围和精神由所附示例性权利要求的列表指示。
Claims (14)
1.一种电子封装,其特征在于,所述电子封装包括:
基底,所述基底包括第一区域和第二区域;
第一组电子部件,所述第一电子部件安装在所述基底的第一区域;
第二组电子部件,所述第二电子部件安装在所述基底的第二区域;
密封层,所述密封层设置在所述基底上并密封所述第一组电子部件和所述第二组电子部件;
一组互连部件,所述互连部件设置在所述基底的所述第二区域,以及延伸穿过所述密封层,其中,所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件;以及
连接器,所述连接器安装在所述密封层上,并通过所述一组互连部件电耦接到所述第一组电子部件和所述第二组电子部件。
2.根据权利要求1所述的电子封装,其特征在于,在所述第一区域的所述密封层的一部分比在所述第二区域的所述密封层的另一部分厚。
3.根据权利要求1所述的电子封装,其特征在于,所述一组互连部件设置在所述第二组电子部件的周围。
4.根据权利要求1所述的电子封装,其特征在于,所述一组互连部件是焊球或导电柱。
5.根据权利要求1所述的电子封装,其特征在于,所述连接器是板对板连接器。
6.根据权利要求1所述的电子封装,其特征在于,所述电子封装还包括:
屏蔽层,所述屏蔽层设置在所述密封层上,其中所述一组互连部件还延伸穿过所述屏蔽层,并且所述一组互连部件的至少一部分不电耦接至所述屏蔽层。
7.根据权利要求6所述的电子封装,其特征在于,所述电子封装还包括:
散热盖,所述散热盖附接在所述第一区域的所述屏蔽层上。
8.一种用于制造电子封装的方法,所述方法包括:
提供基底,所述基底包括第一区域和第二区域;
将第一组电子部件安装在所述基底的第一区域;
将第二组电子部件安装在所述基底的第二区域;
将一组互连部件安装在所述基底的所述第二区域;
在所述基底上形成密封层以密封所述第一组电子部件、所述第二组电子部件以及所述一组互连部件;
形成穿过所述密封层的一组开口以露出所述一组互连部件;以及
将连接器安装在所述一组互连部件上,其中所述连接器具有一组端子,所述端子分别与所述一组开口对齐,使得所述连接器通过所述一组互连部件电耦接所述第一组电子部件和所述第二组电子部件。
9.根据权利要求8所述的方法,其特征在于,在形成穿过所述密封层的一组开口之前,所述方法还包括:
在所述密封层上形成屏蔽层,其中,所述一组互连部件中的至少一部分没有电耦接到所述屏蔽层。
10.根据权利要求9所述的方法,所述方法还包括:
将散热盖附接在所述第一区域的屏蔽层上。
11.根据权利要求8所述的方法,在将所述连接器安装在所述密封层之前,所述方法还包括:
在所述一组开口内填充相应的导电填充物,以将所述一组互连部件升高到基本上高于所述密封层。
12.根据权利要求8所述的方法,其特征在于,在所述第一区域的所述密封层的一部分比在所述第二区域的所述密封层的另一部分厚。
13.根据权利要求8所述的方法,其特征在于,所述一组互连部件设置在所述第二组电子部件的周围。
14.根据权利要求8所述的方法,其特征在于,所述一组互连部件是焊球或导电柱。
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