CN117930555A - Array substrate, display panel and display device - Google Patents

Abstract

The array substrate, the display panel and the display device provided by the disclosure comprise a substrate, wherein the substrate comprises a display area, a binding area positioned at one side of the display area, a first non-display area positioned at one side of the display area far away from the binding area, and a second non-display area and a third non-display area which are respectively connected with the binding area and the first non-display area; a common voltage line extending in a first direction, the common voltage line extending from the display region to the binding region and the first non-display region; the first direction is the direction from the binding area to the first non-display area; a first common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the first common voltage line being connected to the common voltage line within the first non-display region; and a second common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the second common voltage line being connected to the first common voltage line within the first non-display region.

Description

Array substrate, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

The thin film transistor liquid crystal display (Thin Film Transistor Liquid CRYSTAL DISPLAY, TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation, portability, etc., has been rapidly developed in recent years, has gradually replaced the conventional cathode ray tube display device (Cathode Ray Tube display, CRT), and has been dominant in the current flat panel display market. At present, TFT-LCDs are widely used in various large, medium and small-sized products, and almost cover the main electronic products of the current information society, such as liquid crystal televisions, high definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigators, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and illusive displays.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate, a display panel and a display device, which are used for improving the compensation capability of the panel, so that the recovery speed of a coupled common voltage signal is improved, a series of defects such as line afterimage and the like are reduced, and the product competitiveness is improved.

The embodiment of the disclosure provides an array substrate, a display panel and a display device, and the specific scheme is as follows:

in one aspect, an embodiment of the present disclosure provides an array substrate, including:

The substrate comprises a display area, a binding area positioned at one side of the display area, a first non-display area positioned at one side of the display area far away from the binding area, and a second non-display area and a third non-display area which are respectively connected with the binding area and the first non-display area;

a common voltage line extending in a first direction, the common voltage line extending from the display region to the binding region and the first non-display region; the first direction is the direction from the binding area to the first non-display area;

A first common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the first common voltage line being connected to the common voltage line within the first non-display region;

And a second common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the second common voltage line being connected to the first common voltage line within the first non-display region.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a dimension of the display area along the second direction is a, and a symmetry axis of the display area extending along the first direction is a first symmetry axis;

The distance from the connection point of the second common voltage line and the first common voltage line to the first symmetry axis is more than or equal to 0 and less than or equal to a/6.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the second common voltage lines include two, the two second common voltage lines extend from the second non-display area and the third non-display area to the first non-display area, respectively, and the two second common voltage lines are symmetrically disposed about the first symmetry axis.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the second common voltage line is located at a side of the first common voltage line away from the display area.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the second common voltage line includes a connection portion extending in the first direction within the first non-display region;

The array substrate further includes a short line extending in the second direction in the first non-display region, the short line being connected to the first common voltage line at a side of the first common voltage line away from the display region, and the short line being disconnected at the connection portion.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, an antistatic structure is further included, and the short circuit line is connected to the first common voltage line through the antistatic structure.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the array substrate further includes a common electrode located in the display area, a third common voltage line located in the binding area, and a fourth common voltage line located at least in the second non-display area and/or the third non-display area;

the common electrode is connected with the common voltage line;

the common electrode comprises a far-end common electrode part close to the first non-display area, a near-end common electrode part close to the binding area and a middle-end common electrode part positioned between the near-end common electrode part and the far-end common electrode part;

The first common voltage line is connected to the distal common electrode portion, the third common voltage line is connected to the proximal common electrode portion, and the fourth common voltage line is connected to the middle common electrode portion.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, a feedback line located in the second non-display area and/or the third non-display area is further included, where the feedback line is connected to the distal common electrode portion.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the array substrate further includes a common electrode bus disposed surrounding the display area, and the first common voltage line, the third common voltage line, the fourth common voltage line, and the feedback line are connected to the common electrode through the common electrode bus, respectively.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, gate lines and data lines are disposed in the display area in a crossing manner;

the common voltage lines are arranged in the same layer as the data lines and alternately in the second direction;

the first common voltage line and the second common voltage line are respectively arranged on the same layer as the grid line and the data line;

The third common voltage line, the fourth common voltage line, the common voltage bus line, the feedback line and the gate line are arranged in the same layer.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the array substrate further includes a plurality of pixel electrodes arranged in an array in the display area, and two gate lines are included between two adjacent pixel electrodes arranged along the first direction.

Based on the same inventive concept, the embodiment of the disclosure provides a display panel, which comprises the array substrate provided by the embodiment of the disclosure, and a counter substrate opposite to the array substrate.

Based on the same inventive concept, the embodiment of the disclosure provides a display device, which comprises the display panel provided by the embodiment of the disclosure, and a backlight module positioned on the light incident side of the display panel.

The beneficial effects of the present disclosure are as follows:

the array substrate, the display panel and the display device provided by the embodiment of the disclosure comprise a substrate, wherein the substrate comprises a display area, a binding area positioned at one side of the display area, a first non-display area positioned at one side of the display area far away from the binding area, and a second non-display area and a third non-display area which are respectively connected with the binding area and the first non-display area; a common voltage line extending in a first direction, the common voltage line extending from the display region to the binding region and the first non-display region; the first direction is the direction from the binding area to the first non-display area; a first common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the first common voltage line being connected to the common voltage line within the first non-display region; and a second common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the second common voltage line being connected to the first common voltage line within the first non-display region. The present disclosure greatly improves compensation effects by adding a second common voltage line connected to a first common voltage line in a first non-display region, directly compensating the common voltage line, not indirectly compensating via a related common electrode (Com ITO), and has a good preventive effect on an afterimage.

Drawings

Fig. 1 is a schematic diagram of a pixel arrangement of a dual gate product according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of still another pixel arrangement of a dual gate product according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It is noted that in the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described in this disclosure with reference to cross-sectional views that are schematic illustrations of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing techniques and/or tolerances, will be expected. Thus, the embodiments described in this disclosure should not be construed as limited to the particular shapes of regions as illustrated in this disclosure but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat may typically have rough and/or nonlinear features; the sharp corners illustrated may be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their sizes and shapes are not intended to illustrate the precise shape of a region and are not to reflect an actual scale, so as to merely schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed description of known functions and known components.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.

In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected to, or intervening elements or layers may be present. When an element or layer is referred to as being "disposed on" a side of another element or layer, it can be directly on the side of the other element or layer, be directly connected to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The term "and/or" includes any and all combinations of one or more of the associated listed items.

The current display field is increasingly competitive, and the cost is reduced, so that the whole display field is realized. Compared with the conventional scheme of driving one column of sub-pixels by one data line, the Dual Gate (Dual Gate) product simultaneously drives a plurality of columns of sub-pixels by one data line, thereby reducing the number of data lines, reducing the total number of Source driving chips (Source ICs), greatly reducing the material cost, and being particularly suitable for medium-and large-sized display devices such as notebooks (notebooks), monitors (monitors), televisions (TVs) and the like.

Fig. 1 is a schematic diagram of a pixel arrangement of a dual gate (dual gate) product according to an embodiment of the disclosure. In fig. 1, a horizontal common voltage line (CL 1) which is in the same layer and is in the same material as the Gate Line (GL) and a vertical common voltage line (CL 2) which is in the same layer and is in the same material as the Data Line (DL) exist, the horizontal common voltage line (CL 1) and the vertical common voltage line (CL 2) are connected through a via hole to form a net shape, and the horizontal common voltage line (CL 1) and the vertical common voltage line (CL 2) are connected with the common electrode at the via hole, so that the uniformity of a common voltage signal (Com) is better, and after being coupled by the Data Line (DL), the recovery can be faster, thereby effectively improving the line afterimage.

As technology advances, there is a beginning need for a high resolution (HAR) for dual gate pixels, and to achieve this goal, the present disclosure provides a design (as shown in fig. 2) that removes the lateral common voltage line (CL 1). Since the lateral common voltage line (CL 1) is removed, the mesh common voltage line becomes a stripe shape, and at this time, only the common electrode is turned on in the lateral direction, and the common voltage signal (Com) of the display area cannot be effectively compensated, so that the common voltage signal (Com) cannot be quickly recovered after being coupled, and defects such as line afterimages occur.

In order to improve the above technical problems in the related art, an embodiment of the present disclosure provides an array substrate, and fig. 3 and fig. 4 are schematic structural diagrams of the array substrate provided by the embodiment of the present disclosure, and as can be seen from fig. 3 and fig. 4, the array substrate provided by the embodiment of the present disclosure may include:

A substrate 101, where the substrate 101 includes a display area AA, a binding area BA (may also be referred to as a lower frame) located at one side of the display area AA, a first non-display area BB1 (may also be referred to as an upper frame) located at one side of the display area AA away from the binding area BA, and a second non-display area BB2 (may also be referred to as a left frame) and a third non-display area BB3 (may also be referred to as a right frame) connected to the binding area BA and the first non-display area BB1, respectively; in some embodiments, the binding area BA may be electrically connected to at least one circuit board (for example, a flip chip film COF), the display area AA includes a plurality of sub-pixel areas (for example, a red sub-pixel area R, a green sub-pixel area G, and a blue sub-pixel area B) arranged in an array, and the pixel arrangement manner in the display area AA may adopt the dual gate structure shown in fig. 1 and 2, that is, two Gate Lines (GL) are included between two adjacent pixel electrodes P arranged along the first direction Y, where the two Gate Lines (GL) may have a lateral common voltage line (CL 1) or may not have a lateral common voltage line (CL 1), and the disclosure is not limited; optionally, the substrate 101 is a substrate that allows visible light to pass through, for example, glass, quartz, plastic, etc.;

A common voltage line 102 extending in the first direction Y, the common voltage line 102 extending from the display area AA to the binding area BA and the first non-display area BB1; the first direction Y is a direction pointed to the first non-display area BB1 by the binding area BA; alternatively, the common voltage line 102 is disposed in the same layer and material as the Data Line (DL), and the common voltage line 102 and the Data Line (DL) are alternately disposed between each column of the sub-pixel regions; the material of the common voltage line 102 may include a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the common voltage line 102 may have a single-layer structure or a stacked structure, for example, the common voltage line 102 has a stacked structure composed of a titanium metal layer/an aluminum metal layer/a titanium metal layer;

A first common voltage line 103 extending from the second non-display region BB2 and/or the third non-display region BB3 to the first non-display region BB1, the first common voltage line 103 being connected to the common voltage line 102 within the first non-display region BB1 to perform common voltage signal compensation on the common voltage line 102 at the side where the first display region BB1 is located; optionally, the first common voltage line 103 is disposed in the same layer and material as the Data Line (DL) and the Gate Line (GL), i.e., the first common voltage line 103 is a double-layer wiring to reduce the resistance of the first common voltage line 103 and improve the signal drop (IR drop) on the first common voltage line 103;

A second common voltage line 104 extending from the second non-display region BB2 and/or the third non-display region BB3 to the first non-display region BB1, the second common voltage line 104 being connected to the first common voltage line 103 within the first non-display region BB1 such that the second common voltage line 104 performs common voltage signal compensation on the common voltage line 102 in common with the first common voltage line 103 on the side of the first display region BB 1; in some embodiments, the second common voltage line 104 is disposed in the same layer and material as the Data Line (DL) and the Gate Line (GL), i.e., the second common voltage line 104 is a double-layer wiring, so that the resistance of the second common voltage line 104 can be reduced, and the signal drop (IR drop) on the second common voltage line 104 can be improved.

In the array substrate provided by the embodiment of the present disclosure, by adding the second common voltage line 104 connected to the first common voltage line 103 in the first non-display area BB1, the first common voltage line 103 and the second common voltage line 104 can be used to directly compensate the common voltage line 102, instead of indirectly compensating via the common electrode, so that the compensation effect is greatly improved, and the effect of preventing the line afterimage is very good.

In this disclosure, "same layer and same material" refers to a layer structure formed by forming a film layer for making a specific pattern by using the same film forming process and then forming by one patterning process using the same mask plate. I.e., one patterning process corresponds to one mask, also known as a reticle. Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular patterns in the formed layer structure may be continuous or discontinuous, and may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in fig. 4, the second common voltage lines 104 include two, the two second common voltage lines 104 extend from the second non-display area BB2 and the third non-display area BB3 to the first non-display area BB1, respectively, and the two second common voltage lines 104 are symmetrically disposed about the first symmetry axis MN (i.e., the symmetry axis in which the display area AA extends along the first direction Y), so that the second common voltage lines 104 are synchronously transferred from two sides of the second non-display area BB2 and the third non-display area BB3 to the first non-display area BB1 to compensate the common voltage lines 102, thereby improving the compensation efficiency. In addition, since only one second common voltage line 104 is additionally added in the second non-display area BB2 and the third non-display area BB3, and since the two second common voltage lines 104 are symmetrically arranged about the first symmetry axis MN, the wiring space of one second common voltage line 104 is increased in the first non-display area BB1, the influence on the panel frame is small, and the product specification can be ensured to be almost unchanged.

In some embodiments, as shown in fig. 4, for the far end, the number of the common voltage lines 102 connected to the first common voltage line 103 from the edge connection points 1, 5 to the intermediate connection point 3 is gradually increased, and the load (RC loading) is gradually increased, so that the voltage compensation effect on the common voltage line 102 is gradually weakened, and thus, the compensation cannot be effectively performed. Based on this, the present disclosure may set the distance d between the connection points 6, 7 of the second common voltage line 104 and the first common voltage line 103 and the first symmetry axis MN to be equal to or greater than 0 and equal to or less than a/6, in other words, the distance between the connection points 6, 7 is equal to or greater than 0 and equal to or less than a/3, where a represents the size of the display area AA along the second direction X, so that the compensation effect of the common voltage line 102 at the middle section of the side where the first non-display area BB1 is located can be effectively improved, thereby ensuring that the overall compensation effect uniformity of the first common voltage line 103 and the second common voltage line 104 on the common voltage line 102 is better.

In some embodiments, in the above-described array substrate provided in the embodiments of the present disclosure, as shown in fig. 4, in order to simplify the wiring, the second common voltage line 104 may be disposed at a side of the first common voltage line 103 away from the display area AA. Of course, in some examples, the second common voltage line 104 may be disposed between the first common voltage line 103 and the display area AA, and at this time, the second common voltage line 104 may be ensured to be disposed continuously by bridging connection using the pixel electrode layer or the like at the connection points 1 to 5.

In some embodiments, in the above-described array substrate provided in the embodiments of the present disclosure, as shown in fig. 3, the second common voltage line 104 includes a connection line portion 1041 extending in the first direction Y within the first non-display area BB 1; the array substrate further includes a short line 105 extending along the second direction X in the first non-display area BB1, so that the short line 105 is disconnected at the connection portion 1041 to avoid shorting the short line 105 to the connection portion 1041.

As can be seen from fig. 3, to ensure that the signal of the shorting line 105 is clear, the shorting line 105 may be connected to the first common voltage line 103 on a side of the first common voltage line 103 away from the display area AA, for example, the shorting line 105 is connected to the first common voltage line 103 through an antistatic structure 106. The anti-static structure 106 can disperse static electricity onto the first common voltage line 103, so as to avoid poor circuit caused by overlarge static electricity.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in fig. 4, the array substrate may further include a common electrode 107 located in the display area AA, a third common voltage line 108 located in the binding area BA, and a fourth common voltage line 109 located at least in the second non-display area BB2 and/or the third non-display area BB 3; alternatively, the common electrode 107 is connected to the common voltage line 102, and the common electrode 107 includes a distal common electrode portion 1071 adjacent to the first non-display region BB1, a proximal common electrode portion 1072 adjacent to the bonding region BA, and a middle common electrode portion 1073 between the proximal common electrode portion 1072 and the distal common electrode portion 1071; the first common voltage line 103 is connected to the distal common electrode portion 1071, the third common voltage line 108 is connected to the proximal common electrode portion 1072, and the fourth common voltage line 109 is connected to the middle common electrode portion 1073. In this way, the first common voltage line 103, the third common voltage line 108 and the fourth common voltage line 109 can be used to compensate the middle common electrode 1073 of the far common electrode 1071 and the near common electrode 1072, so that the uniformity of the common voltage signal is better, and the common voltage signal can be recovered quickly even after being coupled by the Data Line (DL), thereby effectively improving the line afterimage.

Note that, fig. 4 illustrates the common electrode 107 as a block electrode, and in some embodiments, the common electrode 107 may be a slit (slit) electrode, etc., which is not specifically limited in this disclosure.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in fig. 4, the feedback line 110 may be further included in the second non-display area BB2 and/or the third non-display area BB3, where the feedback line 110 is connected to the distal common electrode 1071, and optionally, the feedback line 110 is disposed in the same layer and the same material as the Gate Line (GL). In a specific implementation, the feedback line 110 may be connected to the common electrode 107 at 1/6 of the direction in which the first non-display area BB1 points to the binding area BA, by monitoring the common voltage waveform at that point, and compensating the three by a corresponding multiple in combination with different loads (RC loading) of the distal common electrode 1071, the middle common electrode 1073, and the proximal common electrode 1072, and in some embodiments, the compensation multiple of the distal common electrode 1071, the middle common electrode 1073, and the proximal common electrode 1072 decreases sequentially.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 4, the array substrate further includes a common electrode bus 111 disposed around the display area AA, and the first common voltage line 103, the third common voltage line 108, the fourth common voltage line 109, and the feedback line 110 are connected to the common electrode 107 through the common electrode bus 111, respectively. Optionally, the third common voltage line 108, the fourth common voltage line 109, and the common voltage bus line 111 are disposed in the same layer and material as the Gate Line (GL). The arrangement of the common electrode bus 111 can reduce the contact resistance of the first common voltage line 103, the third common voltage line 108, the fourth common voltage line 109, the feedback line 110 and the common electrode 107, and reduce the signal transmission loss between the first common voltage line 103, the third common voltage line 108, the fourth common voltage line 109, the feedback line 110 and the common electrode 107.

In some embodiments, as can be seen in fig. 3, the array substrate provided in the embodiments of the present disclosure may further include a gate driving circuit GOA, a ground line 112, and other essential components of the array substrate, which are understood by those of ordinary skill in the art, and are not described herein in detail, and should not be taken as a limitation of the present disclosure.

Based on the same inventive concept, the embodiment of the present disclosure provides a display panel, as shown in fig. 5, including the above-mentioned array substrate 001 provided by the embodiment of the present disclosure, and the opposite substrate 002 opposite to the array substrate 001.

In some embodiments, the opposite substrate 002 may include a Black Matrix (BM) having a grid structure, the Data Lines (DL), the transistors (TFT), and the Gate Lines (GL) are disposed in the black matrix region, and color resists may be disposed in the grid of the black matrix, and include a red color resist corresponding to the red sub-pixel region R, a blue color resist corresponding to the blue sub-pixel region B, and a green color resist corresponding to the green sub-pixel region G. In some embodiments, the color resistors may also be disposed on the array substrate, which is not limited by the disclosure.

In some embodiments, as shown in fig. 5, the display panel provided in the embodiments of the disclosure may further include a liquid crystal layer 003 between the array substrate 001 and the opposite substrate 002, a first polarizer 004 located on a side of the array substrate 001 away from the opposite substrate 002, and a second polarizer 005 located on a side of the opposite substrate 002 away from the array substrate 001, where a polarization direction of the first polarizer 004 and a polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in fig. 6, including the above-mentioned display panel PNL provided in the embodiment of the present disclosure, and a backlight module BLU located on a light incident side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side-in type backlight module. Alternatively, the side-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, and the like, which are stacked, and the light bar is located at one side of the light guide plate in the thickness direction of the light guide plate. The direct type backlight module can comprise a matrix light source, a reflecting sheet, a diffusion plate, a brightness enhancement film and the like, wherein the reflecting sheet, the diffusion plate, the brightness enhancement film and the like are arranged on the light emitting side of the matrix light source in a stacked mode, and the reflecting sheet comprises an opening which is opposite to the position of each lamp bead in the matrix light source. The beads in the light bar, the beads in the matrix light source may be Light Emitting Devices (LEDs), such as quantum dot light emitting devices.

In some embodiments, the beads may also be Micro light emitting devices (e.g., mini LEDs, micro LEDs), etc., which are self-emitting devices on the order of submillimeter or even micrometer, as are Organic Light Emitting Devices (OLEDs). It has a series of advantages of high brightness, ultra low delay, ultra large visible angle, etc. as the organic light emitting device. And because the inorganic luminescent device emits light based on a metal semiconductor with more stable property and lower resistance, the inorganic luminescent device has the advantages of lower power consumption, higher high temperature and low temperature resistance and longer service life compared with an organic luminescent device which emits light based on an organic substance. And when the miniature light-emitting device is used as a backlight source, a more precise dynamic backlight effect can be realized, the glare phenomenon caused between the bright and dark areas of the screen by the traditional dynamic backlight can be solved while the brightness and the contrast of the screen are effectively improved, and the visual experience is optimized.

In some embodiments, the display device provided by the embodiments of the present disclosure may be: projectors, 3D printers, virtual reality devices, cell phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators, smartwatches, fitness bracelets, personal digital assistants, and any other product or component having a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to: the system comprises a radio frequency unit, a network module, an audio output and input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), or the like. For example, the control chip may further include a memory, a power module, and the like, and realize power supply and signal input/output functions through wires, signal lines, and the like that are additionally provided. For example, the control chip may also include hardware circuitry, computer-executable code, and the like. The hardware circuitry may include conventional Very Large Scale Integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; the hardware circuitry may also include field programmable gate arrays, programmable array logic, programmable logic devices, or the like. In addition, the above-described structure does not constitute a limitation of the above-described display device provided by the embodiments of the present disclosure, in other words, more or less of the above-described components may be included in the above-described display device provided by the embodiments of the present disclosure, or some components may be combined, or different component arrangements may be included.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims (13)

1. An array substrate, characterized by comprising:

The substrate comprises a display area, a binding area positioned at one side of the display area, a first non-display area positioned at one side of the display area far away from the binding area, and a second non-display area and a third non-display area which are respectively connected with the binding area and the first non-display area;

a common voltage line extending in a first direction, the common voltage line extending from the display region to the binding region and the first non-display region; the first direction is the direction from the binding area to the first non-display area;

A first common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the first common voltage line being connected to the common voltage line within the first non-display region;

And a second common voltage line extending from the second non-display region and/or the third non-display region to the first non-display region, the second common voltage line being connected to the first common voltage line within the first non-display region.

2. The array substrate of claim 1, wherein the display area has a dimension a in the second direction, and the symmetry axis of the display area extending in the first direction is a first symmetry axis;

The distance from the connection point of the second common voltage line and the first common voltage line to the first symmetry axis is more than or equal to 0 and less than or equal to a/6.

3. The array substrate of claim 2, wherein the second common voltage line includes two, the two second common voltage lines extend from the second non-display region and the third non-display region to the first non-display region, respectively, and the two second common voltage lines are symmetrically disposed about the first symmetry axis.

4. The array substrate of claim 1 or 2, wherein the second common voltage line is located at a side of the first common voltage line remote from the display region.

5. The array substrate of claim 4, wherein the second common voltage line includes a connection portion extending in the first direction within the first non-display region;

The array substrate further includes a short line extending in the second direction in the first non-display region, the short line being connected to the first common voltage line at a side of the first common voltage line away from the display region, and the short line being disconnected at the connection portion.

6. The array substrate of claim 5, further comprising an anti-static structure through which the shorting line is connected to the first common voltage line.

7. The array substrate of any one of claims 1 to 3, 5, 6, further comprising a common electrode in the display region, a third common voltage line in the bonding region, and a fourth common voltage line in at least the second non-display region and/or the third non-display region;

the common electrode is connected with the common voltage line;

the common electrode comprises a far-end common electrode part close to the first non-display area, a near-end common electrode part close to the binding area and a middle-end common electrode part positioned between the near-end common electrode part and the far-end common electrode part;

The first common voltage line is connected to the distal common electrode portion, the third common voltage line is connected to the proximal common electrode portion, and the fourth common voltage line is connected to the middle common electrode portion.

8. The array substrate of claim 7, further comprising a feedback line at the second non-display region and/or the third non-display region, the feedback line being connected to the distal common electrode part.

9. The array substrate of claim 8, further comprising a common electrode bus line disposed around the display region, the first common voltage line, the third common voltage line, the fourth common voltage line, and the feedback line being connected to the common electrode through the common electrode bus line, respectively.

10. The array substrate of claim 9, wherein the gate lines and the data lines are disposed to cross in the display area;

the common voltage lines are arranged in the same layer as the data lines and alternately in the second direction;

the first common voltage line and the second common voltage line are respectively arranged on the same layer as the grid line and the data line;

The third common voltage line, the fourth common voltage line, the common voltage bus line, the feedback line and the gate line are arranged in the same layer.

11. The array substrate of claim 10, further comprising a plurality of pixel electrodes arranged in an array in the display area, wherein two of the gate lines are included between two adjacent pixel electrodes arranged in the first direction.

12. A display panel comprising the array substrate according to any one of claims 1 to 11, and an opposite substrate disposed opposite to the array substrate.

13. A display device comprising the display panel of claim 12, and a backlight module disposed on an incident side of the display panel.